From: Ard Biesheuvel <ardb@kernel.org>
To: linux-arm-kernel@lists.infradead.org
Cc: linux-efi@vger.kernel.org, Ard Biesheuvel <ardb@kernel.org>,
Zhen Lei <thunder.leizhen@huawei.com>,
Russell King <rmk+kernel@armlinux.org.uk>,
Santosh Shilimkar <santosh.shilimkar@ti.com>,
Linus Walleij <linus.walleij@linaro.org>,
Nicolas Pitre <nico@fluxnic.net>
Subject: [RFC/RFT PATCH 4/6] ARM: p2v: use relative references in patch site arrays
Date: Fri, 18 Sep 2020 13:31:00 +0300 [thread overview]
Message-ID: <20200918103102.18107-5-ardb@kernel.org> (raw)
In-Reply-To: <20200918103102.18107-1-ardb@kernel.org>
Free up a register in the p2v patching code by switching to relative
references, which don't require keeping the phys-to-virt displacement
live in a register.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
---
arch/arm/include/asm/memory.h | 6 +++---
arch/arm/kernel/head.S | 15 ++++++++-------
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index eb3c8e6e960a..4121662dea5a 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -187,7 +187,7 @@ extern const void *__pv_table_begin, *__pv_table_end;
__asm__("@ __pv_stub\n" \
"1: " instr " %0, %1, %2\n" \
" .pushsection .pv_table,\"a\"\n" \
- " .long 1b\n" \
+ " .long 1b - .\n" \
" .popsection\n" \
: "=r" (to) \
: "r" (from), "I" (__PV_BITS_31_24))
@@ -196,7 +196,7 @@ extern const void *__pv_table_begin, *__pv_table_end;
__asm__ volatile("@ __pv_stub_mov\n" \
"1: mov %R0, %1\n" \
" .pushsection .pv_table,\"a\"\n" \
- " .long 1b\n" \
+ " .long 1b - .\n" \
" .popsection\n" \
: "=r" (t) \
: "I" (__PV_BITS_7_0))
@@ -206,7 +206,7 @@ extern const void *__pv_table_begin, *__pv_table_end;
"1: adds %Q0, %1, %2\n" \
" adc %R0, %R0, #0\n" \
" .pushsection .pv_table,\"a\"\n" \
- " .long 1b\n" \
+ " .long 1b - .\n" \
" .popsection\n" \
: "+r" (y) \
: "r" (x), "I" (__PV_BITS_31_24) \
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index c2a912121e3e..d2bd3b258386 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -633,7 +633,7 @@ ENDPROC(__fixup_pv_table)
__fixup_a_pv_table:
adr r0, 3f
ldr r6, [r0]
- add r6, r6, r3
+ add r6, r6, r0
ldr r0, [r6, #HIGH_OFFSET] @ pv_offset high word
ldr r6, [r6, #LOW_OFFSET] @ pv_offset low word
mov r6, r6, lsr #24
@@ -651,7 +651,8 @@ __fixup_a_pv_table:
orr r6, r6, r7, lsl #12
orr r6, #0x4000
b .Lnext
-.Lloop: add r7, r3
+.Lloop: add r7, r4
+ add r4, #4
ldrh ip, [r7, #2]
ARM_BE8(rev16 ip, ip)
tst ip, #0x4000
@@ -681,28 +682,28 @@ ARM_BE8(rev16 ip, ip)
moveq r0, #PV_BIT22 @ set bit 22, mov to mvn instruction
b .Lnext
-.Lloop: ldr ip, [r7, r3]
+.Lloop: ldr ip, [r7, r4]
bic ip, ip, #PV_IMM8_MASK
tst ip, #PV_ROT_MASK @ check the rotation field
orrne ip, ip, r6 ARM_BE8(, lsl #24) @ mask in offset bits 31-24
biceq ip, ip, #PV_BIT22 @ clear bit 22
orreq ip, ip, r0 @ mask in offset bits 7-0
- str ip, [r7, r3]
+ str ip, [r7, r4]
+ add r4, r4, #4
#endif
.Lnext:
cmp r4, r5
- ldrcc r7, [r4], #4 @ use branch for delay slot
+ ldrcc r7, [r4] @ use branch for delay slot
bcc .Lloop
ret lr
ENDPROC(__fixup_a_pv_table)
.align
-3: .long __pv_offset
+3: .long __pv_offset - .
ENTRY(fixup_pv_table)
stmfd sp!, {r4 - r7, lr}
- mov r3, #0 @ no offset
mov r4, r0 @ r0 = table start
add r5, r0, r1 @ r1 = table size
bl __fixup_a_pv_table
--
2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Ard Biesheuvel <ardb@kernel.org>
To: linux-arm-kernel@lists.infradead.org
Cc: linux-efi@vger.kernel.org, Nicolas Pitre <nico@fluxnic.net>,
Linus Walleij <linus.walleij@linaro.org>,
Russell King <rmk+kernel@armlinux.org.uk>,
Santosh Shilimkar <santosh.shilimkar@ti.com>,
Zhen Lei <thunder.leizhen@huawei.com>,
Ard Biesheuvel <ardb@kernel.org>
Subject: [RFC/RFT PATCH 4/6] ARM: p2v: use relative references in patch site arrays
Date: Fri, 18 Sep 2020 13:31:00 +0300 [thread overview]
Message-ID: <20200918103102.18107-5-ardb@kernel.org> (raw)
In-Reply-To: <20200918103102.18107-1-ardb@kernel.org>
Free up a register in the p2v patching code by switching to relative
references, which don't require keeping the phys-to-virt displacement
live in a register.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
---
arch/arm/include/asm/memory.h | 6 +++---
arch/arm/kernel/head.S | 15 ++++++++-------
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index eb3c8e6e960a..4121662dea5a 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -187,7 +187,7 @@ extern const void *__pv_table_begin, *__pv_table_end;
__asm__("@ __pv_stub\n" \
"1: " instr " %0, %1, %2\n" \
" .pushsection .pv_table,\"a\"\n" \
- " .long 1b\n" \
+ " .long 1b - .\n" \
" .popsection\n" \
: "=r" (to) \
: "r" (from), "I" (__PV_BITS_31_24))
@@ -196,7 +196,7 @@ extern const void *__pv_table_begin, *__pv_table_end;
__asm__ volatile("@ __pv_stub_mov\n" \
"1: mov %R0, %1\n" \
" .pushsection .pv_table,\"a\"\n" \
- " .long 1b\n" \
+ " .long 1b - .\n" \
" .popsection\n" \
: "=r" (t) \
: "I" (__PV_BITS_7_0))
@@ -206,7 +206,7 @@ extern const void *__pv_table_begin, *__pv_table_end;
"1: adds %Q0, %1, %2\n" \
" adc %R0, %R0, #0\n" \
" .pushsection .pv_table,\"a\"\n" \
- " .long 1b\n" \
+ " .long 1b - .\n" \
" .popsection\n" \
: "+r" (y) \
: "r" (x), "I" (__PV_BITS_31_24) \
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index c2a912121e3e..d2bd3b258386 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -633,7 +633,7 @@ ENDPROC(__fixup_pv_table)
__fixup_a_pv_table:
adr r0, 3f
ldr r6, [r0]
- add r6, r6, r3
+ add r6, r6, r0
ldr r0, [r6, #HIGH_OFFSET] @ pv_offset high word
ldr r6, [r6, #LOW_OFFSET] @ pv_offset low word
mov r6, r6, lsr #24
@@ -651,7 +651,8 @@ __fixup_a_pv_table:
orr r6, r6, r7, lsl #12
orr r6, #0x4000
b .Lnext
-.Lloop: add r7, r3
+.Lloop: add r7, r4
+ add r4, #4
ldrh ip, [r7, #2]
ARM_BE8(rev16 ip, ip)
tst ip, #0x4000
@@ -681,28 +682,28 @@ ARM_BE8(rev16 ip, ip)
moveq r0, #PV_BIT22 @ set bit 22, mov to mvn instruction
b .Lnext
-.Lloop: ldr ip, [r7, r3]
+.Lloop: ldr ip, [r7, r4]
bic ip, ip, #PV_IMM8_MASK
tst ip, #PV_ROT_MASK @ check the rotation field
orrne ip, ip, r6 ARM_BE8(, lsl #24) @ mask in offset bits 31-24
biceq ip, ip, #PV_BIT22 @ clear bit 22
orreq ip, ip, r0 @ mask in offset bits 7-0
- str ip, [r7, r3]
+ str ip, [r7, r4]
+ add r4, r4, #4
#endif
.Lnext:
cmp r4, r5
- ldrcc r7, [r4], #4 @ use branch for delay slot
+ ldrcc r7, [r4] @ use branch for delay slot
bcc .Lloop
ret lr
ENDPROC(__fixup_a_pv_table)
.align
-3: .long __pv_offset
+3: .long __pv_offset - .
ENTRY(fixup_pv_table)
stmfd sp!, {r4 - r7, lr}
- mov r3, #0 @ no offset
mov r4, r0 @ r0 = table start
add r5, r0, r1 @ r1 = table size
bl __fixup_a_pv_table
--
2.17.1
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next prev parent reply other threads:[~2020-09-18 10:31 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-18 10:30 [RFC/RFT PATCH 0/6] ARM: p2v: reduce min alignment to 2 MiB Ard Biesheuvel
2020-09-18 10:30 ` Ard Biesheuvel
2020-09-18 10:30 ` [RFC/RFT PATCH 1/6] ARM: p2v: factor out shared loop processing Ard Biesheuvel
2020-09-18 10:30 ` Ard Biesheuvel
2020-09-18 10:30 ` [RFC/RFT PATCH 2/6] ARM: p2v: factor out BE8 handling Ard Biesheuvel
2020-09-18 10:30 ` Ard Biesheuvel
2020-09-18 10:30 ` [RFC/RFT PATCH 3/6] ARM: p2v: drop redundant 'type' argument from __pv_stub Ard Biesheuvel
2020-09-18 10:30 ` Ard Biesheuvel
2020-09-18 10:31 ` Ard Biesheuvel [this message]
2020-09-18 10:31 ` [RFC/RFT PATCH 4/6] ARM: p2v: use relative references in patch site arrays Ard Biesheuvel
2020-09-18 10:31 ` [RFC/RFT PATCH 5/6] ARM: p2v: switch to MOVW for Thumb2 and ARM/LPAE Ard Biesheuvel
2020-09-18 10:31 ` Ard Biesheuvel
2020-09-18 10:31 ` [RFC/RFT PATCH 6/6] ARM: p2v: reduce p2v alignment requirement to 2 MiB Ard Biesheuvel
2020-09-18 10:31 ` Ard Biesheuvel
2020-09-18 17:25 ` [RFC/RFT PATCH 0/6] ARM: p2v: reduce min alignment " Ard Biesheuvel
2020-09-18 17:25 ` Ard Biesheuvel
2020-09-19 23:49 ` Nicolas Pitre
2020-09-19 23:49 ` Nicolas Pitre
2020-09-20 7:50 ` Ard Biesheuvel
2020-09-20 7:50 ` Ard Biesheuvel
2020-09-20 8:57 ` Russell King - ARM Linux admin
2020-09-20 8:57 ` Russell King - ARM Linux admin
2020-09-20 10:06 ` Ard Biesheuvel
2020-09-20 10:06 ` Ard Biesheuvel
2020-09-20 15:34 ` Nicolas Pitre
2020-09-20 15:34 ` Nicolas Pitre
2020-09-20 8:55 ` Russell King - ARM Linux admin
2020-09-20 8:55 ` Russell King - ARM Linux admin
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