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From: Daniel Palmer <daniel@0x0f.com>
To: linux-arm-kernel@lists.infradead.org
Cc: devicetree@vger.kernel.org, arnd@arndb.de, maz@kernel.org,
	Daniel Palmer <daniel@0x0f.com>,
	linux-kernel@vger.kernel.org, mark-pk.tsai@mediatek.com
Subject: [PATCH 2/3] ARM: mstar: Add interrupt controller to base dtsi
Date: Fri, 18 Sep 2020 19:49:48 +0900	[thread overview]
Message-ID: <20200918104949.3260823-3-daniel@0x0f.com> (raw)
In-Reply-To: <20200918104949.3260823-1-daniel@0x0f.com>

Add the IRQ and FIQ intc instances to the base MStar/SigmaStar v7
dtsi. All of the known SoCs have both and at the same place with
their common IPs using the same interrupt lines.

Signed-off-by: Daniel Palmer <daniel@0x0f.com>
---
 arch/arm/boot/dts/mstar-v7.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi
index 3b7b9b793736..aec841b52ca4 100644
--- a/arch/arm/boot/dts/mstar-v7.dtsi
+++ b/arch/arm/boot/dts/mstar-v7.dtsi
@@ -85,6 +85,25 @@ reboot {
 				mask = <0x79>;
 			};
 
+			intc_fiq: interrupt-controller@201310 {
+				compatible = "mstar,mst-intc";
+				reg = <0x201310 0x40>;
+				#interrupt-cells = <3>;
+				interrupt-controller;
+				interrupt-parent = <&gic>;
+				mstar,irqs-map-range = <96 127>;
+			};
+
+			intc_irq: interrupt-controller@201350 {
+				compatible = "mstar,mst-intc";
+				reg = <0x201350 0x40>;
+				#interrupt-cells = <3>;
+				interrupt-controller;
+				interrupt-parent = <&gic>;
+				mstar,irqs-map-range = <32 95>;
+				mstar,intc-no-eoi;
+			};
+
 			l3bridge: l3bridge@204400 {
 				compatible = "mstar,l3bridge";
 				reg = <0x204400 0x200>;
-- 
2.27.0


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WARNING: multiple messages have this Message-ID (diff)
From: Daniel Palmer <daniel@0x0f.com>
To: linux-arm-kernel@lists.infradead.org
Cc: devicetree@vger.kernel.org, mark-pk.tsai@mediatek.com,
	arnd@arndb.de, maz@kernel.org, linux-kernel@vger.kernel.org,
	Daniel Palmer <daniel@0x0f.com>
Subject: [PATCH 2/3] ARM: mstar: Add interrupt controller to base dtsi
Date: Fri, 18 Sep 2020 19:49:48 +0900	[thread overview]
Message-ID: <20200918104949.3260823-3-daniel@0x0f.com> (raw)
In-Reply-To: <20200918104949.3260823-1-daniel@0x0f.com>

Add the IRQ and FIQ intc instances to the base MStar/SigmaStar v7
dtsi. All of the known SoCs have both and at the same place with
their common IPs using the same interrupt lines.

Signed-off-by: Daniel Palmer <daniel@0x0f.com>
---
 arch/arm/boot/dts/mstar-v7.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi
index 3b7b9b793736..aec841b52ca4 100644
--- a/arch/arm/boot/dts/mstar-v7.dtsi
+++ b/arch/arm/boot/dts/mstar-v7.dtsi
@@ -85,6 +85,25 @@ reboot {
 				mask = <0x79>;
 			};
 
+			intc_fiq: interrupt-controller@201310 {
+				compatible = "mstar,mst-intc";
+				reg = <0x201310 0x40>;
+				#interrupt-cells = <3>;
+				interrupt-controller;
+				interrupt-parent = <&gic>;
+				mstar,irqs-map-range = <96 127>;
+			};
+
+			intc_irq: interrupt-controller@201350 {
+				compatible = "mstar,mst-intc";
+				reg = <0x201350 0x40>;
+				#interrupt-cells = <3>;
+				interrupt-controller;
+				interrupt-parent = <&gic>;
+				mstar,irqs-map-range = <32 95>;
+				mstar,intc-no-eoi;
+			};
+
 			l3bridge: l3bridge@204400 {
 				compatible = "mstar,l3bridge";
 				reg = <0x204400 0x200>;
-- 
2.27.0


  parent reply	other threads:[~2020-09-18 10:51 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-18 10:49 [PATCH 0/3] ARM: mstar: wire up interrupt controllers Daniel Palmer
2020-09-18 10:49 ` Daniel Palmer
2020-09-18 10:49 ` [PATCH 1/3] ARM: mstar: Select MStar intc Daniel Palmer
2020-09-18 10:49   ` Daniel Palmer
2020-09-18 10:49 ` Daniel Palmer [this message]
2020-09-18 10:49   ` [PATCH 2/3] ARM: mstar: Add interrupt controller to base dtsi Daniel Palmer
2020-09-18 10:49 ` [PATCH 3/3] ARM: mstar: Add interrupt to pm_uart Daniel Palmer
2020-09-18 10:49   ` Daniel Palmer
2020-09-18 11:34 ` [PATCH 0/3] ARM: mstar: wire up interrupt controllers Arnd Bergmann
2020-09-18 11:34   ` Arnd Bergmann
2020-09-18 11:43   ` Daniel Palmer
2020-09-18 11:43     ` Daniel Palmer

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