From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
To: Huacai Chen <chenhc@lemote.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Marc Zyngier <maz@kernel.org>,
linux-mips@vger.kernel.org, Fuxin Zhang <zhangfx@lemote.com>,
Huacai Chen <chenhuacai@gmail.com>,
Jiaxun Yang <jiaxun.yang@flygoat.com>
Subject: Re: [PATCH V2 1/2] MIPS: Loongson64: Increase NR_IRQS to 320
Date: Fri, 18 Sep 2020 15:51:39 +0200 [thread overview]
Message-ID: <20200918135139.GD19202@alpha.franken.de> (raw)
In-Reply-To: <1599819978-13999-1-git-send-email-chenhc@lemote.com>
On Fri, Sep 11, 2020 at 06:26:17PM +0800, Huacai Chen wrote:
> Modernized Loongson64 uses a hierarchical organization for interrupt
> controllers (INTCs), all INTC nodes (not only leaf nodes) need some IRQ
> numbers. This means 280 (i.e., NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256)
> is not enough to represent all interrupts, so let's increase NR_IRQS to
> 320 (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + NR_MAX_CHAINED_IRQS + 256).
>
> Signed-off-by: Huacai Chen <chenhc@lemote.com>
> ---
> arch/mips/include/asm/mach-loongson64/irq.h | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
applied to mips-next.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
prev parent reply other threads:[~2020-09-18 13:57 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-11 10:26 [PATCH V2 1/2] MIPS: Loongson64: Increase NR_IRQS to 320 Huacai Chen
2020-09-11 10:26 ` [PATCH V2 2/2] irqchip/loongson-htvec: Fix initial interrupts clearing Huacai Chen
2020-10-11 17:57 ` [tip: irq/core] irqchip/loongson-htvec: Fix initial interrupt clearing tip-bot2 for Huacai Chen
2020-09-13 15:20 ` [PATCH V2 1/2] MIPS: Loongson64: Increase NR_IRQS to 320 Marc Zyngier
2020-09-18 13:51 ` Thomas Bogendoerfer [this message]
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