* [PATCH V2 2/2] irqchip/loongson-htvec: Fix initial interrupts clearing
2020-09-11 10:26 [PATCH V2 1/2] MIPS: Loongson64: Increase NR_IRQS to 320 Huacai Chen
@ 2020-09-11 10:26 ` Huacai Chen
2020-10-11 17:57 ` [tip: irq/core] irqchip/loongson-htvec: Fix initial interrupt clearing tip-bot2 for Huacai Chen
2020-09-13 15:20 ` [PATCH V2 1/2] MIPS: Loongson64: Increase NR_IRQS to 320 Marc Zyngier
2020-09-18 13:51 ` Thomas Bogendoerfer
2 siblings, 1 reply; 5+ messages in thread
From: Huacai Chen @ 2020-09-11 10:26 UTC (permalink / raw)
To: Thomas Bogendoerfer, Thomas Gleixner, Jason Cooper, Marc Zyngier
Cc: linux-mips, Fuxin Zhang, Huacai Chen, Jiaxun Yang, Huacai Chen,
stable
In htvec_reset() only the first group of initial interrupts is cleared.
This sometimes causes spurious interrupts, so let's clear all groups.
BTW, commit c47e388cfc648421bd821f ("irqchip/loongson-htvec: Support 8
groups of HT vectors") increase interrupt lines from 4 to 8, so update
comments as well.
Cc: stable@vger.kernel.org
Fixes: 818e915fbac518e8c78e1877 ("irqchip: Add Loongson HyperTransport Vector support")
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
drivers/irqchip/irq-loongson-htvec.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-loongson-htvec.c b/drivers/irqchip/irq-loongson-htvec.c
index 13e6016..6392aaf 100644
--- a/drivers/irqchip/irq-loongson-htvec.c
+++ b/drivers/irqchip/irq-loongson-htvec.c
@@ -151,7 +151,7 @@ static void htvec_reset(struct htvec *priv)
/* Clear IRQ cause registers, mask all interrupts */
for (idx = 0; idx < priv->num_parents; idx++) {
writel_relaxed(0x0, priv->base + HTVEC_EN_OFF + 4 * idx);
- writel_relaxed(0xFFFFFFFF, priv->base);
+ writel_relaxed(0xFFFFFFFF, priv->base + 4 * idx);
}
}
@@ -172,7 +172,7 @@ static int htvec_of_init(struct device_node *node,
goto free_priv;
}
- /* Interrupt may come from any of the 4 interrupt line */
+ /* Interrupt may come from any of the 8 interrupt lines */
for (i = 0; i < HTVEC_MAX_PARENT_IRQ; i++) {
parent_irq[i] = irq_of_parse_and_map(node, i);
if (parent_irq[i] <= 0)
--
2.7.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* [tip: irq/core] irqchip/loongson-htvec: Fix initial interrupt clearing
2020-09-11 10:26 ` [PATCH V2 2/2] irqchip/loongson-htvec: Fix initial interrupts clearing Huacai Chen
@ 2020-10-11 17:57 ` tip-bot2 for Huacai Chen
0 siblings, 0 replies; 5+ messages in thread
From: tip-bot2 for Huacai Chen @ 2020-10-11 17:57 UTC (permalink / raw)
To: linux-tip-commits; +Cc: Huacai Chen, Marc Zyngier, stable, x86, LKML
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 1d1e5630de78f7253ac24b92cee6427c3ff04d56
Gitweb: https://git.kernel.org/tip/1d1e5630de78f7253ac24b92cee6427c3ff04d56
Author: Huacai Chen <chenhc@lemote.com>
AuthorDate: Fri, 11 Sep 2020 18:26:18 +08:00
Committer: Marc Zyngier <maz@kernel.org>
CommitterDate: Sun, 13 Sep 2020 15:30:11 +01:00
irqchip/loongson-htvec: Fix initial interrupt clearing
In htvec_reset() only the first group of initial interrupts is cleared.
This sometimes causes spurious interrupts, so let's clear all groups.
While at it, fix the nearby comment that to match the reality of what
the driver does.
Fixes: 818e915fbac518e8c78e1877 ("irqchip: Add Loongson HyperTransport Vector support")
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/1599819978-13999-2-git-send-email-chenhc@lemote.com
---
drivers/irqchip/irq-loongson-htvec.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-loongson-htvec.c b/drivers/irqchip/irq-loongson-htvec.c
index 13e6016..6392aaf 100644
--- a/drivers/irqchip/irq-loongson-htvec.c
+++ b/drivers/irqchip/irq-loongson-htvec.c
@@ -151,7 +151,7 @@ static void htvec_reset(struct htvec *priv)
/* Clear IRQ cause registers, mask all interrupts */
for (idx = 0; idx < priv->num_parents; idx++) {
writel_relaxed(0x0, priv->base + HTVEC_EN_OFF + 4 * idx);
- writel_relaxed(0xFFFFFFFF, priv->base);
+ writel_relaxed(0xFFFFFFFF, priv->base + 4 * idx);
}
}
@@ -172,7 +172,7 @@ static int htvec_of_init(struct device_node *node,
goto free_priv;
}
- /* Interrupt may come from any of the 4 interrupt line */
+ /* Interrupt may come from any of the 8 interrupt lines */
for (i = 0; i < HTVEC_MAX_PARENT_IRQ; i++) {
parent_irq[i] = irq_of_parse_and_map(node, i);
if (parent_irq[i] <= 0)
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH V2 1/2] MIPS: Loongson64: Increase NR_IRQS to 320
2020-09-11 10:26 [PATCH V2 1/2] MIPS: Loongson64: Increase NR_IRQS to 320 Huacai Chen
2020-09-11 10:26 ` [PATCH V2 2/2] irqchip/loongson-htvec: Fix initial interrupts clearing Huacai Chen
@ 2020-09-13 15:20 ` Marc Zyngier
2020-09-18 13:51 ` Thomas Bogendoerfer
2 siblings, 0 replies; 5+ messages in thread
From: Marc Zyngier @ 2020-09-13 15:20 UTC (permalink / raw)
To: Thomas Bogendoerfer, Jason Cooper, Huacai Chen, Thomas Gleixner
Cc: Huacai Chen, Fuxin Zhang, Jiaxun Yang, linux-mips
On Fri, 11 Sep 2020 18:26:17 +0800, Huacai Chen wrote:
> Modernized Loongson64 uses a hierarchical organization for interrupt
> controllers (INTCs), all INTC nodes (not only leaf nodes) need some IRQ
> numbers. This means 280 (i.e., NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256)
> is not enough to represent all interrupts, so let's increase NR_IRQS to
> 320 (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + NR_MAX_CHAINED_IRQS + 256).
Applied to irq/irqchip-fixes-5.9, thanks!
[2/2] irqchip/loongson-htvec: Fix initial interrupt clearing
commit: 1d1e5630de78f7253ac24b92cee6427c3ff04d56
Patch 1/1 can go via the MIPS tree.
Cheers,
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH V2 1/2] MIPS: Loongson64: Increase NR_IRQS to 320
2020-09-11 10:26 [PATCH V2 1/2] MIPS: Loongson64: Increase NR_IRQS to 320 Huacai Chen
2020-09-11 10:26 ` [PATCH V2 2/2] irqchip/loongson-htvec: Fix initial interrupts clearing Huacai Chen
2020-09-13 15:20 ` [PATCH V2 1/2] MIPS: Loongson64: Increase NR_IRQS to 320 Marc Zyngier
@ 2020-09-18 13:51 ` Thomas Bogendoerfer
2 siblings, 0 replies; 5+ messages in thread
From: Thomas Bogendoerfer @ 2020-09-18 13:51 UTC (permalink / raw)
To: Huacai Chen
Cc: Thomas Gleixner, Jason Cooper, Marc Zyngier, linux-mips,
Fuxin Zhang, Huacai Chen, Jiaxun Yang
On Fri, Sep 11, 2020 at 06:26:17PM +0800, Huacai Chen wrote:
> Modernized Loongson64 uses a hierarchical organization for interrupt
> controllers (INTCs), all INTC nodes (not only leaf nodes) need some IRQ
> numbers. This means 280 (i.e., NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256)
> is not enough to represent all interrupts, so let's increase NR_IRQS to
> 320 (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + NR_MAX_CHAINED_IRQS + 256).
>
> Signed-off-by: Huacai Chen <chenhc@lemote.com>
> ---
> arch/mips/include/asm/mach-loongson64/irq.h | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
applied to mips-next.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 5+ messages in thread