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From: Joerg Roedel <joro@8bytes.org>
To: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Cc: iommu@lists.linux-foundation.org, Jon.Grimm@amd.com,
	brijesh.singh@amd.com, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 0/3] amd : iommu : Initial IOMMU support for SNP
Date: Thu, 24 Sep 2020 12:52:00 +0200	[thread overview]
Message-ID: <20200924105200.GP27174@8bytes.org> (raw)
In-Reply-To: <20200923121347.25365-1-suravee.suthikulpanit@amd.com>

On Wed, Sep 23, 2020 at 12:13:44PM +0000, Suravee Suthikulpanit wrote:
> Suravee Suthikulpanit (3):
>   iommu: amd: Use 4K page for completion wait write-back semaphore
>   iommu: amd: Add support for RMP_PAGE_FAULT and RMP_HW_ERR
>   iommu: amd: Re-purpose Exclusion range registers to support SNP CWWB

Applied, thanks. I am slightly concerned about the re-purposing of the
exclusion-range registers based on a feature bit being set. This makes
the hardware incompatible to older IOMMU drivers which do not check the
FEATURE_SNP bit.

It will probably work in this case, as the firmware on systems with
IOMMU-SNP support will not declare exclusion ranges at all and
exclusion-ranges in the IOMMU hardware have been a bad idea since
forever, but it would have been nicer if hardware actually
provided a bit to enable this behavior.

Regards,

	Joerg
_______________________________________________
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iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu

WARNING: multiple messages have this Message-ID (diff)
From: Joerg Roedel <joro@8bytes.org>
To: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Cc: linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org,
	Jon.Grimm@amd.com, brijesh.singh@amd.com
Subject: Re: [PATCH v2 0/3] amd : iommu : Initial IOMMU support for SNP
Date: Thu, 24 Sep 2020 12:52:00 +0200	[thread overview]
Message-ID: <20200924105200.GP27174@8bytes.org> (raw)
In-Reply-To: <20200923121347.25365-1-suravee.suthikulpanit@amd.com>

On Wed, Sep 23, 2020 at 12:13:44PM +0000, Suravee Suthikulpanit wrote:
> Suravee Suthikulpanit (3):
>   iommu: amd: Use 4K page for completion wait write-back semaphore
>   iommu: amd: Add support for RMP_PAGE_FAULT and RMP_HW_ERR
>   iommu: amd: Re-purpose Exclusion range registers to support SNP CWWB

Applied, thanks. I am slightly concerned about the re-purposing of the
exclusion-range registers based on a feature bit being set. This makes
the hardware incompatible to older IOMMU drivers which do not check the
FEATURE_SNP bit.

It will probably work in this case, as the firmware on systems with
IOMMU-SNP support will not declare exclusion ranges at all and
exclusion-ranges in the IOMMU hardware have been a bad idea since
forever, but it would have been nicer if hardware actually
provided a bit to enable this behavior.

Regards,

	Joerg

  parent reply	other threads:[~2020-09-24 10:52 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-23 12:13 [PATCH v2 0/3] amd : iommu : Initial IOMMU support for SNP Suravee Suthikulpanit
2020-09-23 12:13 ` Suravee Suthikulpanit
2020-09-23 12:13 ` [PATCH v2 1/3] iommu: amd: Use 4K page for completion wait write-back semaphore Suravee Suthikulpanit
2020-09-23 12:13   ` Suravee Suthikulpanit
2020-09-23 12:13 ` [PATCH v2 2/3] iommu: amd: Add support for RMP_PAGE_FAULT and RMP_HW_ERR Suravee Suthikulpanit
2020-09-23 12:13   ` Suravee Suthikulpanit
2020-09-23 12:13 ` [PATCH v2 3/3] iommu: amd: Re-purpose Exclusion range registers to support SNP CWWB Suravee Suthikulpanit
2020-09-23 12:13   ` Suravee Suthikulpanit
2020-09-24 10:52 ` Joerg Roedel [this message]
2020-09-24 10:52   ` [PATCH v2 0/3] amd : iommu : Initial IOMMU support for SNP Joerg Roedel

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