From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Karthik B S <karthik.b.s@intel.com>
Cc: paulo.r.zanoni@intel.com, michel@daenzer.net,
dri-devel@lists.freedesktop.org, nicholas.kazlauskas@amd.com,
daniel.vetter@intel.com, harry.wentland@amd.com,
intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v10 0/8] Asynchronous flip implementation for i915
Date: Mon, 28 Sep 2020 15:18:28 +0300 [thread overview]
Message-ID: <20200928121828.GU6112@intel.com> (raw)
In-Reply-To: <20200921110210.21182-1-karthik.b.s@intel.com>
On Mon, Sep 21, 2020 at 04:32:02PM +0530, Karthik B S wrote:
> Without async flip support in the kernel, fullscreen apps where game
> resolution is equal to the screen resolution, must perform an extra blit
> per frame prior to flipping.
>
> Asynchronous page flips will also boost the FPS of Mesa benchmarks.
>
> v2: -Few patches have been squashed and patches have been shuffled as
> per the reviews on the previous version.
>
> v3: -Few patches have been squashed and patches have been shuffled as
> per the reviews on the previous version.
>
> v4: -Made changes to fix the sequence and time stamp issue as per the
> comments received on the previous version.
> -Timestamps are calculated using the flip done time stamp and current
> timestamp. Here I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP flag is used
> for timestamp calculations.
> -Event is sent from the interrupt handler immediately using this
> updated timestamps and sequence.
> -Added more state checks as async flip should only allow change in plane
> surface address and nothing else should be allowed to change.
> -Added a separate plane hook for async flip.
> -Need to find a way to reject fbc enabling if it comes as part of this
> flip as bspec states that changes to FBC are not allowed.
>
> v5: -Fixed the Checkpatch and sparse warnings.
>
> v6: -Reverted back to the old timestamping code as per the feedback received.
> -Added documentation.
>
> v7: -Changes in intel_atomic_check_async()
> -Add vfunc for skl_program_async_surface_address()
>
> v8: -Add WA for older platforms with double buffered
> async address update enable bit.
>
> v9: -Changes as per feedback received on previous version.
>
> v10: -Changes as per feedback received on previous version.
Everything seems good, so pushed the series to dinq. Thanks.
Gave this a little test run on my cfl as well. At first it didn't
kick in, but then I remebered that I'm running X with modifiers
enabled so I was getting compression instead. After disabling
modifiers I got plain old X-tile again and did see async flips
happening.
>
> Karthik B S (8):
> drm/i915: Add enable/disable flip done and flip done handler
> drm/i915: Add support for async flips in I915
> drm/i915: Add checks specific to async flips
> drm/i915: Do not call drm_crtc_arm_vblank_event in async flips
> drm/i915: Add dedicated plane hook for async flip case
> drm/i915: WA for platforms with double buffered address update enable
> bit
> Documentation/gpu: Add asynchronous flip documentation for i915
> drm/i915: Enable async flips in i915
>
> Documentation/gpu/i915.rst | 6 +
> .../gpu/drm/i915/display/intel_atomic_plane.c | 6 +-
> drivers/gpu/drm/i915/display/intel_display.c | 199 ++++++++++++++++++
> .../drm/i915/display/intel_display_types.h | 3 +
> drivers/gpu/drm/i915/display/intel_sprite.c | 30 +++
> drivers/gpu/drm/i915/i915_irq.c | 52 +++++
> drivers/gpu/drm/i915/i915_irq.h | 3 +
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 8 files changed, 299 insertions(+), 1 deletion(-)
>
> --
> 2.22.0
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
WARNING: multiple messages have this Message-ID (diff)
From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Karthik B S <karthik.b.s@intel.com>
Cc: paulo.r.zanoni@intel.com, michel@daenzer.net,
dri-devel@lists.freedesktop.org, nicholas.kazlauskas@amd.com,
vandita.kulkarni@intel.com, uma.shankar@intel.com,
daniel.vetter@intel.com, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v10 0/8] Asynchronous flip implementation for i915
Date: Mon, 28 Sep 2020 15:18:28 +0300 [thread overview]
Message-ID: <20200928121828.GU6112@intel.com> (raw)
In-Reply-To: <20200921110210.21182-1-karthik.b.s@intel.com>
On Mon, Sep 21, 2020 at 04:32:02PM +0530, Karthik B S wrote:
> Without async flip support in the kernel, fullscreen apps where game
> resolution is equal to the screen resolution, must perform an extra blit
> per frame prior to flipping.
>
> Asynchronous page flips will also boost the FPS of Mesa benchmarks.
>
> v2: -Few patches have been squashed and patches have been shuffled as
> per the reviews on the previous version.
>
> v3: -Few patches have been squashed and patches have been shuffled as
> per the reviews on the previous version.
>
> v4: -Made changes to fix the sequence and time stamp issue as per the
> comments received on the previous version.
> -Timestamps are calculated using the flip done time stamp and current
> timestamp. Here I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP flag is used
> for timestamp calculations.
> -Event is sent from the interrupt handler immediately using this
> updated timestamps and sequence.
> -Added more state checks as async flip should only allow change in plane
> surface address and nothing else should be allowed to change.
> -Added a separate plane hook for async flip.
> -Need to find a way to reject fbc enabling if it comes as part of this
> flip as bspec states that changes to FBC are not allowed.
>
> v5: -Fixed the Checkpatch and sparse warnings.
>
> v6: -Reverted back to the old timestamping code as per the feedback received.
> -Added documentation.
>
> v7: -Changes in intel_atomic_check_async()
> -Add vfunc for skl_program_async_surface_address()
>
> v8: -Add WA for older platforms with double buffered
> async address update enable bit.
>
> v9: -Changes as per feedback received on previous version.
>
> v10: -Changes as per feedback received on previous version.
Everything seems good, so pushed the series to dinq. Thanks.
Gave this a little test run on my cfl as well. At first it didn't
kick in, but then I remebered that I'm running X with modifiers
enabled so I was getting compression instead. After disabling
modifiers I got plain old X-tile again and did see async flips
happening.
>
> Karthik B S (8):
> drm/i915: Add enable/disable flip done and flip done handler
> drm/i915: Add support for async flips in I915
> drm/i915: Add checks specific to async flips
> drm/i915: Do not call drm_crtc_arm_vblank_event in async flips
> drm/i915: Add dedicated plane hook for async flip case
> drm/i915: WA for platforms with double buffered address update enable
> bit
> Documentation/gpu: Add asynchronous flip documentation for i915
> drm/i915: Enable async flips in i915
>
> Documentation/gpu/i915.rst | 6 +
> .../gpu/drm/i915/display/intel_atomic_plane.c | 6 +-
> drivers/gpu/drm/i915/display/intel_display.c | 199 ++++++++++++++++++
> .../drm/i915/display/intel_display_types.h | 3 +
> drivers/gpu/drm/i915/display/intel_sprite.c | 30 +++
> drivers/gpu/drm/i915/i915_irq.c | 52 +++++
> drivers/gpu/drm/i915/i915_irq.h | 3 +
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 8 files changed, 299 insertions(+), 1 deletion(-)
>
> --
> 2.22.0
--
Ville Syrjälä
Intel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2020-09-28 12:18 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-21 11:02 [Intel-gfx] [PATCH v10 0/8] Asynchronous flip implementation for i915 Karthik B S
2020-09-21 11:02 ` Karthik B S
2020-09-21 11:02 ` [Intel-gfx] [PATCH v10 1/8] drm/i915: Add enable/disable flip done and flip done handler Karthik B S
2020-09-21 11:02 ` Karthik B S
2020-09-21 11:02 ` [Intel-gfx] [PATCH v10 2/8] drm/i915: Add support for async flips in I915 Karthik B S
2020-09-21 11:02 ` Karthik B S
2020-09-21 11:02 ` [Intel-gfx] [PATCH v11 3/8] drm/i915: Add checks specific to async flips Karthik B S
2020-09-21 11:02 ` Karthik B S
2020-09-21 11:02 ` [Intel-gfx] [PATCH v10 4/8] drm/i915: Do not call drm_crtc_arm_vblank_event in " Karthik B S
2020-09-21 11:02 ` Karthik B S
2020-09-21 11:02 ` [Intel-gfx] [PATCH v11 5/8] drm/i915: Add dedicated plane hook for async flip case Karthik B S
2020-09-21 11:02 ` Karthik B S
2020-09-21 11:02 ` [Intel-gfx] [PATCH v10 6/8] drm/i915: WA for platforms with double buffered address update enable bit Karthik B S
2020-09-21 11:02 ` Karthik B S
2020-09-21 11:02 ` [Intel-gfx] [PATCH v10 7/8] Documentation/gpu: Add asynchronous flip documentation for i915 Karthik B S
2020-09-21 11:02 ` Karthik B S
2020-09-21 11:02 ` [Intel-gfx] [PATCH v10 8/8] drm/i915: Enable async flips in i915 Karthik B S
2020-09-21 11:02 ` Karthik B S
2020-09-21 11:49 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Asynchronous flip implementation for i915 (rev12) Patchwork
2020-09-21 12:13 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-09-21 13:20 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-09-28 12:18 ` Ville Syrjälä [this message]
2020-09-28 12:18 ` [PATCH v10 0/8] Asynchronous flip implementation for i915 Ville Syrjälä
2020-09-29 9:46 ` [Intel-gfx] " Karthik B S
2020-09-29 9:46 ` Karthik B S
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