* [PATCH v2 0/3] power: Add reset support for Microchip Sparx5 SoC
@ 2020-10-06 20:03 ` Lars Povlsen
0 siblings, 0 replies; 12+ messages in thread
From: Lars Povlsen @ 2020-10-06 20:03 UTC (permalink / raw)
To: Sebastian Reichel
Cc: devicetree, Alexandre Belloni, linux-pm, linux-kernel,
Microchip Linux Driver Support, linux-arm-kernel, Lars Povlsen
This adds reset support for the Sparx5 SoC, using the ocelot reset
driver.
Changes in v2:
- Dropped the parts for resetting the switch core upon load time -
controlled by the 'microchip,reset-switch-core' DT property.
Lars Povlsen (3):
dt-bindings: reset: ocelot: Add Sparx5 support
power: reset: ocelot: Add support for Sparx5
arm64: dts: sparx5: Add reset support
.../bindings/power/reset/ocelot-reset.txt | 7 ++-
MAINTAINERS | 1 +
arch/arm64/boot/dts/microchip/sparx5.dtsi | 10 ++++
drivers/power/reset/Kconfig | 3 +-
drivers/power/reset/ocelot-reset.c | 55 +++++++++++++++----
5 files changed, 60 insertions(+), 16 deletions(-)
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 1/3] dt-bindings: reset: ocelot: Add Sparx5 support
2020-10-06 20:03 ` Lars Povlsen
@ 2020-10-06 20:03 ` Lars Povlsen
-1 siblings, 0 replies; 12+ messages in thread
From: Lars Povlsen @ 2020-10-06 20:03 UTC (permalink / raw)
To: Sebastian Reichel, Rob Herring
Cc: Lars Povlsen, Alexandre Belloni, Microchip Linux Driver Support,
linux-pm, devicetree, linux-kernel, linux-arm-kernel
This adds the support for the Sparx5 SoC.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
---
.../devicetree/bindings/power/reset/ocelot-reset.txt | 7 +++++--
MAINTAINERS | 1 +
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
index 1b4213eb3473..4d530d815484 100644
--- a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
+++ b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
@@ -1,10 +1,13 @@
Microsemi Ocelot reset controller
The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the
-SoC MIPS core.
+SoC core.
+
+The reset registers are both present in the MSCC vcoreiii MIPS and
+microchip Sparx5 armv8 SoC's.
Required Properties:
- - compatible: "mscc,ocelot-chip-reset"
+ - compatible: "mscc,ocelot-chip-reset" or "microchip,sparx5-chip-reset"
Example:
reset@1070008 {
diff --git a/MAINTAINERS b/MAINTAINERS
index deaafb617361..cc70e3ab428b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11516,6 +11516,7 @@ M: Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>
L: linux-mips@vger.kernel.org
S: Supported
F: Documentation/devicetree/bindings/mips/mscc.txt
+F: Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
F: arch/mips/boot/dts/mscc/
F: arch/mips/configs/generic/board-ocelot.config
F: arch/mips/generic/board-ocelot.c
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 1/3] dt-bindings: reset: ocelot: Add Sparx5 support
@ 2020-10-06 20:03 ` Lars Povlsen
0 siblings, 0 replies; 12+ messages in thread
From: Lars Povlsen @ 2020-10-06 20:03 UTC (permalink / raw)
To: Sebastian Reichel, Rob Herring
Cc: devicetree, Alexandre Belloni, linux-pm, linux-kernel,
Microchip Linux Driver Support, linux-arm-kernel, Lars Povlsen
This adds the support for the Sparx5 SoC.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
---
.../devicetree/bindings/power/reset/ocelot-reset.txt | 7 +++++--
MAINTAINERS | 1 +
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
index 1b4213eb3473..4d530d815484 100644
--- a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
+++ b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
@@ -1,10 +1,13 @@
Microsemi Ocelot reset controller
The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the
-SoC MIPS core.
+SoC core.
+
+The reset registers are both present in the MSCC vcoreiii MIPS and
+microchip Sparx5 armv8 SoC's.
Required Properties:
- - compatible: "mscc,ocelot-chip-reset"
+ - compatible: "mscc,ocelot-chip-reset" or "microchip,sparx5-chip-reset"
Example:
reset@1070008 {
diff --git a/MAINTAINERS b/MAINTAINERS
index deaafb617361..cc70e3ab428b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11516,6 +11516,7 @@ M: Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>
L: linux-mips@vger.kernel.org
S: Supported
F: Documentation/devicetree/bindings/mips/mscc.txt
+F: Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
F: arch/mips/boot/dts/mscc/
F: arch/mips/configs/generic/board-ocelot.config
F: arch/mips/generic/board-ocelot.c
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v2 1/3] dt-bindings: reset: ocelot: Add Sparx5 support
2020-10-06 20:03 ` Lars Povlsen
@ 2020-10-07 15:54 ` Rob Herring
-1 siblings, 0 replies; 12+ messages in thread
From: Rob Herring @ 2020-10-07 15:54 UTC (permalink / raw)
To: Lars Povlsen
Cc: linux-kernel, linux-arm-kernel, Sebastian Reichel, linux-pm,
Microchip Linux Driver Support, devicetree, Alexandre Belloni,
Rob Herring
On Tue, 06 Oct 2020 22:03:14 +0200, Lars Povlsen wrote:
> This adds the support for the Sparx5 SoC.
>
> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
> ---
> .../devicetree/bindings/power/reset/ocelot-reset.txt | 7 +++++--
> MAINTAINERS | 1 +
> 2 files changed, 6 insertions(+), 2 deletions(-)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: reset: ocelot: Add Sparx5 support
@ 2020-10-07 15:54 ` Rob Herring
0 siblings, 0 replies; 12+ messages in thread
From: Rob Herring @ 2020-10-07 15:54 UTC (permalink / raw)
To: Lars Povlsen
Cc: devicetree, Alexandre Belloni, linux-pm, linux-kernel,
Microchip Linux Driver Support, Rob Herring, Sebastian Reichel,
linux-arm-kernel
On Tue, 06 Oct 2020 22:03:14 +0200, Lars Povlsen wrote:
> This adds the support for the Sparx5 SoC.
>
> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
> ---
> .../devicetree/bindings/power/reset/ocelot-reset.txt | 7 +++++--
> MAINTAINERS | 1 +
> 2 files changed, 6 insertions(+), 2 deletions(-)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 2/3] power: reset: ocelot: Add support for Sparx5
2020-10-06 20:03 ` Lars Povlsen
@ 2020-10-06 20:03 ` Lars Povlsen
-1 siblings, 0 replies; 12+ messages in thread
From: Lars Povlsen @ 2020-10-06 20:03 UTC (permalink / raw)
To: Sebastian Reichel
Cc: Lars Povlsen, Alexandre Belloni, Microchip Linux Driver Support,
linux-pm, devicetree, linux-kernel, linux-arm-kernel
This adds reset support for Sparx5 in the ocelot-reset driver.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
---
drivers/power/reset/Kconfig | 3 +-
drivers/power/reset/ocelot-reset.c | 55 +++++++++++++++++++++++-------
2 files changed, 44 insertions(+), 14 deletions(-)
diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig
index 0a1fb5c74f83..6361569aacb7 100644
--- a/drivers/power/reset/Kconfig
+++ b/drivers/power/reset/Kconfig
@@ -129,10 +129,9 @@ config POWER_RESET_QCOM_PON
config POWER_RESET_OCELOT_RESET
bool "Microsemi Ocelot reset driver"
- depends on MSCC_OCELOT || COMPILE_TEST
select MFD_SYSCON
help
- This driver supports restart for Microsemi Ocelot SoC.
+ This driver supports restart for Microsemi Ocelot SoC and similar.
config POWER_RESET_OXNAS
bool "OXNAS SoC restart driver"
diff --git a/drivers/power/reset/ocelot-reset.c b/drivers/power/reset/ocelot-reset.c
index 419952c61fd0..f74e1dbb4ba3 100644
--- a/drivers/power/reset/ocelot-reset.c
+++ b/drivers/power/reset/ocelot-reset.c
@@ -15,15 +15,20 @@
#include <linux/reboot.h>
#include <linux/regmap.h>
+struct reset_props {
+ const char *syscon;
+ u32 protect_reg;
+ u32 vcore_protect;
+ u32 if_si_owner_bit;
+};
+
struct ocelot_reset_context {
void __iomem *base;
struct regmap *cpu_ctrl;
+ const struct reset_props *props;
struct notifier_block restart_handler;
};
-#define ICPU_CFG_CPU_SYSTEM_CTRL_RESET 0x20
-#define CORE_RST_PROTECT BIT(2)
-
#define SOFT_CHIP_RST BIT(0)
#define ICPU_CFG_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24
@@ -31,7 +36,6 @@ struct ocelot_reset_context {
#define IF_SI_OWNER_SISL 0
#define IF_SI_OWNER_SIBM 1
#define IF_SI_OWNER_SIMC 2
-#define IF_SI_OWNER_OFFSET 4
static int ocelot_restart_handle(struct notifier_block *this,
unsigned long mode, void *cmd)
@@ -39,15 +43,18 @@ static int ocelot_restart_handle(struct notifier_block *this,
struct ocelot_reset_context *ctx = container_of(this, struct
ocelot_reset_context,
restart_handler);
+ u32 if_si_owner_bit = ctx->props->if_si_owner_bit;
/* Make sure the core is not protected from reset */
- regmap_update_bits(ctx->cpu_ctrl, ICPU_CFG_CPU_SYSTEM_CTRL_RESET,
- CORE_RST_PROTECT, 0);
+ regmap_update_bits(ctx->cpu_ctrl, ctx->props->protect_reg,
+ ctx->props->vcore_protect, 0);
/* Make the SI back to boot mode */
regmap_update_bits(ctx->cpu_ctrl, ICPU_CFG_CPU_SYSTEM_CTRL_GENERAL_CTRL,
- IF_SI_OWNER_MASK << IF_SI_OWNER_OFFSET,
- IF_SI_OWNER_SIBM << IF_SI_OWNER_OFFSET);
+ IF_SI_OWNER_MASK << if_si_owner_bit,
+ IF_SI_OWNER_SIBM << if_si_owner_bit);
+
+ pr_emerg("Resetting SoC\n");
writel(SOFT_CHIP_RST, ctx->base);
@@ -72,9 +79,13 @@ static int ocelot_reset_probe(struct platform_device *pdev)
if (IS_ERR(ctx->base))
return PTR_ERR(ctx->base);
- ctx->cpu_ctrl = syscon_regmap_lookup_by_compatible("mscc,ocelot-cpu-syscon");
- if (IS_ERR(ctx->cpu_ctrl))
+ ctx->props = device_get_match_data(dev);
+
+ ctx->cpu_ctrl = syscon_regmap_lookup_by_compatible(ctx->props->syscon);
+ if (IS_ERR(ctx->cpu_ctrl)) {
+ dev_err(dev, "No syscon map: %s\n", ctx->props->syscon);
return PTR_ERR(ctx->cpu_ctrl);
+ }
ctx->restart_handler.notifier_call = ocelot_restart_handle;
ctx->restart_handler.priority = 192;
@@ -85,9 +96,29 @@ static int ocelot_reset_probe(struct platform_device *pdev)
return err;
}
+static const struct reset_props reset_props_ocelot = {
+ .syscon = "mscc,ocelot-cpu-syscon",
+ .protect_reg = 0x20,
+ .vcore_protect = BIT(2),
+ .if_si_owner_bit = 4,
+};
+
+static const struct reset_props reset_props_sparx5 = {
+ .syscon = "microchip,sparx5-cpu-syscon",
+ .protect_reg = 0x84,
+ .vcore_protect = BIT(10),
+ .if_si_owner_bit = 6,
+};
+
static const struct of_device_id ocelot_reset_of_match[] = {
- { .compatible = "mscc,ocelot-chip-reset" },
- {}
+ {
+ .compatible = "mscc,ocelot-chip-reset",
+ .data = &reset_props_ocelot
+ }, {
+ .compatible = "microchip,sparx5-chip-reset",
+ .data = &reset_props_sparx5
+ },
+ { /*sentinel*/ }
};
static struct platform_driver ocelot_reset_driver = {
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 2/3] power: reset: ocelot: Add support for Sparx5
@ 2020-10-06 20:03 ` Lars Povlsen
0 siblings, 0 replies; 12+ messages in thread
From: Lars Povlsen @ 2020-10-06 20:03 UTC (permalink / raw)
To: Sebastian Reichel
Cc: devicetree, Alexandre Belloni, linux-pm, linux-kernel,
Microchip Linux Driver Support, linux-arm-kernel, Lars Povlsen
This adds reset support for Sparx5 in the ocelot-reset driver.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
---
drivers/power/reset/Kconfig | 3 +-
drivers/power/reset/ocelot-reset.c | 55 +++++++++++++++++++++++-------
2 files changed, 44 insertions(+), 14 deletions(-)
diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig
index 0a1fb5c74f83..6361569aacb7 100644
--- a/drivers/power/reset/Kconfig
+++ b/drivers/power/reset/Kconfig
@@ -129,10 +129,9 @@ config POWER_RESET_QCOM_PON
config POWER_RESET_OCELOT_RESET
bool "Microsemi Ocelot reset driver"
- depends on MSCC_OCELOT || COMPILE_TEST
select MFD_SYSCON
help
- This driver supports restart for Microsemi Ocelot SoC.
+ This driver supports restart for Microsemi Ocelot SoC and similar.
config POWER_RESET_OXNAS
bool "OXNAS SoC restart driver"
diff --git a/drivers/power/reset/ocelot-reset.c b/drivers/power/reset/ocelot-reset.c
index 419952c61fd0..f74e1dbb4ba3 100644
--- a/drivers/power/reset/ocelot-reset.c
+++ b/drivers/power/reset/ocelot-reset.c
@@ -15,15 +15,20 @@
#include <linux/reboot.h>
#include <linux/regmap.h>
+struct reset_props {
+ const char *syscon;
+ u32 protect_reg;
+ u32 vcore_protect;
+ u32 if_si_owner_bit;
+};
+
struct ocelot_reset_context {
void __iomem *base;
struct regmap *cpu_ctrl;
+ const struct reset_props *props;
struct notifier_block restart_handler;
};
-#define ICPU_CFG_CPU_SYSTEM_CTRL_RESET 0x20
-#define CORE_RST_PROTECT BIT(2)
-
#define SOFT_CHIP_RST BIT(0)
#define ICPU_CFG_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24
@@ -31,7 +36,6 @@ struct ocelot_reset_context {
#define IF_SI_OWNER_SISL 0
#define IF_SI_OWNER_SIBM 1
#define IF_SI_OWNER_SIMC 2
-#define IF_SI_OWNER_OFFSET 4
static int ocelot_restart_handle(struct notifier_block *this,
unsigned long mode, void *cmd)
@@ -39,15 +43,18 @@ static int ocelot_restart_handle(struct notifier_block *this,
struct ocelot_reset_context *ctx = container_of(this, struct
ocelot_reset_context,
restart_handler);
+ u32 if_si_owner_bit = ctx->props->if_si_owner_bit;
/* Make sure the core is not protected from reset */
- regmap_update_bits(ctx->cpu_ctrl, ICPU_CFG_CPU_SYSTEM_CTRL_RESET,
- CORE_RST_PROTECT, 0);
+ regmap_update_bits(ctx->cpu_ctrl, ctx->props->protect_reg,
+ ctx->props->vcore_protect, 0);
/* Make the SI back to boot mode */
regmap_update_bits(ctx->cpu_ctrl, ICPU_CFG_CPU_SYSTEM_CTRL_GENERAL_CTRL,
- IF_SI_OWNER_MASK << IF_SI_OWNER_OFFSET,
- IF_SI_OWNER_SIBM << IF_SI_OWNER_OFFSET);
+ IF_SI_OWNER_MASK << if_si_owner_bit,
+ IF_SI_OWNER_SIBM << if_si_owner_bit);
+
+ pr_emerg("Resetting SoC\n");
writel(SOFT_CHIP_RST, ctx->base);
@@ -72,9 +79,13 @@ static int ocelot_reset_probe(struct platform_device *pdev)
if (IS_ERR(ctx->base))
return PTR_ERR(ctx->base);
- ctx->cpu_ctrl = syscon_regmap_lookup_by_compatible("mscc,ocelot-cpu-syscon");
- if (IS_ERR(ctx->cpu_ctrl))
+ ctx->props = device_get_match_data(dev);
+
+ ctx->cpu_ctrl = syscon_regmap_lookup_by_compatible(ctx->props->syscon);
+ if (IS_ERR(ctx->cpu_ctrl)) {
+ dev_err(dev, "No syscon map: %s\n", ctx->props->syscon);
return PTR_ERR(ctx->cpu_ctrl);
+ }
ctx->restart_handler.notifier_call = ocelot_restart_handle;
ctx->restart_handler.priority = 192;
@@ -85,9 +96,29 @@ static int ocelot_reset_probe(struct platform_device *pdev)
return err;
}
+static const struct reset_props reset_props_ocelot = {
+ .syscon = "mscc,ocelot-cpu-syscon",
+ .protect_reg = 0x20,
+ .vcore_protect = BIT(2),
+ .if_si_owner_bit = 4,
+};
+
+static const struct reset_props reset_props_sparx5 = {
+ .syscon = "microchip,sparx5-cpu-syscon",
+ .protect_reg = 0x84,
+ .vcore_protect = BIT(10),
+ .if_si_owner_bit = 6,
+};
+
static const struct of_device_id ocelot_reset_of_match[] = {
- { .compatible = "mscc,ocelot-chip-reset" },
- {}
+ {
+ .compatible = "mscc,ocelot-chip-reset",
+ .data = &reset_props_ocelot
+ }, {
+ .compatible = "microchip,sparx5-chip-reset",
+ .data = &reset_props_sparx5
+ },
+ { /*sentinel*/ }
};
static struct platform_driver ocelot_reset_driver = {
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 3/3] arm64: dts: sparx5: Add reset support
2020-10-06 20:03 ` Lars Povlsen
@ 2020-10-06 20:03 ` Lars Povlsen
-1 siblings, 0 replies; 12+ messages in thread
From: Lars Povlsen @ 2020-10-06 20:03 UTC (permalink / raw)
To: Sebastian Reichel
Cc: Lars Povlsen, Alexandre Belloni, Microchip Linux Driver Support,
linux-pm, devicetree, linux-kernel, linux-arm-kernel
This adds reset support to the Sparx5 SoC DT.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index a84ffd3069d4..016be6d27a6b 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -118,6 +118,16 @@ gic: interrupt-controller@600300000 {
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
+ cpu_ctrl: syscon@600000000 {
+ compatible = "microchip,sparx5-cpu-syscon", "syscon";
+ reg = <0x6 0x00000000 0xd0>;
+ };
+
+ reset@611010008 {
+ compatible = "microchip,sparx5-chip-reset";
+ reg = <0x6 0x11010008 0x4>;
+ };
+
uart0: serial@600100000 {
pinctrl-0 = <&uart_pins>;
pinctrl-names = "default";
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 3/3] arm64: dts: sparx5: Add reset support
@ 2020-10-06 20:03 ` Lars Povlsen
0 siblings, 0 replies; 12+ messages in thread
From: Lars Povlsen @ 2020-10-06 20:03 UTC (permalink / raw)
To: Sebastian Reichel
Cc: devicetree, Alexandre Belloni, linux-pm, linux-kernel,
Microchip Linux Driver Support, linux-arm-kernel, Lars Povlsen
This adds reset support to the Sparx5 SoC DT.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index a84ffd3069d4..016be6d27a6b 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -118,6 +118,16 @@ gic: interrupt-controller@600300000 {
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
+ cpu_ctrl: syscon@600000000 {
+ compatible = "microchip,sparx5-cpu-syscon", "syscon";
+ reg = <0x6 0x00000000 0xd0>;
+ };
+
+ reset@611010008 {
+ compatible = "microchip,sparx5-chip-reset";
+ reg = <0x6 0x11010008 0x4>;
+ };
+
uart0: serial@600100000 {
pinctrl-0 = <&uart_pins>;
pinctrl-names = "default";
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v2 0/3] power: Add reset support for Microchip Sparx5 SoC
2020-10-06 20:03 ` Lars Povlsen
@ 2020-10-08 22:05 ` Sebastian Reichel
-1 siblings, 0 replies; 12+ messages in thread
From: Sebastian Reichel @ 2020-10-08 22:05 UTC (permalink / raw)
To: Lars Povlsen
Cc: Alexandre Belloni, Microchip Linux Driver Support, linux-pm,
devicetree, linux-kernel, linux-arm-kernel
[-- Attachment #1: Type: text/plain, Size: 906 bytes --]
Hi,
On Tue, Oct 06, 2020 at 10:03:13PM +0200, Lars Povlsen wrote:
> This adds reset support for the Sparx5 SoC, using the ocelot reset
> driver.
>
> Changes in v2:
> - Dropped the parts for resetting the switch core upon load time -
> controlled by the 'microchip,reset-switch-core' DT property.
>
> Lars Povlsen (3):
> dt-bindings: reset: ocelot: Add Sparx5 support
> power: reset: ocelot: Add support for Sparx5
> arm64: dts: sparx5: Add reset support
>
> .../bindings/power/reset/ocelot-reset.txt | 7 ++-
> MAINTAINERS | 1 +
> arch/arm64/boot/dts/microchip/sparx5.dtsi | 10 ++++
> drivers/power/reset/Kconfig | 3 +-
> drivers/power/reset/ocelot-reset.c | 55 +++++++++++++++----
> 5 files changed, 60 insertions(+), 16 deletions(-)
Thanks, I queued the first two patches.
-- Sebastian
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* Re: [PATCH v2 0/3] power: Add reset support for Microchip Sparx5 SoC
@ 2020-10-08 22:05 ` Sebastian Reichel
0 siblings, 0 replies; 12+ messages in thread
From: Sebastian Reichel @ 2020-10-08 22:05 UTC (permalink / raw)
To: Lars Povlsen
Cc: devicetree, Alexandre Belloni, linux-pm, linux-kernel,
Microchip Linux Driver Support, linux-arm-kernel
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Hi,
On Tue, Oct 06, 2020 at 10:03:13PM +0200, Lars Povlsen wrote:
> This adds reset support for the Sparx5 SoC, using the ocelot reset
> driver.
>
> Changes in v2:
> - Dropped the parts for resetting the switch core upon load time -
> controlled by the 'microchip,reset-switch-core' DT property.
>
> Lars Povlsen (3):
> dt-bindings: reset: ocelot: Add Sparx5 support
> power: reset: ocelot: Add support for Sparx5
> arm64: dts: sparx5: Add reset support
>
> .../bindings/power/reset/ocelot-reset.txt | 7 ++-
> MAINTAINERS | 1 +
> arch/arm64/boot/dts/microchip/sparx5.dtsi | 10 ++++
> drivers/power/reset/Kconfig | 3 +-
> drivers/power/reset/ocelot-reset.c | 55 +++++++++++++++----
> 5 files changed, 60 insertions(+), 16 deletions(-)
Thanks, I queued the first two patches.
-- Sebastian
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