All of lore.kernel.org
 help / color / mirror / Atom feed
From: Anshuman Gupta <anshuman.gupta@intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: jani.nikula@intel.com, seanpaul@chromium.org
Subject: [Intel-gfx] [PATCH v2 13/15] drm/i915/hdcp: Add HDCP 2.2 stream register
Date: Tue, 20 Oct 2020 19:09:04 +0530	[thread overview]
Message-ID: <20201020133906.23710-14-anshuman.gupta@intel.com> (raw)
In-Reply-To: <20201020133906.23710-1-anshuman.gupta@intel.com>

Add HDCP 2.2 DP MST HDCP2_STREAM_STATUS
and HDCP2_AUTH_STREAM register in i915_reg header.

Cc: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e0b995162e96..3a8c8eada96a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9861,6 +9861,7 @@ enum skl_power_gate {
 					  _PORTD_HDCP2_BASE, \
 					  _PORTE_HDCP2_BASE, \
 					  _PORTF_HDCP2_BASE) + (x))
+
 #define PORT_HDCP2_AUTH(port)		_PORT_HDCP2_BASE(port, 0x98)
 #define _TRANSA_HDCP2_AUTH		0x66498
 #define _TRANSB_HDCP2_AUTH		0x66598
@@ -9900,6 +9901,35 @@ enum skl_power_gate {
 					 TRANS_HDCP2_STATUS(trans) : \
 					 PORT_HDCP2_STATUS(port))
 
+#define PORT_HDCP2_STREAM_STATUS(port)		_PORT_HDCP2_BASE(port, 0xC0)
+#define _TRANSA_HDCP2_STREAM_STATUS		0x664C0
+#define _TRANSB_HDCP2_STREAM_STATUS		0x665C0
+#define TRANS_HDCP2_STREAM_STATUS(trans)	_MMIO_TRANS(trans, \
+						    _TRANSA_HDCP2_STREAM_STATUS, \
+						    _TRANSB_HDCP2_STREAM_STATUS)
+#define   STREAM_ENCRYPTION_STATUS	BIT(31)
+#define   STREAM_TYPE_STATUS		BIT(30)
+#define HDCP2_STREAM_STATUS(dev_priv, trans, port) \
+					(INTEL_GEN(dev_priv) >= 12 ? \
+					 TRANS_HDCP2_STREAM_STATUS(trans) : \
+					 PORT_HDCP2_STREAM_STATUS(port))
+
+#define _PORTA_HDCP2_AUTH_STREAM		0x66F00
+#define _PORTB_HDCP2_AUTH_STREAM		0x66F04
+#define PORT_HDCP2_AUTH_STREAM(port)	_MMIO_PORT(port, \
+						   _PORTA_HDCP2_AUTH_STREAM, \
+						   _PORTB_HDCP2_AUTH_STREAM)
+#define _TRANSA_HDCP2_AUTH_STREAM		0x66F00
+#define _TRANSB_HDCP2_AUTH_STREAM		0x66F04
+#define TRANS_HDCP2_AUTH_STREAM(trans)	_MMIO_TRANS(trans, \
+						    _TRANSA_HDCP2_AUTH_STREAM, \
+						    _TRANSB_HDCP2_AUTH_STREAM)
+#define   AUTH_STREAM_TYPE		BIT(31)
+#define HDCP2_AUTH_STREAM(dev_priv, trans, port) \
+					(INTEL_GEN(dev_priv) >= 12 ? \
+					 TRANS_HDCP2_AUTH_STREAM(trans) : \
+					 PORT_HDCP2_AUTH_STREAM(port))
+
 /* Per-pipe DDI Function Control */
 #define _TRANS_DDI_FUNC_CTL_A		0x60400
 #define _TRANS_DDI_FUNC_CTL_B		0x61400
-- 
2.26.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

WARNING: multiple messages have this Message-ID (diff)
From: Anshuman Gupta <anshuman.gupta@intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: jani.nikula@intel.com, seanpaul@chromium.org,
	juston.li@intel.com, Anshuman Gupta <anshuman.gupta@intel.com>
Subject: [PATCH v2 13/15] drm/i915/hdcp: Add HDCP 2.2 stream register
Date: Tue, 20 Oct 2020 19:09:04 +0530	[thread overview]
Message-ID: <20201020133906.23710-14-anshuman.gupta@intel.com> (raw)
In-Reply-To: <20201020133906.23710-1-anshuman.gupta@intel.com>

Add HDCP 2.2 DP MST HDCP2_STREAM_STATUS
and HDCP2_AUTH_STREAM register in i915_reg header.

Cc: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e0b995162e96..3a8c8eada96a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9861,6 +9861,7 @@ enum skl_power_gate {
 					  _PORTD_HDCP2_BASE, \
 					  _PORTE_HDCP2_BASE, \
 					  _PORTF_HDCP2_BASE) + (x))
+
 #define PORT_HDCP2_AUTH(port)		_PORT_HDCP2_BASE(port, 0x98)
 #define _TRANSA_HDCP2_AUTH		0x66498
 #define _TRANSB_HDCP2_AUTH		0x66598
@@ -9900,6 +9901,35 @@ enum skl_power_gate {
 					 TRANS_HDCP2_STATUS(trans) : \
 					 PORT_HDCP2_STATUS(port))
 
+#define PORT_HDCP2_STREAM_STATUS(port)		_PORT_HDCP2_BASE(port, 0xC0)
+#define _TRANSA_HDCP2_STREAM_STATUS		0x664C0
+#define _TRANSB_HDCP2_STREAM_STATUS		0x665C0
+#define TRANS_HDCP2_STREAM_STATUS(trans)	_MMIO_TRANS(trans, \
+						    _TRANSA_HDCP2_STREAM_STATUS, \
+						    _TRANSB_HDCP2_STREAM_STATUS)
+#define   STREAM_ENCRYPTION_STATUS	BIT(31)
+#define   STREAM_TYPE_STATUS		BIT(30)
+#define HDCP2_STREAM_STATUS(dev_priv, trans, port) \
+					(INTEL_GEN(dev_priv) >= 12 ? \
+					 TRANS_HDCP2_STREAM_STATUS(trans) : \
+					 PORT_HDCP2_STREAM_STATUS(port))
+
+#define _PORTA_HDCP2_AUTH_STREAM		0x66F00
+#define _PORTB_HDCP2_AUTH_STREAM		0x66F04
+#define PORT_HDCP2_AUTH_STREAM(port)	_MMIO_PORT(port, \
+						   _PORTA_HDCP2_AUTH_STREAM, \
+						   _PORTB_HDCP2_AUTH_STREAM)
+#define _TRANSA_HDCP2_AUTH_STREAM		0x66F00
+#define _TRANSB_HDCP2_AUTH_STREAM		0x66F04
+#define TRANS_HDCP2_AUTH_STREAM(trans)	_MMIO_TRANS(trans, \
+						    _TRANSA_HDCP2_AUTH_STREAM, \
+						    _TRANSB_HDCP2_AUTH_STREAM)
+#define   AUTH_STREAM_TYPE		BIT(31)
+#define HDCP2_AUTH_STREAM(dev_priv, trans, port) \
+					(INTEL_GEN(dev_priv) >= 12 ? \
+					 TRANS_HDCP2_AUTH_STREAM(trans) : \
+					 PORT_HDCP2_AUTH_STREAM(port))
+
 /* Per-pipe DDI Function Control */
 #define _TRANS_DDI_FUNC_CTL_A		0x60400
 #define _TRANS_DDI_FUNC_CTL_B		0x61400
-- 
2.26.2

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

  parent reply	other threads:[~2020-10-20 13:50 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-20 13:38 [Intel-gfx] [PATCH v2 00/15] HDCP 2.2 DP MST Support Anshuman Gupta
2020-10-20 13:38 ` Anshuman Gupta
2020-10-20 13:38 ` [Intel-gfx] [PATCH v2 01/15] drm/i915/hdcp: Update CP property in update_pipe Anshuman Gupta
2020-10-20 13:38   ` Anshuman Gupta
2020-10-20 13:38 ` [Intel-gfx] [PATCH v2 02/15] drm/i915/hotplug: Handle CP_IRQ for DP-MST Anshuman Gupta
2020-10-20 13:38   ` Anshuman Gupta
2020-10-20 13:38 ` [Intel-gfx] [PATCH v2 03/15] drm/i915/hdcp: DP MST transcoder for link and stream Anshuman Gupta
2020-10-20 13:38   ` Anshuman Gupta
2020-10-20 13:38 ` [Intel-gfx] [PATCH v2 04/15] drm/i915/hdcp: Move HDCP enc status timeout to header Anshuman Gupta
2020-10-20 13:38   ` Anshuman Gupta
2020-10-20 13:38 ` [Intel-gfx] [PATCH v2 05/15] drm/i915/hdcp: HDCP stream encryption support Anshuman Gupta
2020-10-20 13:38   ` Anshuman Gupta
2020-10-20 13:38 ` [Intel-gfx] [PATCH v2 06/15] drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support Anshuman Gupta
2020-10-20 13:38   ` Anshuman Gupta
2020-10-20 13:38 ` [Intel-gfx] [PATCH v2 07/15] drm/i915/hdcp: Pass dig_port to intel_hdcp_init Anshuman Gupta
2020-10-20 13:38   ` Anshuman Gupta
2020-10-20 13:38 ` [Intel-gfx] [PATCH v2 08/15] drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port Anshuman Gupta
2020-10-20 13:38   ` Anshuman Gupta
2020-10-20 13:39 ` [Intel-gfx] [PATCH v2 09/15] misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len Anshuman Gupta
2020-10-20 13:39   ` Anshuman Gupta
2020-10-20 18:32   ` [Intel-gfx] " Jani Nikula
2020-10-20 18:32     ` Jani Nikula
2020-10-21 16:30     ` [Intel-gfx] " Winkler, Tomas
2020-10-21 16:30       ` Winkler, Tomas
2020-10-20 13:39 ` [Intel-gfx] [PATCH v2 10/15] drm/hdcp: Max MST content streams Anshuman Gupta
2020-10-20 13:39   ` Anshuman Gupta
2020-10-20 13:39 ` [Intel-gfx] [PATCH v2 11/15] drm/i915/hdcp: mst streams support in hdcp port_data Anshuman Gupta
2020-10-20 13:39   ` Anshuman Gupta
2020-10-20 13:39 ` [Intel-gfx] [PATCH v2 12/15] drm/i915/hdcp: Pass connector to check_2_2_link Anshuman Gupta
2020-10-20 13:39   ` Anshuman Gupta
2020-10-20 13:39 ` Anshuman Gupta [this message]
2020-10-20 13:39   ` [PATCH v2 13/15] drm/i915/hdcp: Add HDCP 2.2 stream register Anshuman Gupta
2020-10-20 13:39 ` [Intel-gfx] [PATCH v2 14/15] drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks Anshuman Gupta
2020-10-20 13:39   ` Anshuman Gupta
2020-10-20 13:39 ` [Intel-gfx] [PATCH v2 15/15] drm/i915/hdcp: Enable HDCP 2.2 MST support Anshuman Gupta
2020-10-20 13:39   ` Anshuman Gupta
2020-10-20 13:57 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for HDCP 2.2 DP MST Support (rev4) Patchwork
2020-10-20 13:58 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-10-20 14:27 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20201020133906.23710-14-anshuman.gupta@intel.com \
    --to=anshuman.gupta@intel.com \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=jani.nikula@intel.com \
    --cc=seanpaul@chromium.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.