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From: Alexey Baturo <baturo.alexey@gmail.com>
Cc: baturo.alexey@gmail.com, richard.henderson@linaro.org,
	space.monkey.delivers@gmail.com, kupokupokupopo@gmail.com,
	palmer@dabbelt.com, Alistair.Francis@wdc.com,
	sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: [PATCH v6 6/6] [RISCV_PM] Allow experimental J-ext to be turned on
Date: Thu, 22 Oct 2020 11:04:40 +0300	[thread overview]
Message-ID: <20201022080440.10069-7-space.monkey.delivers@gmail.com> (raw)
In-Reply-To: <20201022080440.10069-1-space.monkey.delivers@gmail.com>

Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
---
 target/riscv/cpu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1c00d9ea26..56633c14eb 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -465,6 +465,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
         }
         if (cpu->cfg.ext_j) {
             env->mmte |= PM_EXT_INITIAL;
+            target_misa |= RVJ;
         }
         if (cpu->cfg.ext_v) {
             target_misa |= RVV;
-- 
2.20.1



WARNING: multiple messages have this Message-ID (diff)
From: Alexey Baturo <baturo.alexey@gmail.com>
Cc: baturo.alexey@gmail.com, qemu-riscv@nongnu.org,
	sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de,
	richard.henderson@linaro.org, qemu-devel@nongnu.org,
	space.monkey.delivers@gmail.com, Alistair.Francis@wdc.com,
	kupokupokupopo@gmail.com, palmer@dabbelt.com
Subject: [PATCH v6 6/6] [RISCV_PM] Allow experimental J-ext to be turned on
Date: Thu, 22 Oct 2020 11:04:40 +0300	[thread overview]
Message-ID: <20201022080440.10069-7-space.monkey.delivers@gmail.com> (raw)
In-Reply-To: <20201022080440.10069-1-space.monkey.delivers@gmail.com>

Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
---
 target/riscv/cpu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1c00d9ea26..56633c14eb 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -465,6 +465,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
         }
         if (cpu->cfg.ext_j) {
             env->mmte |= PM_EXT_INITIAL;
+            target_misa |= RVJ;
         }
         if (cpu->cfg.ext_v) {
             target_misa |= RVV;
-- 
2.20.1



  parent reply	other threads:[~2020-10-22  8:04 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-22  8:04 [PATCH v6 0/6] RISC-V Pointer Masking implementation Alexey Baturo
2020-10-22  8:04 ` Alexey Baturo
2020-10-22  8:04 ` [PATCH v6 1/6] [RISCV_PM] Add J-extension into RISC-V Alexey Baturo
2020-10-22  8:04   ` Alexey Baturo
2020-10-24  0:24   ` Alistair Francis
2020-10-22  8:04 ` [PATCH v6 2/6] [RISCV_PM] Support CSRs required for RISC-V PM extension except for ones in hypervisor mode Alexey Baturo
2020-10-22  8:04   ` Alexey Baturo
2020-10-22  8:04 ` [PATCH v6 3/6] [RISCV_PM] Print new PM CSRs in QEMU logs Alexey Baturo
2020-10-22  8:04   ` Alexey Baturo
2020-10-22  8:04 ` [PATCH v6 4/6] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions Alexey Baturo
2020-10-22  8:04   ` Alexey Baturo
2020-10-22  8:04 ` [PATCH v6 5/6] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension Alexey Baturo
2020-10-22  8:04   ` Alexey Baturo
2020-10-22  8:04 ` Alexey Baturo [this message]
2020-10-22  8:04   ` [PATCH v6 6/6] [RISCV_PM] Allow experimental J-ext to be turned on Alexey Baturo
2020-10-24  0:25 ` [PATCH v6 0/6] RISC-V Pointer Masking implementation Alistair Francis
2020-10-26 19:10   ` Richard Henderson

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