Re: [PATCH 2/2] acpi/crs: Support ranges > 32b for hosts

[Igor Mammedov <imammedo@redhat.com>]

On Tue, 27 Oct 2020 08:45:05 -0700
Ben Widawsky <ben@bwidawsk.net> wrote:

> On 20-10-27 15:36:12, Igor Mammedov wrote:
> > On Mon, 26 Oct 2020 12:39:24 -0700
> > Ben Widawsky <ben.widawsky@intel.com> wrote:
> >   
> > > According to PCIe spec 5.0 Type 1 header space Base Address Registers
> > > are defined by 7.5.1.2.1 Base Address Registers (same as Type 0). The
> > > _CRS region should allow for the same range (up to 64b). Prior to this
> > > change, any host bridge utilizing more than 32b for the BAR would have
> > > the address truncated and likely lead to conflicts when the operating
> > > systems reads the _CRS object.
> > > 
> > > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>  
> > 
> > Looks good to me, so
> > 
> > Reviewed-by: Igor Mammedov <imammedo@redhat.com>
> > 
> > 
> > CCing,
> > Michael to have a send pair of eyes on it 
> > 
> > but I wonder how/why ivshm (which might have quite large BAR) works.  
> 
> I think this will only hit things that subclass TYPE_PCI_HOST_BRIDGE. AFAICT,
> ivshm is a regular TYPE_PCI_DEVICE. Is there a _CRS created for ivshm?

no, but device uses _CRS provided by bus, so I'd expect it would fail
on guest side if its BAR is bigger than window provided by host bridge.

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