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From: Boris Brezillon <boris.brezillon@collabora.com>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: dri-devel@lists.freedesktop.org, stable@vger.kernel.org,
	Steven Price <steven.price@arm.com>,
	Rob Herring <robh+dt@kernel.org>,
	Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>,
	Robin Murphy <robin.murphy@arm.com>
Subject: Re: [PATCH v3] drm/panfrost: Move the GPU reset bits outside the timeout handler
Date: Tue, 3 Nov 2020 12:03:26 +0100	[thread overview]
Message-ID: <20201103120326.10037005@collabora.com> (raw)
In-Reply-To: <20201103102540.GB401619@phenom.ffwll.local>

On Tue, 3 Nov 2020 11:25:40 +0100
Daniel Vetter <daniel@ffwll.ch> wrote:

> On Tue, Nov 03, 2020 at 09:13:47AM +0100, Boris Brezillon wrote:
> > We've fixed many races in panfrost_job_timedout() but some remain.
> > Instead of trying to fix it again, let's simplify the logic and move
> > the reset bits to a separate work scheduled when one of the queue
> > reports a timeout.
> > 
> > v3:
> > - Replace the atomic_cmpxchg() by an atomic_xchg() (Robin Murphy)
> > - Add Steven's R-b
> > 
> > v2:
> > - Use atomic_cmpxchg() to conditionally schedule the reset work (Steven Price)
> > 
> > Fixes: 1a11a88cfd9a ("drm/panfrost: Fix job timeout handling")
> > Cc: <stable@vger.kernel.org>
> > Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
> > Reviewed-by: Steven Price <steven.price@arm.com>  
> 
> Sprinkling the dma_fence annotations over this would be really nice ...

You mean something like that?

--->8---
From 4f90ee2972eaec0332833ff6f9ea078acbfa899a Mon Sep 17 00:00:00 2001
From: Boris Brezillon <boris.brezillon@collabora.com>
Date: Tue, 3 Nov 2020 12:01:09 +0100
Subject: [PATCH] drm/panfrost: Annotate dma_fence signalling

Annotate dma_fence signalling to help lockdep catch deadlocks.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
---
 drivers/gpu/drm/panfrost/panfrost_job.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/panfrost/panfrost_job.c b/drivers/gpu/drm/panfrost/panfrost_job.c
index 569a099dc10e..046cb3677332 100644
--- a/drivers/gpu/drm/panfrost/panfrost_job.c
+++ b/drivers/gpu/drm/panfrost/panfrost_job.c
@@ -482,7 +482,9 @@ static irqreturn_t panfrost_job_irq_handler(int irq, void *data)
 
 		if (status & JOB_INT_MASK_DONE(j)) {
 			struct panfrost_job *job;
+			bool cookie;
 
+			cookie = dma_fence_begin_signalling();
 			spin_lock(&pfdev->js->job_lock);
 			job = pfdev->jobs[j];
 			/* Only NULL if job timeout occurred */
@@ -496,6 +498,7 @@ static irqreturn_t panfrost_job_irq_handler(int irq, void *data)
 				pm_runtime_put_autosuspend(pfdev->dev);
 			}
 			spin_unlock(&pfdev->js->job_lock);
+			dma_fence_end_signalling(cookie);
 		}
 
 		status &= ~mask;
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WARNING: multiple messages have this Message-ID (diff)
From: Boris Brezillon <boris.brezillon@collabora.com>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: Rob Herring <robh+dt@kernel.org>,
	Tomeu Vizoso <tomeu@tomeuvizoso.net>,
	Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>,
	Steven Price <steven.price@arm.com>,
	Robin Murphy <robin.murphy@arm.com>,
	stable@vger.kernel.org, dri-devel@lists.freedesktop.org
Subject: Re: [PATCH v3] drm/panfrost: Move the GPU reset bits outside the timeout handler
Date: Tue, 3 Nov 2020 12:03:26 +0100	[thread overview]
Message-ID: <20201103120326.10037005@collabora.com> (raw)
In-Reply-To: <20201103102540.GB401619@phenom.ffwll.local>

On Tue, 3 Nov 2020 11:25:40 +0100
Daniel Vetter <daniel@ffwll.ch> wrote:

> On Tue, Nov 03, 2020 at 09:13:47AM +0100, Boris Brezillon wrote:
> > We've fixed many races in panfrost_job_timedout() but some remain.
> > Instead of trying to fix it again, let's simplify the logic and move
> > the reset bits to a separate work scheduled when one of the queue
> > reports a timeout.
> > 
> > v3:
> > - Replace the atomic_cmpxchg() by an atomic_xchg() (Robin Murphy)
> > - Add Steven's R-b
> > 
> > v2:
> > - Use atomic_cmpxchg() to conditionally schedule the reset work (Steven Price)
> > 
> > Fixes: 1a11a88cfd9a ("drm/panfrost: Fix job timeout handling")
> > Cc: <stable@vger.kernel.org>
> > Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
> > Reviewed-by: Steven Price <steven.price@arm.com>  
> 
> Sprinkling the dma_fence annotations over this would be really nice ...

You mean something like that?

--->8---
From 4f90ee2972eaec0332833ff6f9ea078acbfa899a Mon Sep 17 00:00:00 2001
From: Boris Brezillon <boris.brezillon@collabora.com>
Date: Tue, 3 Nov 2020 12:01:09 +0100
Subject: [PATCH] drm/panfrost: Annotate dma_fence signalling

Annotate dma_fence signalling to help lockdep catch deadlocks.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
---
 drivers/gpu/drm/panfrost/panfrost_job.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/panfrost/panfrost_job.c b/drivers/gpu/drm/panfrost/panfrost_job.c
index 569a099dc10e..046cb3677332 100644
--- a/drivers/gpu/drm/panfrost/panfrost_job.c
+++ b/drivers/gpu/drm/panfrost/panfrost_job.c
@@ -482,7 +482,9 @@ static irqreturn_t panfrost_job_irq_handler(int irq, void *data)
 
 		if (status & JOB_INT_MASK_DONE(j)) {
 			struct panfrost_job *job;
+			bool cookie;
 
+			cookie = dma_fence_begin_signalling();
 			spin_lock(&pfdev->js->job_lock);
 			job = pfdev->jobs[j];
 			/* Only NULL if job timeout occurred */
@@ -496,6 +498,7 @@ static irqreturn_t panfrost_job_irq_handler(int irq, void *data)
 				pm_runtime_put_autosuspend(pfdev->dev);
 			}
 			spin_unlock(&pfdev->js->job_lock);
+			dma_fence_end_signalling(cookie);
 		}
 
 		status &= ~mask;

  reply	other threads:[~2020-11-03 11:03 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-03  8:13 [PATCH v3] drm/panfrost: Move the GPU reset bits outside the timeout handler Boris Brezillon
2020-11-03  8:13 ` Boris Brezillon
2020-11-03 10:25 ` Daniel Vetter
2020-11-03 10:25   ` Daniel Vetter
2020-11-03 11:03   ` Boris Brezillon [this message]
2020-11-03 11:03     ` Boris Brezillon
2020-11-03 11:08     ` Daniel Vetter
2020-11-03 11:08       ` Daniel Vetter
2020-11-03 12:02       ` Boris Brezillon
2020-11-03 12:02         ` Boris Brezillon

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