From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: coresight@lists.linaro.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org
Subject: Re: [PATCH v3 09/26] coresight: Convert coresight_timeout to use access abstraction
Date: Tue, 3 Nov 2020 11:03:29 -0700 [thread overview]
Message-ID: <20201103180329.GB2855763@xps15> (raw)
In-Reply-To: <20201028220945.3826358-11-suzuki.poulose@arm.com>
On Wed, Oct 28, 2020 at 10:09:28PM +0000, Suzuki K Poulose wrote:
> Convert the generic routines to use the new access abstraction layer
> gradually, starting with coresigth_timeout.
>
> Cc: Mike Leach <mike.leach@linaro.org>
> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> drivers/hwtracing/coresight/coresight-catu.c | 5 ++--
> drivers/hwtracing/coresight/coresight-core.c | 15 ++++++----
> drivers/hwtracing/coresight/coresight-etb10.c | 5 ++--
> .../coresight/coresight-etm4x-core.c | 30 ++++++++++++-------
> drivers/hwtracing/coresight/coresight-stm.c | 3 +-
> .../hwtracing/coresight/coresight-tmc-core.c | 15 ++++++----
> drivers/hwtracing/coresight/coresight-tpiu.c | 4 +--
> include/linux/coresight.h | 17 ++++++++---
> 8 files changed, 61 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-catu.c b/drivers/hwtracing/coresight/coresight-catu.c
> index 5baf29510f1b..34c74b05c542 100644
> --- a/drivers/hwtracing/coresight/coresight-catu.c
> +++ b/drivers/hwtracing/coresight/coresight-catu.c
> @@ -401,8 +401,9 @@ static const struct attribute_group *catu_groups[] = {
>
> static inline int catu_wait_for_ready(struct catu_drvdata *drvdata)
> {
> - return coresight_timeout(drvdata->base,
> - CATU_STATUS, CATU_STATUS_READY, 1);
> + struct csdev_access *csa = &drvdata->csdev->access;
> +
> + return coresight_timeout(csa, CATU_STATUS, CATU_STATUS_READY, 1);
> }
>
> static int catu_enable_hw(struct catu_drvdata *drvdata, void *data)
> diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c
> index e96deaca8cab..42ba989a6b5e 100644
> --- a/drivers/hwtracing/coresight/coresight-core.c
> +++ b/drivers/hwtracing/coresight/coresight-core.c
> @@ -1412,23 +1412,26 @@ static void coresight_remove_conns(struct coresight_device *csdev)
> }
>
> /**
> - * coresight_timeout - loop until a bit has changed to a specific state.
> - * @addr: base address of the area of interest.
> - * @offset: address of a register, starting from @addr.
> + * coresight_timeout - loop until a bit has changed to a specific register
> + * state.
> + * @csa: coresight device access for the device
> + * @offset: Offset of the register from the base of the device.
> * @position: the position of the bit of interest.
> * @value: the value the bit should have.
> *
> * Return: 0 as soon as the bit has taken the desired state or -EAGAIN if
> * TIMEOUT_US has elapsed, which ever happens first.
> */
> -
> -int coresight_timeout(void __iomem *addr, u32 offset, int position, int value)
> +int coresight_timeout(struct csdev_access *csa,
> + u32 offset,
> + int position,
> + int value)
There is no need for stacking, please maximise the 80 characters. The function
stubs in coresight.h should also be revised.
> {
> int i;
> u32 val;
>
> for (i = TIMEOUT_US; i > 0; i--) {
> - val = __raw_readl(addr + offset);
> + val = csdev_access_read32(csa, offset);
I vaguely remember commenting on this, or perhaps it was on some othe patch you
wrote... Anyways, I think it is a good thing to go from an unordered access to
an ordered access for the timeout function.
With the above:
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
> /* waiting on the bit to go from 0 to 1 */
> if (value) {
> if (val & BIT(position))
> diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c
> index b91633c6c9b4..f994a22876d9 100644
> --- a/drivers/hwtracing/coresight/coresight-etb10.c
> +++ b/drivers/hwtracing/coresight/coresight-etb10.c
> @@ -251,6 +251,7 @@ static void __etb_disable_hw(struct etb_drvdata *drvdata)
> {
> u32 ffcr;
> struct device *dev = &drvdata->csdev->dev;
> + struct csdev_access *csa = &drvdata->csdev->access;
>
> CS_UNLOCK(drvdata->base);
>
> @@ -262,7 +263,7 @@ static void __etb_disable_hw(struct etb_drvdata *drvdata)
> ffcr |= ETB_FFCR_FON_MAN;
> writel_relaxed(ffcr, drvdata->base + ETB_FFCR);
>
> - if (coresight_timeout(drvdata->base, ETB_FFCR, ETB_FFCR_BIT, 0)) {
> + if (coresight_timeout(csa, ETB_FFCR, ETB_FFCR_BIT, 0)) {
> dev_err(dev,
> "timeout while waiting for completion of Manual Flush\n");
> }
> @@ -270,7 +271,7 @@ static void __etb_disable_hw(struct etb_drvdata *drvdata)
> /* disable trace capture */
> writel_relaxed(0x0, drvdata->base + ETB_CTL_REG);
>
> - if (coresight_timeout(drvdata->base, ETB_FFSR, ETB_FFSR_BIT, 1)) {
> + if (coresight_timeout(csa, ETB_FFSR, ETB_FFSR_BIT, 1)) {
> dev_err(dev,
> "timeout while waiting for Formatter to Stop\n");
> }
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index c5cb93f1b80c..2744aadaa5ec 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -107,7 +107,9 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> {
> int i, rc;
> struct etmv4_config *config = &drvdata->config;
> - struct device *etm_dev = &drvdata->csdev->dev;
> + struct coresight_device *csdev = drvdata->csdev;
> + struct device *etm_dev = &csdev->dev;
> + struct csdev_access *csa = &csdev->access;
>
> CS_UNLOCK(drvdata->base);
>
> @@ -121,7 +123,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> writel_relaxed(0, drvdata->base + TRCPRGCTLR);
>
> /* wait for TRCSTATR.IDLE to go up */
> - if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
> + if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
> dev_err(etm_dev,
> "timeout while waiting for Idle Trace Status\n");
> if (drvdata->nr_pe)
> @@ -212,7 +214,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> writel_relaxed(1, drvdata->base + TRCPRGCTLR);
>
> /* wait for TRCSTATR.IDLE to go back down to '0' */
> - if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
> + if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
> dev_err(etm_dev,
> "timeout while waiting for Idle Trace Status\n");
>
> @@ -476,7 +478,9 @@ static void etm4_disable_hw(void *info)
> u32 control;
> struct etmv4_drvdata *drvdata = info;
> struct etmv4_config *config = &drvdata->config;
> - struct device *etm_dev = &drvdata->csdev->dev;
> + struct coresight_device *csdev = drvdata->csdev;
> + struct device *etm_dev = &csdev->dev;
> + struct csdev_access *csa = &csdev->access;
> int i;
>
> CS_UNLOCK(drvdata->base);
> @@ -503,8 +507,7 @@ static void etm4_disable_hw(void *info)
> writel_relaxed(control, drvdata->base + TRCPRGCTLR);
>
> /* wait for TRCSTATR.PMSTABLE to go to '1' */
> - if (coresight_timeout(drvdata->base, TRCSTATR,
> - TRCSTATR_PMSTABLE_BIT, 1))
> + if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1))
> dev_err(etm_dev,
> "timeout while waiting for PM stable Trace Status\n");
>
> @@ -1160,7 +1163,15 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
> {
> int i, ret = 0;
> struct etmv4_save_state *state;
> - struct device *etm_dev = &drvdata->csdev->dev;
> + struct coresight_device *csdev = drvdata->csdev;
> + struct csdev_access *csa;
> + struct device *etm_dev;
> +
> + if (WARN_ON(!csdev))
> + return -ENODEV;
> +
> + etm_dev = &csdev->dev;
> + csa = &csdev->access;
>
> /*
> * As recommended by 3.4.1 ("The procedure when powering down the PE")
> @@ -1175,8 +1186,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
> etm4_os_lock(drvdata);
>
> /* wait for TRCSTATR.PMSTABLE to go up */
> - if (coresight_timeout(drvdata->base, TRCSTATR,
> - TRCSTATR_PMSTABLE_BIT, 1)) {
> + if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1)) {
> dev_err(etm_dev,
> "timeout while waiting for PM Stable Status\n");
> etm4_os_unlock(drvdata);
> @@ -1264,7 +1274,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
> state->trcpdcr = readl(drvdata->base + TRCPDCR);
>
> /* wait for TRCSTATR.IDLE to go up */
> - if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) {
> + if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) {
> dev_err(etm_dev,
> "timeout while waiting for Idle Trace Status\n");
> etm4_os_unlock(drvdata);
> diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c
> index 315500b7763f..9cba67b27586 100644
> --- a/drivers/hwtracing/coresight/coresight-stm.c
> +++ b/drivers/hwtracing/coresight/coresight-stm.c
> @@ -258,6 +258,7 @@ static void stm_disable(struct coresight_device *csdev,
> struct perf_event *event)
> {
> struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> + struct csdev_access *csa = &csdev->access;
>
> /*
> * For as long as the tracer isn't disabled another entity can't
> @@ -270,7 +271,7 @@ static void stm_disable(struct coresight_device *csdev,
> spin_unlock(&drvdata->spinlock);
>
> /* Wait until the engine has completely stopped */
> - coresight_timeout(drvdata->base, STMTCSR, STMTCSR_BUSY_BIT, 0);
> + coresight_timeout(csa, STMTCSR, STMTCSR_BUSY_BIT, 0);
>
> pm_runtime_put(csdev->dev.parent);
>
> diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c
> index 8fd640d41e1b..572f4b316798 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc-core.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c
> @@ -33,16 +33,20 @@ DEFINE_CORESIGHT_DEVLIST(etr_devs, "tmc_etr");
>
> void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata)
> {
> + struct coresight_device *csdev = drvdata->csdev;
> + struct csdev_access *csa = &csdev->access;
> +
> /* Ensure formatter, unformatter and hardware fifo are empty */
> - if (coresight_timeout(drvdata->base,
> - TMC_STS, TMC_STS_TMCREADY_BIT, 1)) {
> - dev_err(&drvdata->csdev->dev,
> + if (coresight_timeout(csa, TMC_STS, TMC_STS_TMCREADY_BIT, 1)) {
> + dev_err(&csdev->dev,
> "timeout while waiting for TMC to be Ready\n");
> }
> }
>
> void tmc_flush_and_stop(struct tmc_drvdata *drvdata)
> {
> + struct coresight_device *csdev = drvdata->csdev;
> + struct csdev_access *csa = &csdev->access;
> u32 ffcr;
>
> ffcr = readl_relaxed(drvdata->base + TMC_FFCR);
> @@ -51,9 +55,8 @@ void tmc_flush_and_stop(struct tmc_drvdata *drvdata)
> ffcr |= BIT(TMC_FFCR_FLUSHMAN_BIT);
> writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
> /* Ensure flush completes */
> - if (coresight_timeout(drvdata->base,
> - TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0)) {
> - dev_err(&drvdata->csdev->dev,
> + if (coresight_timeout(csa, TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0)) {
> + dev_err(&csdev->dev,
> "timeout while waiting for completion of Manual Flush\n");
> }
>
> diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtracing/coresight/coresight-tpiu.c
> index 98c4a029854c..1e92c76d9656 100644
> --- a/drivers/hwtracing/coresight/coresight-tpiu.c
> +++ b/drivers/hwtracing/coresight/coresight-tpiu.c
> @@ -86,9 +86,9 @@ static void tpiu_disable_hw(struct csdev_access *csa)
> /* Generate manual flush */
> csdev_access_relaxed_write32(csa, FFCR_STOP_FI | FFCR_FON_MAN, TPIU_FFCR);
> /* Wait for flush to complete */
> - coresight_timeout(csa->base, TPIU_FFCR, FFCR_FON_MAN_BIT, 0);
> + coresight_timeout(csa, TPIU_FFCR, FFCR_FON_MAN_BIT, 0);
> /* Wait for formatter to stop */
> - coresight_timeout(csa->base, TPIU_FFSR, FFSR_FT_STOPPED_BIT, 1);
> + coresight_timeout(csa, TPIU_FFSR, FFSR_FT_STOPPED_BIT, 1);
>
> CS_LOCK(csa->base);
> }
> diff --git a/include/linux/coresight.h b/include/linux/coresight.h
> index 5a34c2f2debc..cefc8fe239e6 100644
> --- a/include/linux/coresight.h
> +++ b/include/linux/coresight.h
> @@ -469,8 +469,10 @@ coresight_register(struct coresight_desc *desc);
> extern void coresight_unregister(struct coresight_device *csdev);
> extern int coresight_enable(struct coresight_device *csdev);
> extern void coresight_disable(struct coresight_device *csdev);
> -extern int coresight_timeout(void __iomem *addr, u32 offset,
> - int position, int value);
> +extern int coresight_timeout(struct csdev_access *csa,
> + u32 offset,
> + int position,
> + int value);
>
> extern int coresight_claim_device(void __iomem *base);
> extern int coresight_claim_device_unlocked(void __iomem *base);
> @@ -502,8 +504,15 @@ static inline void coresight_unregister(struct coresight_device *csdev) {}
> static inline int
> coresight_enable(struct coresight_device *csdev) { return -ENOSYS; }
> static inline void coresight_disable(struct coresight_device *csdev) {}
> -static inline int coresight_timeout(void __iomem *addr, u32 offset,
> - int position, int value) { return 1; }
> +
> +static inline int coresight_timeout(struct csdev_access *csa,
> + u32 offset,
> + int position,
> + int value)
> +{
> + return 1;
> +}
> +
> static inline int coresight_claim_device_unlocked(void __iomem *base)
> {
> return -EINVAL;
> --
> 2.24.1
>
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WARNING: multiple messages have this Message-ID (diff)
From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org,
coresight@lists.linaro.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 09/26] coresight: Convert coresight_timeout to use access abstraction
Date: Tue, 3 Nov 2020 11:03:29 -0700 [thread overview]
Message-ID: <20201103180329.GB2855763@xps15> (raw)
In-Reply-To: <20201028220945.3826358-11-suzuki.poulose@arm.com>
On Wed, Oct 28, 2020 at 10:09:28PM +0000, Suzuki K Poulose wrote:
> Convert the generic routines to use the new access abstraction layer
> gradually, starting with coresigth_timeout.
>
> Cc: Mike Leach <mike.leach@linaro.org>
> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> drivers/hwtracing/coresight/coresight-catu.c | 5 ++--
> drivers/hwtracing/coresight/coresight-core.c | 15 ++++++----
> drivers/hwtracing/coresight/coresight-etb10.c | 5 ++--
> .../coresight/coresight-etm4x-core.c | 30 ++++++++++++-------
> drivers/hwtracing/coresight/coresight-stm.c | 3 +-
> .../hwtracing/coresight/coresight-tmc-core.c | 15 ++++++----
> drivers/hwtracing/coresight/coresight-tpiu.c | 4 +--
> include/linux/coresight.h | 17 ++++++++---
> 8 files changed, 61 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-catu.c b/drivers/hwtracing/coresight/coresight-catu.c
> index 5baf29510f1b..34c74b05c542 100644
> --- a/drivers/hwtracing/coresight/coresight-catu.c
> +++ b/drivers/hwtracing/coresight/coresight-catu.c
> @@ -401,8 +401,9 @@ static const struct attribute_group *catu_groups[] = {
>
> static inline int catu_wait_for_ready(struct catu_drvdata *drvdata)
> {
> - return coresight_timeout(drvdata->base,
> - CATU_STATUS, CATU_STATUS_READY, 1);
> + struct csdev_access *csa = &drvdata->csdev->access;
> +
> + return coresight_timeout(csa, CATU_STATUS, CATU_STATUS_READY, 1);
> }
>
> static int catu_enable_hw(struct catu_drvdata *drvdata, void *data)
> diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c
> index e96deaca8cab..42ba989a6b5e 100644
> --- a/drivers/hwtracing/coresight/coresight-core.c
> +++ b/drivers/hwtracing/coresight/coresight-core.c
> @@ -1412,23 +1412,26 @@ static void coresight_remove_conns(struct coresight_device *csdev)
> }
>
> /**
> - * coresight_timeout - loop until a bit has changed to a specific state.
> - * @addr: base address of the area of interest.
> - * @offset: address of a register, starting from @addr.
> + * coresight_timeout - loop until a bit has changed to a specific register
> + * state.
> + * @csa: coresight device access for the device
> + * @offset: Offset of the register from the base of the device.
> * @position: the position of the bit of interest.
> * @value: the value the bit should have.
> *
> * Return: 0 as soon as the bit has taken the desired state or -EAGAIN if
> * TIMEOUT_US has elapsed, which ever happens first.
> */
> -
> -int coresight_timeout(void __iomem *addr, u32 offset, int position, int value)
> +int coresight_timeout(struct csdev_access *csa,
> + u32 offset,
> + int position,
> + int value)
There is no need for stacking, please maximise the 80 characters. The function
stubs in coresight.h should also be revised.
> {
> int i;
> u32 val;
>
> for (i = TIMEOUT_US; i > 0; i--) {
> - val = __raw_readl(addr + offset);
> + val = csdev_access_read32(csa, offset);
I vaguely remember commenting on this, or perhaps it was on some othe patch you
wrote... Anyways, I think it is a good thing to go from an unordered access to
an ordered access for the timeout function.
With the above:
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
> /* waiting on the bit to go from 0 to 1 */
> if (value) {
> if (val & BIT(position))
> diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c
> index b91633c6c9b4..f994a22876d9 100644
> --- a/drivers/hwtracing/coresight/coresight-etb10.c
> +++ b/drivers/hwtracing/coresight/coresight-etb10.c
> @@ -251,6 +251,7 @@ static void __etb_disable_hw(struct etb_drvdata *drvdata)
> {
> u32 ffcr;
> struct device *dev = &drvdata->csdev->dev;
> + struct csdev_access *csa = &drvdata->csdev->access;
>
> CS_UNLOCK(drvdata->base);
>
> @@ -262,7 +263,7 @@ static void __etb_disable_hw(struct etb_drvdata *drvdata)
> ffcr |= ETB_FFCR_FON_MAN;
> writel_relaxed(ffcr, drvdata->base + ETB_FFCR);
>
> - if (coresight_timeout(drvdata->base, ETB_FFCR, ETB_FFCR_BIT, 0)) {
> + if (coresight_timeout(csa, ETB_FFCR, ETB_FFCR_BIT, 0)) {
> dev_err(dev,
> "timeout while waiting for completion of Manual Flush\n");
> }
> @@ -270,7 +271,7 @@ static void __etb_disable_hw(struct etb_drvdata *drvdata)
> /* disable trace capture */
> writel_relaxed(0x0, drvdata->base + ETB_CTL_REG);
>
> - if (coresight_timeout(drvdata->base, ETB_FFSR, ETB_FFSR_BIT, 1)) {
> + if (coresight_timeout(csa, ETB_FFSR, ETB_FFSR_BIT, 1)) {
> dev_err(dev,
> "timeout while waiting for Formatter to Stop\n");
> }
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index c5cb93f1b80c..2744aadaa5ec 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -107,7 +107,9 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> {
> int i, rc;
> struct etmv4_config *config = &drvdata->config;
> - struct device *etm_dev = &drvdata->csdev->dev;
> + struct coresight_device *csdev = drvdata->csdev;
> + struct device *etm_dev = &csdev->dev;
> + struct csdev_access *csa = &csdev->access;
>
> CS_UNLOCK(drvdata->base);
>
> @@ -121,7 +123,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> writel_relaxed(0, drvdata->base + TRCPRGCTLR);
>
> /* wait for TRCSTATR.IDLE to go up */
> - if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
> + if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
> dev_err(etm_dev,
> "timeout while waiting for Idle Trace Status\n");
> if (drvdata->nr_pe)
> @@ -212,7 +214,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> writel_relaxed(1, drvdata->base + TRCPRGCTLR);
>
> /* wait for TRCSTATR.IDLE to go back down to '0' */
> - if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
> + if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
> dev_err(etm_dev,
> "timeout while waiting for Idle Trace Status\n");
>
> @@ -476,7 +478,9 @@ static void etm4_disable_hw(void *info)
> u32 control;
> struct etmv4_drvdata *drvdata = info;
> struct etmv4_config *config = &drvdata->config;
> - struct device *etm_dev = &drvdata->csdev->dev;
> + struct coresight_device *csdev = drvdata->csdev;
> + struct device *etm_dev = &csdev->dev;
> + struct csdev_access *csa = &csdev->access;
> int i;
>
> CS_UNLOCK(drvdata->base);
> @@ -503,8 +507,7 @@ static void etm4_disable_hw(void *info)
> writel_relaxed(control, drvdata->base + TRCPRGCTLR);
>
> /* wait for TRCSTATR.PMSTABLE to go to '1' */
> - if (coresight_timeout(drvdata->base, TRCSTATR,
> - TRCSTATR_PMSTABLE_BIT, 1))
> + if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1))
> dev_err(etm_dev,
> "timeout while waiting for PM stable Trace Status\n");
>
> @@ -1160,7 +1163,15 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
> {
> int i, ret = 0;
> struct etmv4_save_state *state;
> - struct device *etm_dev = &drvdata->csdev->dev;
> + struct coresight_device *csdev = drvdata->csdev;
> + struct csdev_access *csa;
> + struct device *etm_dev;
> +
> + if (WARN_ON(!csdev))
> + return -ENODEV;
> +
> + etm_dev = &csdev->dev;
> + csa = &csdev->access;
>
> /*
> * As recommended by 3.4.1 ("The procedure when powering down the PE")
> @@ -1175,8 +1186,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
> etm4_os_lock(drvdata);
>
> /* wait for TRCSTATR.PMSTABLE to go up */
> - if (coresight_timeout(drvdata->base, TRCSTATR,
> - TRCSTATR_PMSTABLE_BIT, 1)) {
> + if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1)) {
> dev_err(etm_dev,
> "timeout while waiting for PM Stable Status\n");
> etm4_os_unlock(drvdata);
> @@ -1264,7 +1274,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
> state->trcpdcr = readl(drvdata->base + TRCPDCR);
>
> /* wait for TRCSTATR.IDLE to go up */
> - if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) {
> + if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) {
> dev_err(etm_dev,
> "timeout while waiting for Idle Trace Status\n");
> etm4_os_unlock(drvdata);
> diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c
> index 315500b7763f..9cba67b27586 100644
> --- a/drivers/hwtracing/coresight/coresight-stm.c
> +++ b/drivers/hwtracing/coresight/coresight-stm.c
> @@ -258,6 +258,7 @@ static void stm_disable(struct coresight_device *csdev,
> struct perf_event *event)
> {
> struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> + struct csdev_access *csa = &csdev->access;
>
> /*
> * For as long as the tracer isn't disabled another entity can't
> @@ -270,7 +271,7 @@ static void stm_disable(struct coresight_device *csdev,
> spin_unlock(&drvdata->spinlock);
>
> /* Wait until the engine has completely stopped */
> - coresight_timeout(drvdata->base, STMTCSR, STMTCSR_BUSY_BIT, 0);
> + coresight_timeout(csa, STMTCSR, STMTCSR_BUSY_BIT, 0);
>
> pm_runtime_put(csdev->dev.parent);
>
> diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c
> index 8fd640d41e1b..572f4b316798 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc-core.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c
> @@ -33,16 +33,20 @@ DEFINE_CORESIGHT_DEVLIST(etr_devs, "tmc_etr");
>
> void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata)
> {
> + struct coresight_device *csdev = drvdata->csdev;
> + struct csdev_access *csa = &csdev->access;
> +
> /* Ensure formatter, unformatter and hardware fifo are empty */
> - if (coresight_timeout(drvdata->base,
> - TMC_STS, TMC_STS_TMCREADY_BIT, 1)) {
> - dev_err(&drvdata->csdev->dev,
> + if (coresight_timeout(csa, TMC_STS, TMC_STS_TMCREADY_BIT, 1)) {
> + dev_err(&csdev->dev,
> "timeout while waiting for TMC to be Ready\n");
> }
> }
>
> void tmc_flush_and_stop(struct tmc_drvdata *drvdata)
> {
> + struct coresight_device *csdev = drvdata->csdev;
> + struct csdev_access *csa = &csdev->access;
> u32 ffcr;
>
> ffcr = readl_relaxed(drvdata->base + TMC_FFCR);
> @@ -51,9 +55,8 @@ void tmc_flush_and_stop(struct tmc_drvdata *drvdata)
> ffcr |= BIT(TMC_FFCR_FLUSHMAN_BIT);
> writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
> /* Ensure flush completes */
> - if (coresight_timeout(drvdata->base,
> - TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0)) {
> - dev_err(&drvdata->csdev->dev,
> + if (coresight_timeout(csa, TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0)) {
> + dev_err(&csdev->dev,
> "timeout while waiting for completion of Manual Flush\n");
> }
>
> diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtracing/coresight/coresight-tpiu.c
> index 98c4a029854c..1e92c76d9656 100644
> --- a/drivers/hwtracing/coresight/coresight-tpiu.c
> +++ b/drivers/hwtracing/coresight/coresight-tpiu.c
> @@ -86,9 +86,9 @@ static void tpiu_disable_hw(struct csdev_access *csa)
> /* Generate manual flush */
> csdev_access_relaxed_write32(csa, FFCR_STOP_FI | FFCR_FON_MAN, TPIU_FFCR);
> /* Wait for flush to complete */
> - coresight_timeout(csa->base, TPIU_FFCR, FFCR_FON_MAN_BIT, 0);
> + coresight_timeout(csa, TPIU_FFCR, FFCR_FON_MAN_BIT, 0);
> /* Wait for formatter to stop */
> - coresight_timeout(csa->base, TPIU_FFSR, FFSR_FT_STOPPED_BIT, 1);
> + coresight_timeout(csa, TPIU_FFSR, FFSR_FT_STOPPED_BIT, 1);
>
> CS_LOCK(csa->base);
> }
> diff --git a/include/linux/coresight.h b/include/linux/coresight.h
> index 5a34c2f2debc..cefc8fe239e6 100644
> --- a/include/linux/coresight.h
> +++ b/include/linux/coresight.h
> @@ -469,8 +469,10 @@ coresight_register(struct coresight_desc *desc);
> extern void coresight_unregister(struct coresight_device *csdev);
> extern int coresight_enable(struct coresight_device *csdev);
> extern void coresight_disable(struct coresight_device *csdev);
> -extern int coresight_timeout(void __iomem *addr, u32 offset,
> - int position, int value);
> +extern int coresight_timeout(struct csdev_access *csa,
> + u32 offset,
> + int position,
> + int value);
>
> extern int coresight_claim_device(void __iomem *base);
> extern int coresight_claim_device_unlocked(void __iomem *base);
> @@ -502,8 +504,15 @@ static inline void coresight_unregister(struct coresight_device *csdev) {}
> static inline int
> coresight_enable(struct coresight_device *csdev) { return -ENOSYS; }
> static inline void coresight_disable(struct coresight_device *csdev) {}
> -static inline int coresight_timeout(void __iomem *addr, u32 offset,
> - int position, int value) { return 1; }
> +
> +static inline int coresight_timeout(struct csdev_access *csa,
> + u32 offset,
> + int position,
> + int value)
> +{
> + return 1;
> +}
> +
> static inline int coresight_claim_device_unlocked(void __iomem *base)
> {
> return -EINVAL;
> --
> 2.24.1
>
next prev parent reply other threads:[~2020-11-03 18:05 UTC|newest]
Thread overview: 154+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-28 22:09 [PATCH v3 00/26] coresight: Support for ETM system instructions Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 01/26] coresight: etm4x: Fix accesses to TRCVMIDCTLR1 Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 02/26] coresight: etm4x: Fix accesses to TRCCIDCTLR1 Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 03/26] coresight: etm4x: Update TRCIDR3.NUMPROCS handling to match v4.2 Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 04/26] coresight: etm4x: Fix accesses to TRCPROCSELR Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 05/26] coresight: etm4x: Handle TRCVIPCSSCTLR accesses Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 06/26] coresight: etm4x: Handle access to TRCSSPCICRn Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-11-02 21:46 ` Mathieu Poirier
2020-11-02 21:46 ` Mathieu Poirier
2020-11-02 22:04 ` Suzuki K Poulose
2020-11-02 22:04 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 07/26] coresight: Introduce device access abstraction Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-11-03 17:14 ` Mathieu Poirier
2020-11-03 17:14 ` Mathieu Poirier
2020-11-03 17:25 ` Mathieu Poirier
2020-11-03 17:25 ` Mathieu Poirier
2020-11-04 10:07 ` Suzuki K Poulose
2020-11-04 10:07 ` Suzuki K Poulose
2020-11-09 21:00 ` Mathieu Poirier
2020-11-09 21:00 ` Mathieu Poirier
2020-11-10 9:24 ` Suzuki K Poulose
2020-11-10 9:24 ` Suzuki K Poulose
2020-11-10 17:02 ` Mathieu Poirier
2020-11-10 17:02 ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 08/26] coresight: tpiu: Prepare for using coresight " Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-11-03 18:03 ` Mathieu Poirier
2020-11-03 18:03 ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 09/26] coresight: Convert coresight_timeout to use " Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-11-03 18:03 ` Mathieu Poirier [this message]
2020-11-03 18:03 ` Mathieu Poirier
2020-11-04 10:42 ` Suzuki K Poulose
2020-11-04 10:42 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 10/26] coresight: Convert claim/disclaim operations to use access wrappers Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-11-03 18:36 ` Mathieu Poirier
2020-11-03 18:36 ` Mathieu Poirier
2020-11-04 10:54 ` Suzuki K Poulose
2020-11-04 10:54 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 11/26] coresight: etm4x: Always read the registers on the host CPU Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 12/26] coresight: etm4x: Convert all register accesses Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-11-03 18:53 ` Mathieu Poirier
2020-11-03 18:53 ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 13/26] coresight: etm4x: Add commentary on the registers Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-11-03 19:03 ` Mathieu Poirier
2020-11-03 19:03 ` Mathieu Poirier
2020-11-03 19:04 ` Mathieu Poirier
2020-11-03 19:04 ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 14/26] coresight: etm4x: Add sysreg access helpers Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-10-29 15:26 ` Suzuki K Poulose
2020-10-29 15:26 ` Suzuki K Poulose
2020-11-05 20:52 ` Mathieu Poirier
2020-11-05 20:52 ` Mathieu Poirier
2020-11-05 22:47 ` Suzuki K Poulose
2020-11-05 22:47 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 15/26] coresight: etm4x: Define DEVARCH register fields Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 16/26] coresight: etm4x: Check for Software Lock Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-11-05 21:50 ` Mathieu Poirier
2020-11-05 21:50 ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 17/26] coresight: etm4x: Cleanup secure exception level masks Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-11-05 21:55 ` Mathieu Poirier
2020-11-05 21:55 ` Mathieu Poirier
2020-11-09 9:40 ` Suzuki K Poulose
2020-11-09 9:40 ` Suzuki K Poulose
2020-11-09 17:42 ` Mathieu Poirier
2020-11-09 17:42 ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 18/26] coresight: etm4x: Clean up " Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-11-06 18:52 ` Mathieu Poirier
2020-11-06 18:52 ` Mathieu Poirier
2020-11-09 9:44 ` Suzuki K Poulose
2020-11-09 9:44 ` Suzuki K Poulose
2020-11-10 23:15 ` Suzuki K Poulose
2020-11-10 23:15 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 19/26] coresight: etm4x: Detect access early on the target CPU Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-11-06 20:34 ` Mathieu Poirier
2020-11-06 20:34 ` Mathieu Poirier
2020-11-09 9:48 ` Suzuki K Poulose
2020-11-09 9:48 ` Suzuki K Poulose
2020-11-09 17:48 ` Mathieu Poirier
2020-11-09 17:48 ` Mathieu Poirier
2020-11-06 20:46 ` Mathieu Poirier
2020-11-06 20:46 ` Mathieu Poirier
2020-11-10 10:47 ` Suzuki K Poulose
2020-11-10 10:47 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 20/26] coresight: etm4x: Handle ETM architecture version Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-11-06 21:11 ` Mathieu Poirier
2020-11-06 21:11 ` Mathieu Poirier
2020-11-09 9:51 ` Suzuki K Poulose
2020-11-09 9:51 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 21/26] coresight: etm4x: Use TRCDEVARCH for component discovery Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-11-06 21:42 ` Mathieu Poirier
2020-11-06 21:42 ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 22/26] coresight: etm4x: Add necessary synchronization for sysreg access Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-11-09 18:32 ` Mathieu Poirier
2020-11-09 18:32 ` Mathieu Poirier
2020-11-10 10:11 ` Suzuki K Poulose
2020-11-10 10:11 ` Suzuki K Poulose
2020-11-10 11:40 ` John Horley
2020-11-10 11:40 ` John Horley
2020-11-10 17:35 ` Mathieu Poirier
2020-11-10 17:35 ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 23/26] coresight: etm4x: Detect system instructions support Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-11-09 20:22 ` Mathieu Poirier
2020-11-09 20:22 ` Mathieu Poirier
2020-11-10 9:31 ` Suzuki K Poulose
2020-11-10 9:31 ` Suzuki K Poulose
2020-11-10 17:33 ` Mathieu Poirier
2020-11-10 17:33 ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 24/26] coresight: etm4x: Refactor probing routine Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-11-09 20:43 ` Mathieu Poirier
2020-11-09 20:43 ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 25/26] coresight: etm4x: Add support for sysreg only devices Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-11-09 20:46 ` Mathieu Poirier
2020-11-09 20:46 ` Mathieu Poirier
2020-11-10 10:50 ` Suzuki K Poulose
2020-11-10 10:50 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 26/26] dts: bindings: coresight: ETM system register access only units Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-11-02 15:31 ` Rob Herring
2020-11-02 15:31 ` Rob Herring
2020-11-09 20:50 ` Mathieu Poirier
2020-11-09 20:50 ` Mathieu Poirier
2020-11-10 10:51 ` Suzuki K Poulose
2020-11-10 10:51 ` Suzuki K Poulose
2020-10-29 7:53 ` [PATCH v3 00/26] coresight: Support for ETM system instructions Mike Leach
2020-10-29 7:53 ` Mike Leach
2020-10-29 15:45 ` Suzuki K Poulose
2020-10-29 15:45 ` Suzuki K Poulose
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