From: Andrew Lunn <andrew@lunn.ch>
To: Marek Behun <marek.behun@nic.cz>
Cc: Pavana Sharma <pavana.sharma@digi.com>,
lkp@intel.com, ashkan.boldaji@digi.com,
clang-built-linux@googlegroups.com, davem@davemloft.net,
f.fainelli@gmail.com, gregkh@linuxfoundation.org,
kbuild-all@lists.01.org, kuba@kernel.org,
linux-kernel@vger.kernel.org, netdev@vger.kernel.org,
robh+dt@kernel.org, devicetree@vger.kernel.org,
vivien.didelot@gmail.com
Subject: Re: [PATCH v10 4/4] net: dsa: mv88e6xxx: Add support for mv88e6393x family of Marvell
Date: Fri, 20 Nov 2020 02:54:36 +0100 [thread overview]
Message-ID: <20201120015436.GC1804098@lunn.ch> (raw)
In-Reply-To: <20201120024311.5021d6b7@nic.cz>
On Fri, Nov 20, 2020 at 02:43:11AM +0100, Marek Behun wrote:
> Hi Andrew,
>
> On Fri, 20 Nov 2020 02:29:06 +0100
> Andrew Lunn <andrew@lunn.ch> wrote:
>
> > > + if (speed >= 2500 && port > 0 && port < 9)
> > > + return -EOPNOTSUPP;
> >
> > Maybe i'm missing something, but it looks like at this point you can
> > call
> >
> > return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true, duplex);
>
> He can't. That function does not support speed 5000. You can't simply
> add it, because it clashes with register value for speed 2500 on
> previous switches (Peridot, Topaz).
>
> Amethyst reg val Peridot + Topaz reg val
> 2500 SPD_1000 | ALT_BIT SPD_10000 | ALT_BIT
> 5000 SPD_10000 | ALT_BIT not supported
> 10000 SPD_UNFORCED SPD_UNFORCED
Hi Marek
O.K, as i said, i might be missing something :-)
I think a comment would be nice, pointing this out. Otherwise somebody
might try refactoring it, and make the same mistake!
Andrew
WARNING: multiple messages have this Message-ID (diff)
From: Andrew Lunn <andrew@lunn.ch>
To: kbuild-all@lists.01.org
Subject: Re: [PATCH v10 4/4] net: dsa: mv88e6xxx: Add support for mv88e6393x family of Marvell
Date: Fri, 20 Nov 2020 02:54:36 +0100 [thread overview]
Message-ID: <20201120015436.GC1804098@lunn.ch> (raw)
In-Reply-To: <20201120024311.5021d6b7@nic.cz>
[-- Attachment #1: Type: text/plain, Size: 990 bytes --]
On Fri, Nov 20, 2020 at 02:43:11AM +0100, Marek Behun wrote:
> Hi Andrew,
>
> On Fri, 20 Nov 2020 02:29:06 +0100
> Andrew Lunn <andrew@lunn.ch> wrote:
>
> > > + if (speed >= 2500 && port > 0 && port < 9)
> > > + return -EOPNOTSUPP;
> >
> > Maybe i'm missing something, but it looks like at this point you can
> > call
> >
> > return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true, duplex);
>
> He can't. That function does not support speed 5000. You can't simply
> add it, because it clashes with register value for speed 2500 on
> previous switches (Peridot, Topaz).
>
> Amethyst reg val Peridot + Topaz reg val
> 2500 SPD_1000 | ALT_BIT SPD_10000 | ALT_BIT
> 5000 SPD_10000 | ALT_BIT not supported
> 10000 SPD_UNFORCED SPD_UNFORCED
Hi Marek
O.K, as i said, i might be missing something :-)
I think a comment would be nice, pointing this out. Otherwise somebody
might try refactoring it, and make the same mistake!
Andrew
next prev parent reply other threads:[~2020-11-20 1:55 UTC|newest]
Thread overview: 136+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <djc@djc.id.au; danc86@gmail.com[PATCH v2] Add support for mv88e6393x family of Marvell.>
2020-10-16 2:09 ` [PATCH v3] Add support for mv88e6393x family of Marvell Pavana Sharma
2020-10-16 2:37 ` Florian Fainelli
2020-10-17 19:30 ` Andrew Lunn
2020-10-26 5:52 ` [PATCH v4 0/3] " Pavana Sharma
2020-10-26 5:54 ` [PATCH v4 1/3] " Pavana Sharma
2020-10-26 8:58 ` kernel test robot
2020-10-26 8:58 ` kernel test robot
2020-10-27 19:10 ` kernel test robot
2020-10-27 19:10 ` kernel test robot
2020-10-26 5:58 ` [PATCH v4 2/3] Add phy interface for 5GBASER mode Pavana Sharma
2020-10-26 13:38 ` Andrew Lunn
2020-10-26 13:42 ` Florian Fainelli
2020-10-26 5:58 ` [PATCH v4 3/3] Change serdes lane parameter from u8 type to int Pavana Sharma
2020-10-26 13:43 ` [PATCH v4 0/3] Add support for mv88e6393x family of Marvell Florian Fainelli
2020-10-28 0:07 ` [PATCH v5 " Pavana Sharma
2020-10-28 0:08 ` [PATCH v5 1/3] net: phy: Add 5GBASER interface mode Pavana Sharma
2020-10-28 12:03 ` Andrew Lunn
2020-10-28 0:09 ` [PATCH v5 2/3] dt-bindings: net: Add 5GBASER phy " Pavana Sharma
2020-10-28 12:03 ` Andrew Lunn
2020-10-28 0:09 ` [PATCH v5 3/3] net: dsa: mv88e6xxx: Add support for mv88e6393x family of Marvell Pavana Sharma
2020-10-28 2:03 ` Marek Behun
2020-10-28 12:21 ` Andrew Lunn
2020-10-29 5:40 ` [PATCH v6 0/4] " Pavana Sharma
2020-10-29 5:41 ` [PATCH v6 1/4] dt-bindings: net: Add 5GBASER phy interface mode Pavana Sharma
2020-10-29 5:42 ` [PATCH v6 2/4] net: phy: Add 5GBASER " Pavana Sharma
2020-10-29 6:11 ` Marek Behun
2020-10-29 12:42 ` Andrew Lunn
2020-10-29 5:42 ` [PATCH v6 3/4] net: dsa: mv88e6xxx: Add support for mv88e6393x family of Marvell Pavana Sharma
2020-10-29 6:31 ` Marek Behun
2020-11-02 6:40 ` [PATCH v7 0/4] " Pavana Sharma
2020-11-02 6:41 ` [PATCH v7 1/4] dt-bindings: net: Add 5GBASER phy interface mode Pavana Sharma
2020-11-02 6:42 ` [PATCH v7 2/4] net: phy: Add 5GBASER " Pavana Sharma
2020-11-02 13:09 ` Andrew Lunn
2020-11-03 1:34 ` Pavana Sharma
2020-11-03 2:12 ` Florian Fainelli
2020-11-03 3:16 ` Andrew Lunn
2020-11-03 8:48 ` [PATCH v8 0/4] Add support for mv88e6393x family of Marvell Pavana Sharma
2020-11-03 8:49 ` [PATCH v8 1/4] dt-bindings: net: Add 5GBASER phy interface mode Pavana Sharma
2020-11-06 1:42 ` Jakub Kicinski
2020-11-03 8:49 ` [PATCH v8 2/4] net: phy: Add 5GBASER " Pavana Sharma
2020-11-03 8:50 ` [PATCH v8 3/4] net: dsa: mv88e6xxx: Change serdes lane parameter from u8 type to int Pavana Sharma
2020-11-06 1:40 ` Jakub Kicinski
2020-11-03 8:50 ` [PATCH v8 4/4] net: dsa: mv88e6xxx: Add support for mv88e6393x family of Marvell Pavana Sharma
2020-11-06 1:52 ` Jakub Kicinski
2020-11-19 8:01 ` [PATCH v9 0/4] " Pavana Sharma
2020-11-19 8:02 ` [PATCH v9 1/4] dt-bindings: net: Add 5GBASER phy interface mode Pavana Sharma
2020-11-19 8:03 ` [PATCH v9 2/4] net: phy: Add 5GBASER " Pavana Sharma
2020-11-19 8:03 ` [PATCH v9 3/4] net: dsa: mv88e6xxx: Change serdes lane parameter from u8 type to int Pavana Sharma
2020-11-19 8:04 ` [PATCH v9 4/4] net: dsa: mv88e6xxx: Add support for mv88e6393x family of Marvell Pavana Sharma
2020-11-19 15:33 ` kernel test robot
2020-11-19 15:33 ` kernel test robot
2020-11-19 19:12 ` kernel test robot
2020-11-19 19:12 ` kernel test robot
2020-11-20 0:24 ` [PATCH v10 0/4] " Pavana Sharma
2020-11-20 0:24 ` Pavana Sharma
2020-11-20 0:25 ` [PATCH v10 1/4] dt-bindings: net: Add 5GBASER phy interface mode Pavana Sharma
2020-11-20 0:25 ` Pavana Sharma
2020-11-20 0:52 ` Andrew Lunn
2020-11-20 0:52 ` Andrew Lunn
2020-11-20 0:25 ` [PATCH v10 2/4] net: phy: Add 5GBASER " Pavana Sharma
2020-11-20 0:25 ` Pavana Sharma
2020-11-20 0:55 ` Andrew Lunn
2020-11-20 0:55 ` Andrew Lunn
2020-11-20 0:26 ` [PATCH v10 3/4] net: dsa: mv88e6xxx: Change serdes lane parameter from u8 type to int Pavana Sharma
2020-11-20 0:26 ` Pavana Sharma
2020-11-20 0:59 ` Andrew Lunn
2020-11-20 0:59 ` Andrew Lunn
2020-11-20 0:26 ` [PATCH v10 4/4] net: dsa: mv88e6xxx: Add support for mv88e6393x family of Marvell Pavana Sharma
2020-11-20 0:26 ` Pavana Sharma
2020-11-20 1:29 ` Andrew Lunn
2020-11-20 1:29 ` Andrew Lunn
2020-11-20 1:43 ` Marek Behun
2020-11-20 1:43 ` Marek Behun
2020-11-20 1:54 ` Andrew Lunn [this message]
2020-11-20 1:54 ` Andrew Lunn
2020-12-09 5:02 ` [PATCH v11 0/4] " Pavana Sharma
2020-12-09 5:02 ` Pavana Sharma
2020-12-09 5:03 ` [PATCH v11 1/4] dt-bindings: net: Add 5GBASER phy interface mode Pavana Sharma
2020-12-09 5:03 ` Pavana Sharma
2020-12-09 23:15 ` Andrew Lunn
2020-12-09 23:15 ` Andrew Lunn
2020-12-10 13:43 ` Pavana Sharma
2020-12-10 13:43 ` Pavana Sharma
2020-12-09 5:04 ` [PATCH v11 2/4] net: phy: Add 5GBASER " Pavana Sharma
2020-12-09 5:04 ` Pavana Sharma
2020-12-09 23:18 ` Andrew Lunn
2020-12-09 23:18 ` Andrew Lunn
2020-12-09 5:05 ` [PATCH v11 3/4] net: dsa: mv88e6xxx: Change serdes lane parameter type from u8 type to int Pavana Sharma
2020-12-09 5:05 ` Pavana Sharma
2020-12-09 23:24 ` Andrew Lunn
2020-12-09 23:24 ` Andrew Lunn
2020-12-09 5:05 ` [PATCH v11 4/4] net: dsa: mv88e6xxx: Add support for mv88e6393x family of Marvell Pavana Sharma
2020-12-09 5:05 ` Pavana Sharma
2020-12-09 23:40 ` Andrew Lunn
2020-12-09 23:40 ` Andrew Lunn
2020-12-09 19:37 ` [PATCH v11 0/4] " Jakub Kicinski
2020-12-09 19:37 ` Jakub Kicinski
2020-12-11 12:44 ` [net-next PATCH v12 " Pavana Sharma
2020-12-11 12:44 ` Pavana Sharma
2020-12-11 12:46 ` [net-next PATCH v12 1/4] dt-bindings: net: Add 5GBASER phy interface mode Pavana Sharma
2020-12-11 12:46 ` Pavana Sharma
2020-12-14 22:56 ` Rob Herring
2020-12-14 22:56 ` Rob Herring
2020-12-11 12:46 ` [net-next PATCH v12 2/4] net: phy: Add 5GBASER " Pavana Sharma
2020-12-11 12:46 ` Pavana Sharma
2020-12-11 12:49 ` [net-next PATCH v12 3/4] net: dsa: mv88e6xxx: Change serdes lane parameter type from u8 type to int Pavana Sharma
2020-12-11 12:49 ` Pavana Sharma
2020-12-11 12:51 ` [net-next PATCH v12 4/4] net: dsa: mv88e6xxx: Add support for mv88e6393x family of Marvell Pavana Sharma
2020-12-11 12:51 ` Pavana Sharma
2021-01-05 12:15 ` Marek Behún
2021-01-05 12:15 ` Marek Behún
2021-01-06 0:45 ` Pavana Sharma
2021-01-06 12:20 ` Marek Behún
2021-01-06 12:20 ` Marek Behún
2021-01-05 12:37 ` patch fixing mv88e6393x SERDES IRQ for Pavana's series Marek Behún
2021-01-08 9:47 ` [net-next PATCH v13 0/4] Add support for mv88e6393x family of Marvell Pavana Sharma
2021-01-08 9:48 ` [net-next PATCH v13 1/4] dt-bindings: net: Add 5GBASER phy interface Pavana Sharma
2021-01-08 13:49 ` Andrew Lunn
2021-01-08 9:49 ` [net-next PATCH v13 2/4] net: phy: Add 5GBASER interface mode Pavana Sharma
2021-01-08 13:50 ` Andrew Lunn
2021-01-08 9:50 ` [net-next PATCH v13 3/4] net: dsa: mv88e6xxx: Change serdes lane parameter type from u8 type to int Pavana Sharma
2021-01-08 9:50 ` [net-next PATCH v13 4/4] net: dsa: mv88e6xxx: Add support for mv88e6393x family of Marvell Pavana Sharma
2021-01-08 13:51 ` Marek Behún
2021-01-08 14:02 ` Marek Behún
2021-01-08 14:36 ` [PATCH] changes for Pavana Marek Behún
2021-01-09 21:31 ` Marek Behún
2020-11-02 6:43 ` [PATCH v7 3/4] net: dsa: mv88e6xxx: Change serdes lane parameter from u8 type to int Pavana Sharma
2020-11-02 13:34 ` Andrew Lunn
2020-11-02 13:40 ` Andrew Lunn
2020-11-02 6:43 ` [PATCH v7 4/4] net: dsa: mv88e6xxx: Add support for mv88e6393x family of Marvell Pavana Sharma
2020-11-02 13:12 ` [PATCH v7 0/4] " Andrew Lunn
2020-10-29 5:43 ` [PATCH v6 4/4] net: dsa: mv88e6xxx: Change serdes lane parameter from u8 to int Pavana Sharma
2020-10-29 6:07 ` [PATCH v6 0/4] Add support for mv88e6393x family of Marvell Marek Behun
2020-10-28 23:12 ` [PATCH v5 3/3] net: dsa: mv88e6xxx: " Jakub Kicinski
2020-10-29 4:25 ` kernel test robot
2020-10-29 4:25 ` kernel test robot
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20201120015436.GC1804098@lunn.ch \
--to=andrew@lunn.ch \
--cc=ashkan.boldaji@digi.com \
--cc=clang-built-linux@googlegroups.com \
--cc=davem@davemloft.net \
--cc=devicetree@vger.kernel.org \
--cc=f.fainelli@gmail.com \
--cc=gregkh@linuxfoundation.org \
--cc=kbuild-all@lists.01.org \
--cc=kuba@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=lkp@intel.com \
--cc=marek.behun@nic.cz \
--cc=netdev@vger.kernel.org \
--cc=pavana.sharma@digi.com \
--cc=robh+dt@kernel.org \
--cc=vivien.didelot@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.