From: Rob Herring <robh@kernel.org>
To: Yash Shah <yash.shah@sifive.com>
Cc: devicetree@vger.kernel.org, aou@eecs.berkeley.edu,
anup@brainfault.org, paul.walmsley@sifive.com,
linux-kernel@vger.kernel.org, wsa@kernel.org,
sachin.ghadi@sifive.com, palmer@dabbelt.com,
sagar.kadam@sifive.com, Jonathan.Cameron@huawei.com,
linux-riscv@lists.infradead.org, bp@suse.de, sam@ravnborg.org
Subject: Re: [PATCH 1/2] RISC-V: Update l2 cache DT documentation to add support for SiFive FU740
Date: Sat, 21 Nov 2020 06:54:43 -0600 [thread overview]
Message-ID: <20201121125443.GA2076465@robh.at.kernel.org> (raw)
In-Reply-To: <1605172274-44916-1-git-send-email-yash.shah@sifive.com>
On Thu, Nov 12, 2020 at 02:41:13PM +0530, Yash Shah wrote:
> The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as
> compared to 3 in FU540. Update the DT documentation accordingly with
> "compatible" and "interrupt" property changes.
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> ---
> .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 33 +++++++++++++++++-----
> 1 file changed, 26 insertions(+), 7 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> index efc0198..4873d5c 100644
> --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> @@ -27,6 +27,7 @@ select:
> items:
> - enum:
> - sifive,fu540-c000-ccache
> + - sifive,fu740-c000-ccache
>
> required:
> - compatible
> @@ -34,7 +35,9 @@ select:
> properties:
> compatible:
> items:
> - - const: sifive,fu540-c000-ccache
> + - enum:
> + - sifive,fu540-c000-ccache
> + - sifive,fu740-c000-ccache
> - const: cache
>
> cache-block-size:
> @@ -51,12 +54,6 @@ properties:
>
> cache-unified: true
>
> - interrupts:
> - description: |
> - Must contain entries for DirError, DataError and DataFail signals.
> - minItems: 3
> - maxItems: 3
Keep this here and just change maxItems to 4. Really, what each
interrupt is should be listed out as an 'items' entry.
> -
> reg:
> maxItems: 1
>
> @@ -67,6 +64,28 @@ properties:
> The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
> The reserved memory node should be defined as per the bindings in reserved-memory.txt.
>
> +if:
> + properties:
> + compatible:
> + contains:
> + const: sifive,fu540-c000-ccache
> +
> +then:
> + properties:
> + interrupts:
> + description: |
> + Must contain entries for DirError, DataError and DataFail signals.
> + minItems: 3
> + maxItems: 3
Here you just need 'maxItems: 3'.
> +
> +else:
> + properties:
> + interrupts:
> + description: |
> + Must contain entries for DirError, DirFail, DataError, DataFail signals.
DirFail should be last so you keep the same indices.
> + minItems: 4
> + maxItems: 4
And 'minItems: 4'
> +
> additionalProperties: false
>
> required:
> --
> 2.7.4
>
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WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Yash Shah <yash.shah@sifive.com>
Cc: paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, Jonathan.Cameron@huawei.com,
wsa@kernel.org, sam@ravnborg.org, sagar.kadam@sifive.com,
anup@brainfault.org, bp@suse.de, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
sachin.ghadi@sifive.com
Subject: Re: [PATCH 1/2] RISC-V: Update l2 cache DT documentation to add support for SiFive FU740
Date: Sat, 21 Nov 2020 06:54:43 -0600 [thread overview]
Message-ID: <20201121125443.GA2076465@robh.at.kernel.org> (raw)
In-Reply-To: <1605172274-44916-1-git-send-email-yash.shah@sifive.com>
On Thu, Nov 12, 2020 at 02:41:13PM +0530, Yash Shah wrote:
> The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as
> compared to 3 in FU540. Update the DT documentation accordingly with
> "compatible" and "interrupt" property changes.
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> ---
> .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 33 +++++++++++++++++-----
> 1 file changed, 26 insertions(+), 7 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> index efc0198..4873d5c 100644
> --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> @@ -27,6 +27,7 @@ select:
> items:
> - enum:
> - sifive,fu540-c000-ccache
> + - sifive,fu740-c000-ccache
>
> required:
> - compatible
> @@ -34,7 +35,9 @@ select:
> properties:
> compatible:
> items:
> - - const: sifive,fu540-c000-ccache
> + - enum:
> + - sifive,fu540-c000-ccache
> + - sifive,fu740-c000-ccache
> - const: cache
>
> cache-block-size:
> @@ -51,12 +54,6 @@ properties:
>
> cache-unified: true
>
> - interrupts:
> - description: |
> - Must contain entries for DirError, DataError and DataFail signals.
> - minItems: 3
> - maxItems: 3
Keep this here and just change maxItems to 4. Really, what each
interrupt is should be listed out as an 'items' entry.
> -
> reg:
> maxItems: 1
>
> @@ -67,6 +64,28 @@ properties:
> The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
> The reserved memory node should be defined as per the bindings in reserved-memory.txt.
>
> +if:
> + properties:
> + compatible:
> + contains:
> + const: sifive,fu540-c000-ccache
> +
> +then:
> + properties:
> + interrupts:
> + description: |
> + Must contain entries for DirError, DataError and DataFail signals.
> + minItems: 3
> + maxItems: 3
Here you just need 'maxItems: 3'.
> +
> +else:
> + properties:
> + interrupts:
> + description: |
> + Must contain entries for DirError, DirFail, DataError, DataFail signals.
DirFail should be last so you keep the same indices.
> + minItems: 4
> + maxItems: 4
And 'minItems: 4'
> +
> additionalProperties: false
>
> required:
> --
> 2.7.4
>
next prev parent reply other threads:[~2020-11-21 23:39 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-12 9:11 [PATCH 1/2] RISC-V: Update l2 cache DT documentation to add support for SiFive FU740 Yash Shah
2020-11-12 9:11 ` Yash Shah
2020-11-12 9:11 ` [PATCH 2/2] RISC-V: sifive_l2_cache: Update L2 cache driver to support " Yash Shah
2020-11-12 9:11 ` Yash Shah
2020-11-21 12:54 ` Rob Herring [this message]
2020-11-21 12:54 ` [PATCH 1/2] RISC-V: Update l2 cache DT documentation to add support for " Rob Herring
2020-11-23 10:32 ` Yash Shah
2020-11-23 10:32 ` Yash Shah
2020-11-30 15:36 ` Rob Herring
2020-11-30 15:36 ` Rob Herring
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