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From: Matthew Brost <matthew.brost@intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 21/21] drm/i915/gt: Use ppHWSP for unshared non-semaphore related timelines
Date: Thu, 10 Dec 2020 13:28:24 -0800	[thread overview]
Message-ID: <20201210212824.GA24184@sdutt-i7> (raw)
In-Reply-To: <20201210080240.24529-21-chris@chris-wilson.co.uk>

On Thu, Dec 10, 2020 at 08:02:40AM +0000, Chris Wilson wrote:
> When we are not using semaphores with a context/engine, we can simply
> reuse the same seqno location across wraps, but we still require each
> timeline to have its own address. For LRC submission, each context is
> prefixed by a per-process HWSP, which provides us with a unique location
> for each context-local timeline. A shared timeline that is common to
> multiple contexts will continue to use a separate page.
> 
> This enables us to create position invariant contexts should we feel the
> need to relocate them.
> 

Reviewed-by: Matthew Brost <matthew.brost@intel.com>

> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
>  .../drm/i915/gt/intel_execlists_submission.c  | 37 +++++++++++--------
>  1 file changed, 22 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 8bff0559a6a9..cc1b3509d808 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -4749,6 +4749,14 @@ static struct intel_timeline *pinned_timeline(struct intel_context *ce)
>  						 page_unmask_bits(tl));
>  }
>  
> +static struct intel_timeline *pphwsp_timeline(struct intel_context *ce,
> +					      struct i915_vma *state)
> +{
> +	return __intel_timeline_create(ce->engine->gt, state,
> +				       I915_GEM_HWS_SEQNO_ADDR |
> +				       INTEL_TIMELINE_CONTEXT);
> +}
> +
>  static int __execlists_context_alloc(struct intel_context *ce,
>  				     struct intel_engine_cs *engine)
>  {
> @@ -4779,6 +4787,16 @@ static int __execlists_context_alloc(struct intel_context *ce,
>  		goto error_deref_obj;
>  	}
>  
> +	ring = intel_engine_create_ring(engine, (unsigned long)ce->ring);
> +	if (IS_ERR(ring)) {
> +		ret = PTR_ERR(ring);
> +		goto error_deref_obj;
> +	}
> +
> +	ret = populate_lr_context(ce, ctx_obj, engine, ring);
> +	if (ret)
> +		goto error_ring_free;
> +
>  	if (!page_mask_bits(ce->timeline)) {
>  		struct intel_timeline *tl;
>  
> @@ -4788,29 +4806,18 @@ static int __execlists_context_alloc(struct intel_context *ce,
>  		 */
>  		if (unlikely(ce->timeline))
>  			tl = pinned_timeline(ce);
> -		else
> +		else if (intel_engine_has_semaphores(engine))
>  			tl = intel_timeline_create(engine->gt);
> +		else
> +			tl = pphwsp_timeline(ce, vma);
>  		if (IS_ERR(tl)) {
>  			ret = PTR_ERR(tl);
> -			goto error_deref_obj;
> +			goto error_ring_free;
>  		}
>  
>  		ce->timeline = tl;
>  	}
>  
> -	ring = intel_engine_create_ring(engine, (unsigned long)ce->ring);
> -	if (IS_ERR(ring)) {
> -		ret = PTR_ERR(ring);
> -		goto error_deref_obj;
> -	}
> -
> -	ret = populate_lr_context(ce, ctx_obj, engine, ring);
> -	if (ret) {
> -		drm_dbg(&engine->i915->drm,
> -			"Failed to populate LRC: %d\n", ret);
> -		goto error_ring_free;
> -	}
> -
>  	ce->ring = ring;
>  	ce->state = vma;
>  
> -- 
> 2.20.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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  reply	other threads:[~2020-12-10 21:34 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-10  8:02 [Intel-gfx] [PATCH 01/21] drm/i915/gt: Mark legacy ring context as lost Chris Wilson
2020-12-10  8:02 ` [Intel-gfx] [PATCH 02/21] drm/i915/gt: Wean workaround selftests off GEM context Chris Wilson
2020-12-10 17:04   ` Mika Kuoppala
2020-12-10  8:02 ` [Intel-gfx] [PATCH 03/21] drm/i915/gt: Replace direct submit with direct call to tasklet Chris Wilson
2020-12-10  8:02 ` [Intel-gfx] [PATCH 04/21] drm/i915/gt: Use virtual_engine during execlists_dequeue Chris Wilson
2020-12-10  8:02 ` [Intel-gfx] [PATCH 05/21] drm/i915/gt: Decouple inflight virtual engines Chris Wilson
2020-12-10  8:02 ` [Intel-gfx] [PATCH 06/21] drm/i915/gt: Defer schedule_out until after the next dequeue Chris Wilson
2020-12-10  8:02 ` [Intel-gfx] [PATCH 07/21] drm/i915/gt: Remove virtual breadcrumb before transfer Chris Wilson
2020-12-10  8:02 ` [Intel-gfx] [PATCH 08/21] drm/i915/gt: Shrink the critical section for irq signaling Chris Wilson
2020-12-10  8:02 ` [Intel-gfx] [PATCH 09/21] drm/i915/gt: Resubmit the virtual engine on schedule-out Chris Wilson
2020-12-10  8:02 ` [Intel-gfx] [PATCH 10/21] drm/i915/gt: Simplify virtual engine handling for execlists_hold() Chris Wilson
2020-12-10  8:02 ` [Intel-gfx] [PATCH 11/21] drm/i915/gt: ce->inflight updates are now serialised Chris Wilson
2020-12-10  8:02 ` [Intel-gfx] [PATCH 12/21] drm/i915/gem: Drop free_work for GEM contexts Chris Wilson
2020-12-10 18:50   ` Matthew Brost
2020-12-10  8:02 ` [Intel-gfx] [PATCH 13/21] drm/i915/gt: Track the overall awake/busy time Chris Wilson
2020-12-10  8:02 ` [Intel-gfx] [PATCH 14/21] drm/i915: Encode fence specific waitqueue behaviour into the wait.flags Chris Wilson
2020-12-10  8:02 ` [Intel-gfx] [PATCH 15/21] drm/i915/gt: Track all timelines created using the HWSP Chris Wilson
2020-12-10 18:28   ` Matthew Brost
2020-12-10  8:02 ` [Intel-gfx] [PATCH 16/21] drm/i915/gt: Wrap intel_timeline.has_initial_breadcrumb Chris Wilson
2020-12-10  8:02 ` [Intel-gfx] [PATCH 17/21] drm/i915/gt: Track timeline GGTT offset separately from subpage offset Chris Wilson
2020-12-10 21:37   ` Matthew Brost
2020-12-10  8:02 ` [Intel-gfx] [PATCH 18/21] drm/i915/gt: Add timeline "mode" Chris Wilson
2020-12-10 19:28   ` Matthew Brost
2020-12-10 21:00     ` Chris Wilson
2020-12-10 21:18       ` Matthew Brost
2020-12-10  8:02 ` [Intel-gfx] [PATCH 19/21] drm/i915/gt: Use indices for writing into relative timelines Chris Wilson
2020-12-10 19:16   ` Matthew Brost
2020-12-10 21:05     ` Chris Wilson
2020-12-10 21:51       ` Matthew Brost
2020-12-10  8:02 ` [Intel-gfx] [PATCH 20/21] drm/i915/selftests: Exercise relative timeline modes Chris Wilson
2020-12-10  8:02 ` [Intel-gfx] [PATCH 21/21] drm/i915/gt: Use ppHWSP for unshared non-semaphore related timelines Chris Wilson
2020-12-10 21:28   ` Matthew Brost [this message]
2020-12-10  8:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [01/21] drm/i915/gt: Mark legacy ring context as lost Patchwork
2020-12-10  8:34 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2020-12-10  8:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-12-10 12:18 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-12-10 16:39 ` [Intel-gfx] [PATCH 01/21] " Mika Kuoppala
2020-12-10 17:04 ` Matthew Brost

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