All of lore.kernel.org
 help / color / mirror / Atom feed
From: Ulrich Hecht <uli+renesas@fpond.eu>
To: linux-renesas-soc@vger.kernel.org
Cc: wsa@the-dreams.de, geert@linux-m68k.org, hoai.luu.ub@renesas.com,
	Ulrich Hecht <uli+renesas@fpond.eu>
Subject: [PATCH v2 2/5] pinctrl: renesas: add I/O voltage level flag
Date: Mon, 21 Dec 2020 17:54:45 +0100	[thread overview]
Message-ID: <20201221165448.27312-3-uli+renesas@fpond.eu> (raw)
In-Reply-To: <20201221165448.27312-1-uli+renesas@fpond.eu>

This patch adds config macros describing the voltage levels available on
a pin. The current default (3.3V/1.8V) maps to zero to avoid having to
change existing PFC implementations.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
---
 drivers/pinctrl/renesas/pinctrl.c | 16 ++++++++++++++--
 drivers/pinctrl/renesas/sh_pfc.h  |  9 +++++++++
 2 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/renesas/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c
index ac542d278a38..85a182191d7d 100644
--- a/drivers/pinctrl/renesas/pinctrl.c
+++ b/drivers/pinctrl/renesas/pinctrl.c
@@ -634,6 +634,9 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
 	}
 
 	case PIN_CONFIG_POWER_SOURCE: {
+		int idx = sh_pfc_get_pin_index(pfc, _pin);
+		const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
+		int lower_voltage;
 		u32 pocctrl, val;
 		int bit;
 
@@ -648,7 +651,10 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
 		val = sh_pfc_read(pfc, pocctrl);
 		spin_unlock_irqrestore(&pfc->lock, flags);
 
-		arg = (val & BIT(bit)) ? 3300 : 1800;
+		lower_voltage = (pin->configs & SH_PFC_PIN_VOLTAGE_25_33) ?
+			2500 : 1800;
+
+		arg = (val & BIT(bit)) ? 3300 : lower_voltage;
 		break;
 	}
 
@@ -702,6 +708,9 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
 
 		case PIN_CONFIG_POWER_SOURCE: {
 			unsigned int mV = pinconf_to_config_argument(configs[i]);
+			int idx = sh_pfc_get_pin_index(pfc, _pin);
+			const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
+			int lower_voltage;
 			u32 pocctrl, val;
 			int bit;
 
@@ -712,7 +721,10 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
 			if (WARN(bit < 0, "invalid pin %#x", _pin))
 				return bit;
 
-			if (mV != 1800 && mV != 3300)
+			lower_voltage = (pin->configs & SH_PFC_PIN_VOLTAGE_25_33) ?
+				2500 : 1800;
+
+			if (mV != lower_voltage && mV != 3300)
 				return -EINVAL;
 
 			spin_lock_irqsave(&pfc->lock, flags);
diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h
index dc484c13f59c..00bfda90a7b7 100644
--- a/drivers/pinctrl/renesas/sh_pfc.h
+++ b/drivers/pinctrl/renesas/sh_pfc.h
@@ -31,6 +31,15 @@ enum {
 					 SH_PFC_PIN_CFG_PULL_DOWN)
 #define SH_PFC_PIN_CFG_IO_VOLTAGE	(1 << 4)
 #define SH_PFC_PIN_CFG_DRIVE_STRENGTH	(1 << 5)
+
+#define SH_PFC_PIN_VOLTAGE_18_33	(0 << 6)
+#define SH_PFC_PIN_VOLTAGE_25_33	(1 << 6)
+
+#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33	(SH_PFC_PIN_CFG_IO_VOLTAGE | \
+					 SH_PFC_PIN_VOLTAGE_18_33)
+#define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33	(SH_PFC_PIN_CFG_IO_VOLTAGE | \
+					 SH_PFC_PIN_VOLTAGE_25_33)
+
 #define SH_PFC_PIN_CFG_NO_GPIO		(1 << 31)
 
 struct sh_pfc_pin {
-- 
2.20.1


  parent reply	other threads:[~2020-12-21 16:57 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-21 16:54 [PATCH v2 0/5] pinctrl: renesas: basic R8A779A0 (V3U) support Ulrich Hecht
2020-12-21 16:54 ` [PATCH v2 1/5] pinctrl: renesas: implement unlock register masks Ulrich Hecht
2020-12-22 10:31   ` Geert Uytterhoeven
2020-12-21 16:54 ` Ulrich Hecht [this message]
2020-12-22 10:45   ` [PATCH v2 2/5] pinctrl: renesas: add I/O voltage level flag Geert Uytterhoeven
2020-12-22 16:47     ` Ulrich Hecht
2020-12-22 18:44       ` Geert Uytterhoeven
2020-12-22 11:44   ` Geert Uytterhoeven
2020-12-22 16:47     ` Ulrich Hecht
2020-12-21 16:54 ` [PATCH v2 3/5] pinctrl: renesas: add PORT_GP_CFG_{2,31} macros Ulrich Hecht
2020-12-22 10:35   ` Geert Uytterhoeven
2020-12-21 16:54 ` [PATCH v2 5/5] pinctrl: renesas: r8a779a0: Add SCIF pins, groups and functions Ulrich Hecht
2020-12-22 10:05   ` Geert Uytterhoeven
2020-12-28 12:17   ` Wolfram Sang
     [not found] ` <20201221165448.27312-5-uli+renesas@fpond.eu>
2020-12-22 11:42   ` [PATCH v2 4/5] pinctrl: renesas: Initial R8A779A0 (V3U) PFC support Geert Uytterhoeven
2021-01-12 16:58     ` Ulrich Hecht
2020-12-27 20:27   ` Wolfram Sang
2020-12-23 15:59 ` [PATCH v2 0/5] pinctrl: renesas: basic R8A779A0 (V3U) support Wolfram Sang

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20201221165448.27312-3-uli+renesas@fpond.eu \
    --to=uli+renesas@fpond.eu \
    --cc=geert@linux-m68k.org \
    --cc=hoai.luu.ub@renesas.com \
    --cc=linux-renesas-soc@vger.kernel.org \
    --cc=wsa@the-dreams.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.