From: Ulrich Hecht <uli+renesas@fpond.eu>
To: linux-renesas-soc@vger.kernel.org
Cc: wsa@the-dreams.de, geert@linux-m68k.org, hoai.luu.ub@renesas.com,
Ulrich Hecht <uli+renesas@fpond.eu>
Subject: [PATCH v2 3/5] pinctrl: renesas: add PORT_GP_CFG_{2,31} macros
Date: Mon, 21 Dec 2020 17:54:46 +0100 [thread overview]
Message-ID: <20201221165448.27312-4-uli+renesas@fpond.eu> (raw)
In-Reply-To: <20201221165448.27312-1-uli+renesas@fpond.eu>
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
---
drivers/pinctrl/renesas/sh_pfc.h | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h
index 00bfda90a7b7..747dfdb331bd 100644
--- a/drivers/pinctrl/renesas/sh_pfc.h
+++ b/drivers/pinctrl/renesas/sh_pfc.h
@@ -460,6 +460,11 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
#define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
+#define PORT_GP_CFG_2(bank, fn, sfx, cfg) \
+ PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
+ PORT_GP_CFG_1(bank, 1, fn, sfx, cfg)
+#define PORT_GP_2(bank, fn, sfx) PORT_GP_CFG_2(bank, fn, sfx, 0)
+
#define PORT_GP_CFG_4(bank, fn, sfx, cfg) \
PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \
@@ -581,9 +586,13 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
#define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0)
-#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
+#define PORT_GP_CFG_31(bank, fn, sfx, cfg) \
PORT_GP_CFG_30(bank, fn, sfx, cfg), \
- PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), \
+ PORT_GP_CFG_1(bank, 30, fn, sfx, cfg)
+#define PORT_GP_31(bank, fn, sfx) PORT_GP_CFG_31(bank, fn, sfx, 0)
+
+#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
+ PORT_GP_CFG_31(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
#define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0)
--
2.20.1
next prev parent reply other threads:[~2020-12-21 16:57 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-21 16:54 [PATCH v2 0/5] pinctrl: renesas: basic R8A779A0 (V3U) support Ulrich Hecht
2020-12-21 16:54 ` [PATCH v2 1/5] pinctrl: renesas: implement unlock register masks Ulrich Hecht
2020-12-22 10:31 ` Geert Uytterhoeven
2020-12-21 16:54 ` [PATCH v2 2/5] pinctrl: renesas: add I/O voltage level flag Ulrich Hecht
2020-12-22 10:45 ` Geert Uytterhoeven
2020-12-22 16:47 ` Ulrich Hecht
2020-12-22 18:44 ` Geert Uytterhoeven
2020-12-22 11:44 ` Geert Uytterhoeven
2020-12-22 16:47 ` Ulrich Hecht
2020-12-21 16:54 ` Ulrich Hecht [this message]
2020-12-22 10:35 ` [PATCH v2 3/5] pinctrl: renesas: add PORT_GP_CFG_{2,31} macros Geert Uytterhoeven
2020-12-21 16:54 ` [PATCH v2 5/5] pinctrl: renesas: r8a779a0: Add SCIF pins, groups and functions Ulrich Hecht
2020-12-22 10:05 ` Geert Uytterhoeven
2020-12-28 12:17 ` Wolfram Sang
2020-12-23 15:59 ` [PATCH v2 0/5] pinctrl: renesas: basic R8A779A0 (V3U) support Wolfram Sang
[not found] ` <20201221165448.27312-5-uli+renesas@fpond.eu>
2020-12-22 11:42 ` [PATCH v2 4/5] pinctrl: renesas: Initial R8A779A0 (V3U) PFC support Geert Uytterhoeven
2021-01-12 16:58 ` Ulrich Hecht
2020-12-27 20:27 ` Wolfram Sang
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