* [PATCH RESEND 1/2] MIPS: cacheinfo: Add missing VCache
@ 2020-12-30 3:39 Jiaxun Yang
2020-12-30 3:39 ` [PATCH 2/2] MIPS: Loongson64: Set cluster for cores Jiaxun Yang
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Jiaxun Yang @ 2020-12-30 3:39 UTC (permalink / raw)
To: linux-mips
Cc: Jiaxun Yang, Tiezhu Yang, Thomas Bogendoerfer, Huacai Chen,
linux-kernel
Victim Cache is defined by Loongson as per-core unified
private Cache.
Add this into cacheinfo and make cache levels selfincrement
instead of hardcode levels.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Tiezhu Yang <yangtiezhu@loongson.cn>
Tested-by: Tiezhu Yang <yangtiezhu@loongson.cn>
---
arch/mips/kernel/cacheinfo.c | 34 ++++++++++++++++++++++++++--------
1 file changed, 26 insertions(+), 8 deletions(-)
diff --git a/arch/mips/kernel/cacheinfo.c b/arch/mips/kernel/cacheinfo.c
index 47312c529410..83548331ee94 100644
--- a/arch/mips/kernel/cacheinfo.c
+++ b/arch/mips/kernel/cacheinfo.c
@@ -35,6 +35,11 @@ static int __init_cache_level(unsigned int cpu)
leaves += (c->icache.waysize) ? 2 : 1;
+ if (c->vcache.waysize) {
+ levels++;
+ leaves++;
+ }
+
if (c->scache.waysize) {
levels++;
leaves++;
@@ -74,25 +79,38 @@ static int __populate_cache_leaves(unsigned int cpu)
struct cpuinfo_mips *c = ¤t_cpu_data;
struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
struct cacheinfo *this_leaf = this_cpu_ci->info_list;
+ int level = 1;
if (c->icache.waysize) {
- /* L1 caches are per core */
+ /* D/I caches are per core */
fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map);
- populate_cache(dcache, this_leaf, 1, CACHE_TYPE_DATA);
+ populate_cache(dcache, this_leaf, level, CACHE_TYPE_DATA);
fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map);
- populate_cache(icache, this_leaf, 1, CACHE_TYPE_INST);
+ populate_cache(icache, this_leaf, level, CACHE_TYPE_INST);
+ level++;
} else {
- populate_cache(dcache, this_leaf, 1, CACHE_TYPE_UNIFIED);
+ populate_cache(dcache, this_leaf, level, CACHE_TYPE_UNIFIED);
+ level++;
+ }
+
+ if (c->vcache.waysize) {
+ /* Vcache is per core as well */
+ fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map);
+ populate_cache(vcache, this_leaf, level, CACHE_TYPE_UNIFIED);
+ level++;
}
if (c->scache.waysize) {
- /* L2 cache is per cluster */
+ /* Scache is per cluster */
fill_cpumask_cluster(cpu, &this_leaf->shared_cpu_map);
- populate_cache(scache, this_leaf, 2, CACHE_TYPE_UNIFIED);
+ populate_cache(scache, this_leaf, level, CACHE_TYPE_UNIFIED);
+ level++;
}
- if (c->tcache.waysize)
- populate_cache(tcache, this_leaf, 3, CACHE_TYPE_UNIFIED);
+ if (c->tcache.waysize) {
+ populate_cache(tcache, this_leaf, level, CACHE_TYPE_UNIFIED);
+ level++;
+ }
this_cpu_ci->cpu_map_populated = true;
--
2.30.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 2/2] MIPS: Loongson64: Set cluster for cores
2020-12-30 3:39 [PATCH RESEND 1/2] MIPS: cacheinfo: Add missing VCache Jiaxun Yang
@ 2020-12-30 3:39 ` Jiaxun Yang
2020-12-31 0:27 ` Huacai Chen
2021-01-04 10:42 ` Thomas Bogendoerfer
2020-12-31 0:25 ` [PATCH RESEND 1/2] MIPS: cacheinfo: Add missing VCache Huacai Chen
2021-01-04 10:42 ` Thomas Bogendoerfer
2 siblings, 2 replies; 8+ messages in thread
From: Jiaxun Yang @ 2020-12-30 3:39 UTC (permalink / raw)
To: linux-mips
Cc: Jiaxun Yang, Tiezhu Yang, Thomas Bogendoerfer, Huacai Chen,
linux-kernel
cluster is required for cacheinfo to set shared_cpu_map correctly.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Tiezhu Yang <yangtiezhu@loongson.cn>
Tested-by: Tiezhu Yang <yangtiezhu@loongson.cn>
---
arch/mips/loongson64/smp.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c
index e744e1bee49e..fae3a97d853c 100644
--- a/arch/mips/loongson64/smp.c
+++ b/arch/mips/loongson64/smp.c
@@ -403,6 +403,8 @@ static void __init loongson3_smp_setup(void)
__cpu_number_map[i] = num;
__cpu_logical_map[num] = i;
set_cpu_possible(num, true);
+ /* Loongson processors are always grouped by 4 */
+ cpu_set_cluster(&cpu_data[num], i / 4);
num++;
}
i++;
--
2.30.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] MIPS: Loongson64: Set cluster for cores
2020-12-30 3:39 ` [PATCH 2/2] MIPS: Loongson64: Set cluster for cores Jiaxun Yang
@ 2020-12-31 0:27 ` Huacai Chen
2021-01-04 10:42 ` Thomas Bogendoerfer
1 sibling, 0 replies; 8+ messages in thread
From: Huacai Chen @ 2020-12-31 0:27 UTC (permalink / raw)
To: Jiaxun Yang; +Cc: open list:MIPS, Tiezhu Yang, Thomas Bogendoerfer, LKML
Reviewed-by: Huacai Chen <chenhuacai@kernel.org>
On Wed, Dec 30, 2020 at 11:43 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>
> cluster is required for cacheinfo to set shared_cpu_map correctly.
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Reviewed-by: Tiezhu Yang <yangtiezhu@loongson.cn>
> Tested-by: Tiezhu Yang <yangtiezhu@loongson.cn>
> ---
> arch/mips/loongson64/smp.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c
> index e744e1bee49e..fae3a97d853c 100644
> --- a/arch/mips/loongson64/smp.c
> +++ b/arch/mips/loongson64/smp.c
> @@ -403,6 +403,8 @@ static void __init loongson3_smp_setup(void)
> __cpu_number_map[i] = num;
> __cpu_logical_map[num] = i;
> set_cpu_possible(num, true);
> + /* Loongson processors are always grouped by 4 */
> + cpu_set_cluster(&cpu_data[num], i / 4);
> num++;
> }
> i++;
> --
> 2.30.0
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] MIPS: Loongson64: Set cluster for cores
2020-12-30 3:39 ` [PATCH 2/2] MIPS: Loongson64: Set cluster for cores Jiaxun Yang
2020-12-31 0:27 ` Huacai Chen
@ 2021-01-04 10:42 ` Thomas Bogendoerfer
1 sibling, 0 replies; 8+ messages in thread
From: Thomas Bogendoerfer @ 2021-01-04 10:42 UTC (permalink / raw)
To: Jiaxun Yang; +Cc: linux-mips, Tiezhu Yang, Huacai Chen, linux-kernel
On Wed, Dec 30, 2020 at 11:39:49AM +0800, Jiaxun Yang wrote:
> cluster is required for cacheinfo to set shared_cpu_map correctly.
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Reviewed-by: Tiezhu Yang <yangtiezhu@loongson.cn>
> Tested-by: Tiezhu Yang <yangtiezhu@loongson.cn>
> ---
> arch/mips/loongson64/smp.c | 2 ++
> 1 file changed, 2 insertions(+)
applied to mips-next.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH RESEND 1/2] MIPS: cacheinfo: Add missing VCache
2020-12-30 3:39 [PATCH RESEND 1/2] MIPS: cacheinfo: Add missing VCache Jiaxun Yang
2020-12-30 3:39 ` [PATCH 2/2] MIPS: Loongson64: Set cluster for cores Jiaxun Yang
@ 2020-12-31 0:25 ` Huacai Chen
2021-01-04 10:42 ` Thomas Bogendoerfer
2 siblings, 0 replies; 8+ messages in thread
From: Huacai Chen @ 2020-12-31 0:25 UTC (permalink / raw)
To: Jiaxun Yang; +Cc: open list:MIPS, Tiezhu Yang, Thomas Bogendoerfer, LKML
Hi, Jiaxun,
On Wed, Dec 30, 2020 at 11:41 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>
> Victim Cache is defined by Loongson as per-core unified
> private Cache.
> Add this into cacheinfo and make cache levels selfincrement
> instead of hardcode levels.
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Reviewed-by: Tiezhu Yang <yangtiezhu@loongson.cn>
> Tested-by: Tiezhu Yang <yangtiezhu@loongson.cn>
> ---
> arch/mips/kernel/cacheinfo.c | 34 ++++++++++++++++++++++++++--------
> 1 file changed, 26 insertions(+), 8 deletions(-)
>
> diff --git a/arch/mips/kernel/cacheinfo.c b/arch/mips/kernel/cacheinfo.c
> index 47312c529410..83548331ee94 100644
> --- a/arch/mips/kernel/cacheinfo.c
> +++ b/arch/mips/kernel/cacheinfo.c
> @@ -35,6 +35,11 @@ static int __init_cache_level(unsigned int cpu)
>
> leaves += (c->icache.waysize) ? 2 : 1;
>
> + if (c->vcache.waysize) {
> + levels++;
> + leaves++;
> + }
> +
> if (c->scache.waysize) {
> levels++;
> leaves++;
> @@ -74,25 +79,38 @@ static int __populate_cache_leaves(unsigned int cpu)
> struct cpuinfo_mips *c = ¤t_cpu_data;
> struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
> struct cacheinfo *this_leaf = this_cpu_ci->info_list;
> + int level = 1;
>
> if (c->icache.waysize) {
> - /* L1 caches are per core */
> + /* D/I caches are per core */
It seems "I/D caches" is better than "D/I caches", see
arch/mips/include/asm/cpu-info.h and search cache_desc.
Huacai
> fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map);
> - populate_cache(dcache, this_leaf, 1, CACHE_TYPE_DATA);
> + populate_cache(dcache, this_leaf, level, CACHE_TYPE_DATA);
> fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map);
> - populate_cache(icache, this_leaf, 1, CACHE_TYPE_INST);
> + populate_cache(icache, this_leaf, level, CACHE_TYPE_INST);
> + level++;
> } else {
> - populate_cache(dcache, this_leaf, 1, CACHE_TYPE_UNIFIED);
> + populate_cache(dcache, this_leaf, level, CACHE_TYPE_UNIFIED);
> + level++;
> + }
> +
> + if (c->vcache.waysize) {
> + /* Vcache is per core as well */
> + fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map);
> + populate_cache(vcache, this_leaf, level, CACHE_TYPE_UNIFIED);
> + level++;
> }
>
> if (c->scache.waysize) {
> - /* L2 cache is per cluster */
> + /* Scache is per cluster */
> fill_cpumask_cluster(cpu, &this_leaf->shared_cpu_map);
> - populate_cache(scache, this_leaf, 2, CACHE_TYPE_UNIFIED);
> + populate_cache(scache, this_leaf, level, CACHE_TYPE_UNIFIED);
> + level++;
> }
>
> - if (c->tcache.waysize)
> - populate_cache(tcache, this_leaf, 3, CACHE_TYPE_UNIFIED);
> + if (c->tcache.waysize) {
> + populate_cache(tcache, this_leaf, level, CACHE_TYPE_UNIFIED);
> + level++;
> + }
>
> this_cpu_ci->cpu_map_populated = true;
>
> --
> 2.30.0
>
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH RESEND 1/2] MIPS: cacheinfo: Add missing VCache
2020-12-30 3:39 [PATCH RESEND 1/2] MIPS: cacheinfo: Add missing VCache Jiaxun Yang
2020-12-30 3:39 ` [PATCH 2/2] MIPS: Loongson64: Set cluster for cores Jiaxun Yang
2020-12-31 0:25 ` [PATCH RESEND 1/2] MIPS: cacheinfo: Add missing VCache Huacai Chen
@ 2021-01-04 10:42 ` Thomas Bogendoerfer
2 siblings, 0 replies; 8+ messages in thread
From: Thomas Bogendoerfer @ 2021-01-04 10:42 UTC (permalink / raw)
To: Jiaxun Yang; +Cc: linux-mips, Tiezhu Yang, Huacai Chen, linux-kernel
On Wed, Dec 30, 2020 at 11:39:48AM +0800, Jiaxun Yang wrote:
> Victim Cache is defined by Loongson as per-core unified
> private Cache.
> Add this into cacheinfo and make cache levels selfincrement
> instead of hardcode levels.
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Reviewed-by: Tiezhu Yang <yangtiezhu@loongson.cn>
> Tested-by: Tiezhu Yang <yangtiezhu@loongson.cn>
> ---
> arch/mips/kernel/cacheinfo.c | 34 ++++++++++++++++++++++++++--------
> 1 file changed, 26 insertions(+), 8 deletions(-)
applied to mips-next.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/2] MIPS: cacheinfo: Add missing VCache
@ 2020-03-26 10:59 Jiaxun Yang
2020-03-26 10:59 ` [PATCH 2/2] MIPS: Loongson64: Set cluster for cores Jiaxun Yang
2020-03-27 1:47 ` [PATCH 1/2] MIPS: cacheinfo: Add missing VCache Jiaxun Yang
0 siblings, 2 replies; 8+ messages in thread
From: Jiaxun Yang @ 2020-03-26 10:59 UTC (permalink / raw)
To: linux-mips; +Cc: tsbogend, chenhc, Jiaxun Yang
Victim Cache is defined by Loongson as per-core unified
private Cache.
Add this into cacheinfo and make cache levels selfincrement
instead of hardcode levels.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/kernel/cacheinfo.c | 34 ++++++++++++++++++++++++++--------
1 file changed, 26 insertions(+), 8 deletions(-)
diff --git a/arch/mips/kernel/cacheinfo.c b/arch/mips/kernel/cacheinfo.c
index 47312c529410..c56b038aaad8 100644
--- a/arch/mips/kernel/cacheinfo.c
+++ b/arch/mips/kernel/cacheinfo.c
@@ -35,6 +35,11 @@ static int __init_cache_level(unsigned int cpu)
leaves += (c->icache.waysize) ? 2 : 1;
+ if (c->vcache.waysize) {
+ levels++;
+ leaves++;
+ }
+
if (c->scache.waysize) {
levels++;
leaves++;
@@ -74,25 +79,38 @@ static int __populate_cache_leaves(unsigned int cpu)
struct cpuinfo_mips *c = ¤t_cpu_data;
struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
struct cacheinfo *this_leaf = this_cpu_ci->info_list;
+ int level = 1;
if (c->icache.waysize) {
- /* L1 caches are per core */
+ /* D/I caches are per core */
fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map);
- populate_cache(dcache, this_leaf, 1, CACHE_TYPE_DATA);
+ populate_cache(dcache, this_leaf, level, CACHE_TYPE_DATA);
fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map);
- populate_cache(icache, this_leaf, 1, CACHE_TYPE_INST);
+ populate_cache(icache, this_leaf, level, CACHE_TYPE_INST);
+ level++;
} else {
- populate_cache(dcache, this_leaf, 1, CACHE_TYPE_UNIFIED);
+ populate_cache(dcache, this_leaf, level, CACHE_TYPE_UNIFIED);
+ level++;
+ }
+
+ if (c->vcache.waysize) {
+ /* Vcache is per core as well */
+ fill_cpumask_cluster(cpu, &this_leaf->shared_cpu_map);
+ populate_cache(vcache, this_leaf, level, CACHE_TYPE_UNIFIED);
+ level++;
}
if (c->scache.waysize) {
- /* L2 cache is per cluster */
+ /* Scache is per cluster */
fill_cpumask_cluster(cpu, &this_leaf->shared_cpu_map);
- populate_cache(scache, this_leaf, 2, CACHE_TYPE_UNIFIED);
+ populate_cache(scache, this_leaf, level, CACHE_TYPE_UNIFIED);
+ level++;
}
- if (c->tcache.waysize)
- populate_cache(tcache, this_leaf, 3, CACHE_TYPE_UNIFIED);
+ if (c->tcache.waysize) {
+ populate_cache(tcache, this_leaf, level, CACHE_TYPE_UNIFIED);
+ level++;
+ }
this_cpu_ci->cpu_map_populated = true;
--
2.26.0.rc2
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 2/2] MIPS: Loongson64: Set cluster for cores
2020-03-26 10:59 [PATCH " Jiaxun Yang
@ 2020-03-26 10:59 ` Jiaxun Yang
2020-03-27 1:47 ` [PATCH 1/2] MIPS: cacheinfo: Add missing VCache Jiaxun Yang
1 sibling, 0 replies; 8+ messages in thread
From: Jiaxun Yang @ 2020-03-26 10:59 UTC (permalink / raw)
To: linux-mips; +Cc: tsbogend, chenhc, Jiaxun Yang
cluster is required for cacheinfo to set shared_cpu_map correctly.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/loongson64/smp.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c
index e1fe8bbb377d..257cbb3d2656 100644
--- a/arch/mips/loongson64/smp.c
+++ b/arch/mips/loongson64/smp.c
@@ -404,6 +404,8 @@ static void __init loongson3_smp_setup(void)
__cpu_number_map[i] = num;
__cpu_logical_map[num] = i;
set_cpu_possible(num, true);
+ /* Loongson processors are always grouped by 4 */
+ cpu_set_cluster(&cpu_data[i], i / 4);
num++;
}
i++;
--
2.26.0.rc2
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 1/2] MIPS: cacheinfo: Add missing VCache
2020-03-26 10:59 [PATCH " Jiaxun Yang
2020-03-26 10:59 ` [PATCH 2/2] MIPS: Loongson64: Set cluster for cores Jiaxun Yang
@ 2020-03-27 1:47 ` Jiaxun Yang
2020-03-27 1:47 ` [PATCH 2/2] MIPS: Loongson64: Set cluster for cores Jiaxun Yang
1 sibling, 1 reply; 8+ messages in thread
From: Jiaxun Yang @ 2020-03-27 1:47 UTC (permalink / raw)
To: linux-mips; +Cc: tsbogend, chenhc, Jiaxun Yang
Victim Cache is defined by Loongson as per-core unified
private Cache.
Add this into cacheinfo and make cache levels selfincrement
instead of hardcode levels.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/kernel/cacheinfo.c | 34 ++++++++++++++++++++++++++--------
1 file changed, 26 insertions(+), 8 deletions(-)
diff --git a/arch/mips/kernel/cacheinfo.c b/arch/mips/kernel/cacheinfo.c
index 47312c529410..83548331ee94 100644
--- a/arch/mips/kernel/cacheinfo.c
+++ b/arch/mips/kernel/cacheinfo.c
@@ -35,6 +35,11 @@ static int __init_cache_level(unsigned int cpu)
leaves += (c->icache.waysize) ? 2 : 1;
+ if (c->vcache.waysize) {
+ levels++;
+ leaves++;
+ }
+
if (c->scache.waysize) {
levels++;
leaves++;
@@ -74,25 +79,38 @@ static int __populate_cache_leaves(unsigned int cpu)
struct cpuinfo_mips *c = ¤t_cpu_data;
struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
struct cacheinfo *this_leaf = this_cpu_ci->info_list;
+ int level = 1;
if (c->icache.waysize) {
- /* L1 caches are per core */
+ /* D/I caches are per core */
fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map);
- populate_cache(dcache, this_leaf, 1, CACHE_TYPE_DATA);
+ populate_cache(dcache, this_leaf, level, CACHE_TYPE_DATA);
fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map);
- populate_cache(icache, this_leaf, 1, CACHE_TYPE_INST);
+ populate_cache(icache, this_leaf, level, CACHE_TYPE_INST);
+ level++;
} else {
- populate_cache(dcache, this_leaf, 1, CACHE_TYPE_UNIFIED);
+ populate_cache(dcache, this_leaf, level, CACHE_TYPE_UNIFIED);
+ level++;
+ }
+
+ if (c->vcache.waysize) {
+ /* Vcache is per core as well */
+ fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map);
+ populate_cache(vcache, this_leaf, level, CACHE_TYPE_UNIFIED);
+ level++;
}
if (c->scache.waysize) {
- /* L2 cache is per cluster */
+ /* Scache is per cluster */
fill_cpumask_cluster(cpu, &this_leaf->shared_cpu_map);
- populate_cache(scache, this_leaf, 2, CACHE_TYPE_UNIFIED);
+ populate_cache(scache, this_leaf, level, CACHE_TYPE_UNIFIED);
+ level++;
}
- if (c->tcache.waysize)
- populate_cache(tcache, this_leaf, 3, CACHE_TYPE_UNIFIED);
+ if (c->tcache.waysize) {
+ populate_cache(tcache, this_leaf, level, CACHE_TYPE_UNIFIED);
+ level++;
+ }
this_cpu_ci->cpu_map_populated = true;
--
2.26.0.rc2
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 2/2] MIPS: Loongson64: Set cluster for cores
2020-03-27 1:47 ` [PATCH 1/2] MIPS: cacheinfo: Add missing VCache Jiaxun Yang
@ 2020-03-27 1:47 ` Jiaxun Yang
0 siblings, 0 replies; 8+ messages in thread
From: Jiaxun Yang @ 2020-03-27 1:47 UTC (permalink / raw)
To: linux-mips; +Cc: tsbogend, chenhc, Jiaxun Yang
cluster is required for cacheinfo to set shared_cpu_map correctly.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
v2: cpu_data should be indexed by logical id
---
arch/mips/loongson64/smp.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c
index e1fe8bbb377d..257cbb3d2656 100644
--- a/arch/mips/loongson64/smp.c
+++ b/arch/mips/loongson64/smp.c
@@ -404,6 +404,8 @@ static void __init loongson3_smp_setup(void)
__cpu_number_map[i] = num;
__cpu_logical_map[num] = i;
set_cpu_possible(num, true);
+ /* Loongson processors are always grouped by 4 */
+ cpu_set_cluster(&cpu_data[i], i / 4);
num++;
}
i++;
--
2.26.0.rc2
^ permalink raw reply related [flat|nested] 8+ messages in thread
end of thread, other threads:[~2021-01-04 10:49 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-12-30 3:39 [PATCH RESEND 1/2] MIPS: cacheinfo: Add missing VCache Jiaxun Yang
2020-12-30 3:39 ` [PATCH 2/2] MIPS: Loongson64: Set cluster for cores Jiaxun Yang
2020-12-31 0:27 ` Huacai Chen
2021-01-04 10:42 ` Thomas Bogendoerfer
2020-12-31 0:25 ` [PATCH RESEND 1/2] MIPS: cacheinfo: Add missing VCache Huacai Chen
2021-01-04 10:42 ` Thomas Bogendoerfer
-- strict thread matches above, loose matches on Subject: below --
2020-03-26 10:59 [PATCH " Jiaxun Yang
2020-03-26 10:59 ` [PATCH 2/2] MIPS: Loongson64: Set cluster for cores Jiaxun Yang
2020-03-27 1:47 ` [PATCH 1/2] MIPS: cacheinfo: Add missing VCache Jiaxun Yang
2020-03-27 1:47 ` [PATCH 2/2] MIPS: Loongson64: Set cluster for cores Jiaxun Yang
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