* [Intel-gfx] [PATCH] drm/i915/gt: Limit VFE threads based on GT
@ 2020-10-16 17:54 ` Chris Wilson
0 siblings, 0 replies; 10+ messages in thread
From: Chris Wilson @ 2020-10-16 17:54 UTC (permalink / raw)
To: intel-gfx; +Cc: stable, Chris Wilson
MEDIA_STATE_VFE only accepts the 'maximum number of threads' in the
range [0, n-1] where n is #EU * (#threads/EU) with the number of threads
based on plaform and the number of EU based on the number of slices and
subslices. This is a fixed number per platform/gt, so appropriately
limit the number of threads we spawn to match the device.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2024
Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
Cc: Balestrieri Francesco <francesco.balestrieri@intel.com>
Cc: Bloomfield Jon <jon.bloomfield@intel.com>
Cc: <stable@vger.kernel.org> # v5.7+
---
drivers/gpu/drm/i915/gt/gen7_renderclear.c | 35 +++++++++++++++-------
1 file changed, 24 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
index d93d85cd3027..f3b8fea6226e 100644
--- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
+++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
@@ -7,8 +7,6 @@
#include "i915_drv.h"
#include "intel_gpu_commands.h"
-#define MAX_URB_ENTRIES 64
-#define STATE_SIZE (4 * 1024)
#define GT3_INLINE_DATA_DELAYS 0x1E00
#define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS))
@@ -34,8 +32,7 @@ struct batch_chunk {
};
struct batch_vals {
- u32 max_primitives;
- u32 max_urb_entries;
+ u32 max_primitives; /* == number of VFE threads */
u32 cmd_size;
u32 state_size;
u32 state_start;
@@ -50,18 +47,35 @@ static void
batch_get_defaults(struct drm_i915_private *i915, struct batch_vals *bv)
{
if (IS_HASWELL(i915)) {
- bv->max_primitives = 280;
- bv->max_urb_entries = MAX_URB_ENTRIES;
+ switch (INTEL_INFO(i915)->gt) {
+ default:
+ case 1:
+ bv->max_primitives = 70;
+ break;
+ case 2:
+ bv->max_primitives = 140;
+ break;
+ case 3:
+ bv->max_primitives = 280;
+ break;
+ }
bv->surface_height = 16 * 16;
bv->surface_width = 32 * 2 * 16;
} else {
- bv->max_primitives = 128;
- bv->max_urb_entries = MAX_URB_ENTRIES / 2;
+ switch (INTEL_INFO(i915)->gt) {
+ default:
+ case 1: /* including vlv */
+ bv->max_primitives = 36;
+ break;
+ case 2:
+ bv->max_primitives = 128;
+ break;
+ }
bv->surface_height = 16 * 8;
bv->surface_width = 32 * 16;
}
bv->cmd_size = bv->max_primitives * 4096;
- bv->state_size = STATE_SIZE;
+ bv->state_size = SZ_4K;
bv->state_start = bv->cmd_size;
bv->batch_size = bv->cmd_size + bv->state_size;
bv->scratch_size = bv->surface_height * bv->surface_width;
@@ -244,7 +258,6 @@ gen7_emit_vfe_state(struct batch_chunk *batch,
u32 urb_size, u32 curbe_size,
u32 mode)
{
- u32 urb_entries = bv->max_urb_entries;
u32 threads = bv->max_primitives - 1;
u32 *cs = batch_alloc_items(batch, 32, 8);
@@ -254,7 +267,7 @@ gen7_emit_vfe_state(struct batch_chunk *batch,
*cs++ = 0;
/* number of threads & urb entries for GPGPU vs Media Mode */
- *cs++ = threads << 16 | urb_entries << 8 | mode << 2;
+ *cs++ = threads << 16 | 1 << 8 | mode << 2;
*cs++ = 0;
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH] drm/i915/gt: Limit VFE threads based on GT
@ 2020-10-16 17:54 ` Chris Wilson
0 siblings, 0 replies; 10+ messages in thread
From: Chris Wilson @ 2020-10-16 17:54 UTC (permalink / raw)
To: intel-gfx
Cc: Chris Wilson, Mika Kuoppala, Prathap Kumar Valsan,
Akeem G Abodunrin, Balestrieri Francesco, Bloomfield Jon, stable
MEDIA_STATE_VFE only accepts the 'maximum number of threads' in the
range [0, n-1] where n is #EU * (#threads/EU) with the number of threads
based on plaform and the number of EU based on the number of slices and
subslices. This is a fixed number per platform/gt, so appropriately
limit the number of threads we spawn to match the device.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2024
Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
Cc: Balestrieri Francesco <francesco.balestrieri@intel.com>
Cc: Bloomfield Jon <jon.bloomfield@intel.com>
Cc: <stable@vger.kernel.org> # v5.7+
---
drivers/gpu/drm/i915/gt/gen7_renderclear.c | 35 +++++++++++++++-------
1 file changed, 24 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
index d93d85cd3027..f3b8fea6226e 100644
--- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
+++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
@@ -7,8 +7,6 @@
#include "i915_drv.h"
#include "intel_gpu_commands.h"
-#define MAX_URB_ENTRIES 64
-#define STATE_SIZE (4 * 1024)
#define GT3_INLINE_DATA_DELAYS 0x1E00
#define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS))
@@ -34,8 +32,7 @@ struct batch_chunk {
};
struct batch_vals {
- u32 max_primitives;
- u32 max_urb_entries;
+ u32 max_primitives; /* == number of VFE threads */
u32 cmd_size;
u32 state_size;
u32 state_start;
@@ -50,18 +47,35 @@ static void
batch_get_defaults(struct drm_i915_private *i915, struct batch_vals *bv)
{
if (IS_HASWELL(i915)) {
- bv->max_primitives = 280;
- bv->max_urb_entries = MAX_URB_ENTRIES;
+ switch (INTEL_INFO(i915)->gt) {
+ default:
+ case 1:
+ bv->max_primitives = 70;
+ break;
+ case 2:
+ bv->max_primitives = 140;
+ break;
+ case 3:
+ bv->max_primitives = 280;
+ break;
+ }
bv->surface_height = 16 * 16;
bv->surface_width = 32 * 2 * 16;
} else {
- bv->max_primitives = 128;
- bv->max_urb_entries = MAX_URB_ENTRIES / 2;
+ switch (INTEL_INFO(i915)->gt) {
+ default:
+ case 1: /* including vlv */
+ bv->max_primitives = 36;
+ break;
+ case 2:
+ bv->max_primitives = 128;
+ break;
+ }
bv->surface_height = 16 * 8;
bv->surface_width = 32 * 16;
}
bv->cmd_size = bv->max_primitives * 4096;
- bv->state_size = STATE_SIZE;
+ bv->state_size = SZ_4K;
bv->state_start = bv->cmd_size;
bv->batch_size = bv->cmd_size + bv->state_size;
bv->scratch_size = bv->surface_height * bv->surface_width;
@@ -244,7 +258,6 @@ gen7_emit_vfe_state(struct batch_chunk *batch,
u32 urb_size, u32 curbe_size,
u32 mode)
{
- u32 urb_entries = bv->max_urb_entries;
u32 threads = bv->max_primitives - 1;
u32 *cs = batch_alloc_items(batch, 32, 8);
@@ -254,7 +267,7 @@ gen7_emit_vfe_state(struct batch_chunk *batch,
*cs++ = 0;
/* number of threads & urb entries for GPGPU vs Media Mode */
- *cs++ = threads << 16 | urb_entries << 8 | mode << 2;
+ *cs++ = threads << 16 | 1 << 8 | mode << 2;
*cs++ = 0;
--
2.20.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Limit VFE threads based on GT
2020-10-16 17:54 ` Chris Wilson
(?)
@ 2020-10-16 18:26 ` Patchwork
-1 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2020-10-16 18:26 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 6625 bytes --]
== Series Details ==
Series: drm/i915/gt: Limit VFE threads based on GT
URL : https://patchwork.freedesktop.org/series/82783/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9151 -> Patchwork_18720
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18720:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gt_lrc:
- {fi-tgl-dsi}: [DMESG-FAIL][1] ([i915#2373]) -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/fi-tgl-dsi/igt@i915_selftest@live@gt_lrc.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/fi-tgl-dsi/igt@i915_selftest@live@gt_lrc.html
Known issues
------------
Here are the changes found in Patchwork_18720 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_flink_basic@flink-lifetime:
- fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/fi-tgl-y/igt@gem_flink_basic@flink-lifetime.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/fi-tgl-y/igt@gem_flink_basic@flink-lifetime.html
* igt@i915_module_load@reload:
- fi-kbl-soraka: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/fi-kbl-soraka/igt@i915_module_load@reload.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/fi-kbl-soraka/igt@i915_module_load@reload.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7500u: [PASS][7] -> [DMESG-WARN][8] ([i915#2203])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [PASS][9] -> [FAIL][10] ([i915#1161] / [i915#262])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
- fi-icl-u2: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +2 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
#### Possible fixes ####
* igt@gem_flink_basic@double-flink:
- fi-tgl-y: [DMESG-WARN][13] ([i915#402]) -> [PASS][14] +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/fi-tgl-y/igt@gem_flink_basic@double-flink.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/fi-tgl-y/igt@gem_flink_basic@double-flink.html
* igt@i915_module_load@reload:
- fi-byt-j1900: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/fi-byt-j1900/igt@i915_module_load@reload.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/fi-byt-j1900/igt@i915_module_load@reload.html
* igt@i915_selftest@live@coherency:
- fi-gdg-551: [DMESG-FAIL][17] ([i915#1748]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/fi-gdg-551/igt@i915_selftest@live@coherency.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/fi-gdg-551/igt@i915_selftest@live@coherency.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-tgl-u2: [INCOMPLETE][19] ([i915#2557]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/fi-tgl-u2/igt@i915_selftest@live@gt_heartbeat.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/fi-tgl-u2/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- fi-icl-u2: [DMESG-WARN][21] ([i915#1982]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
* igt@kms_flip@basic-flip-vs-dpms@d-edp1:
- fi-tgl-y: [DMESG-WARN][23] ([i915#1982]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/fi-tgl-y/igt@kms_flip@basic-flip-vs-dpms@d-edp1.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/fi-tgl-y/igt@kms_flip@basic-flip-vs-dpms@d-edp1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161
[i915#1748]: https://gitlab.freedesktop.org/drm/intel/issues/1748
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
[i915#2373]: https://gitlab.freedesktop.org/drm/intel/issues/2373
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2557]: https://gitlab.freedesktop.org/drm/intel/issues/2557
[i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (48 -> 41)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9151 -> Patchwork_18720
CI-20190529: 20190529
CI_DRM_9151: 2e462bc73c344c5579c503f403adac6ee574eab6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5821: 2bf22b1cff7905f7e214c0707941929a09450257 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18720: d653a7f6fa1abad9a56cea2159f3f53458abe179 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d653a7f6fa1a drm/i915/gt: Limit VFE threads based on GT
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/index.html
[-- Attachment #1.2: Type: text/html, Size: 7800 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gt: Limit VFE threads based on GT
2020-10-16 17:54 ` Chris Wilson
(?)
(?)
@ 2020-10-16 21:47 ` Patchwork
-1 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2020-10-16 21:47 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 14895 bytes --]
== Series Details ==
Series: drm/i915/gt: Limit VFE threads based on GT
URL : https://patchwork.freedesktop.org/series/82783/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9151_full -> Patchwork_18720_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_18720_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18720_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18720_full:
### IGT changes ###
#### Possible regressions ####
* igt@prime_mmap_coherency@ioctl-errors:
- shard-snb: NOTRUN -> [FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/shard-snb4/igt@prime_mmap_coherency@ioctl-errors.html
* igt@runner@aborted:
- shard-skl: NOTRUN -> [FAIL][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/shard-skl10/igt@runner@aborted.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_async_flips@async-flip-with-page-flip-events}:
- shard-skl: NOTRUN -> [DMESG-FAIL][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/shard-skl10/igt@kms_async_flips@async-flip-with-page-flip-events.html
Known issues
------------
Here are the changes found in Patchwork_18720_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_create@forked:
- shard-glk: [PASS][4] -> [DMESG-WARN][5] ([i915#118] / [i915#95])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/shard-glk8/igt@gem_exec_create@forked.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/shard-glk7/igt@gem_exec_create@forked.html
* igt@gem_exec_whisper@basic-queues-all:
- shard-skl: [PASS][6] -> [FAIL][7] ([i915#1888])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/shard-skl7/igt@gem_exec_whisper@basic-queues-all.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/shard-skl1/igt@gem_exec_whisper@basic-queues-all.html
* igt@gem_exec_whisper@basic-queues-forked-all:
- shard-skl: [PASS][8] -> [DMESG-WARN][9] ([i915#1982]) +10 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/shard-skl4/igt@gem_exec_whisper@basic-queues-forked-all.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/shard-skl7/igt@gem_exec_whisper@basic-queues-forked-all.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-skl: [PASS][10] -> [TIMEOUT][11] ([i915#2424])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/shard-skl2/igt@gem_userptr_blits@unsync-unmap-cycles.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/shard-skl4/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1:
- shard-skl: [PASS][12] -> [FAIL][13] ([i915#2122])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/shard-skl3/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/shard-skl8/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu:
- shard-tglb: [PASS][14] -> [DMESG-WARN][15] ([i915#1982])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/shard-tglb6/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/shard-tglb7/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][16] -> [FAIL][17] ([i915#1188])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/shard-skl9/igt@kms_hdr@bpc-switch-dpms.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/shard-skl5/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_properties@connector-properties-legacy:
- shard-kbl: [PASS][18] -> [DMESG-WARN][19] ([i915#165] / [i915#78])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/shard-kbl3/igt@kms_properties@connector-properties-legacy.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/shard-kbl2/igt@kms_properties@connector-properties-legacy.html
* igt@kms_psr@psr2_sprite_blt:
- shard-iclb: [PASS][20] -> [SKIP][21] ([fdo#109441]) +1 similar issue
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/shard-iclb6/igt@kms_psr@psr2_sprite_blt.html
* igt@kms_vblank@pipe-c-wait-idle:
- shard-kbl: [PASS][22] -> [DMESG-WARN][23] ([i915#1982])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/shard-kbl6/igt@kms_vblank@pipe-c-wait-idle.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/shard-kbl6/igt@kms_vblank@pipe-c-wait-idle.html
#### Possible fixes ####
* igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-skl: [INCOMPLETE][24] ([i915#198]) -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/shard-skl1/igt@gem_ctx_isolation@preservation-s3@rcs0.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/shard-skl10/igt@gem_ctx_isolation@preservation-s3@rcs0.html
* igt@gem_eio@in-flight-contexts-10ms:
- shard-snb: [INCOMPLETE][26] ([i915#82]) -> [PASS][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/shard-snb6/igt@gem_eio@in-flight-contexts-10ms.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/shard-snb4/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_exec_reloc@basic-many-active@vecs0:
- shard-glk: [FAIL][28] ([i915#2389]) -> [PASS][29]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/shard-glk8/igt@gem_exec_reloc@basic-many-active@vecs0.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/shard-glk8/igt@gem_exec_reloc@basic-many-active@vecs0.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [SKIP][30] ([i915#2190]) -> [PASS][31]
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/shard-tglb6/igt@gem_huc_copy@huc-copy.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/shard-tglb1/igt@gem_huc_copy@huc-copy.html
* igt@gem_partial_pwrite_pread@reads-display:
- shard-hsw: [FAIL][32] ([i915#1888] / [i915#2261]) -> [PASS][33]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/shard-hsw1/igt@gem_partial_pwrite_pread@reads-display.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/shard-hsw8/igt@gem_partial_pwrite_pread@reads-display.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy-gup@gtt:
- shard-hsw: [FAIL][34] ([i915#1888]) -> [PASS][35] +1 similar issue
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/shard-hsw4/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup@gtt.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/shard-hsw4/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup@gtt.html
* igt@i915_pm_rpm@fences-dpms:
- shard-glk: [DMESG-WARN][36] ([i915#1982]) -> [PASS][37]
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/shard-glk7/igt@i915_pm_rpm@fences-dpms.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/shard-glk1/igt@i915_pm_rpm@fences-dpms.html
* {igt@kms_async_flips@async-flip-with-page-flip-events}:
- shard-glk: [FAIL][38] ([i915#2521]) -> [PASS][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/shard-glk3/igt@kms_async_flips@async-flip-with-page-flip-events.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/shard-glk1/igt@kms_async_flips@async-flip-with-page-flip-events.html
* igt@kms_cursor_edge_walk@pipe-c-256x256-bottom-edge:
- shard-skl: [DMESG-WARN][40] ([i915#1982]) -> [PASS][41] +3 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/shard-skl5/igt@kms_cursor_edge_walk@pipe-c-256x256-bottom-edge.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/shard-skl2/igt@kms_cursor_edge_walk@pipe-c-256x256-bottom-edge.html
* igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1:
- shard-glk: [FAIL][42] ([i915#79]) -> [PASS][43] +1 similar issue
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/shard-glk9/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/shard-glk9/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1.html
* igt@kms_flip@flip-vs-suspend@c-hdmi-a1:
- shard-hsw: [INCOMPLETE][44] ([i915#2055]) -> [PASS][45]
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/shard-hsw2/igt@kms_flip@flip-vs-suspend@c-hdmi-a1.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/shard-hsw6/igt@kms_flip@flip-vs-suspend@c-hdmi-a1.html
* igt@kms_flip@plain-flip-fb-recreate@b-edp1:
- shard-skl: [FAIL][46] ([i915#2122]) -> [PASS][47]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/shard-skl8/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/shard-skl9/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
- shard-snb: [FAIL][48] ([i915#2546]) -> [PASS][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/shard-snb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/shard-snb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-render:
- shard-tglb: [DMESG-WARN][50] ([i915#1982]) -> [PASS][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-render.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/shard-tglb8/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-render.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [FAIL][52] ([i915#1188]) -> [PASS][53]
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/shard-skl7/igt@kms_hdr@bpc-switch-suspend.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/shard-skl1/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_plane_cursor@pipe-b-viewport-size-64:
- shard-hsw: [INCOMPLETE][54] -> [PASS][55]
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/shard-hsw8/igt@kms_plane_cursor@pipe-b-viewport-size-64.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/shard-hsw7/igt@kms_plane_cursor@pipe-b-viewport-size-64.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [SKIP][56] ([fdo#109441]) -> [PASS][57]
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/shard-iclb5/igt@kms_psr@psr2_sprite_plane_move.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
* igt@syncobj_timeline@wait-for-submit-complex:
- shard-hsw: [DMESG-WARN][58] ([i915#1982]) -> [PASS][59]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/shard-hsw6/igt@syncobj_timeline@wait-for-submit-complex.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/shard-hsw7/igt@syncobj_timeline@wait-for-submit-complex.html
#### Warnings ####
* igt@runner@aborted:
- shard-glk: ([FAIL][60], [FAIL][61]) ([i915#1611] / [i915#1814] / [k.org#202321]) -> [FAIL][62] ([k.org#202321])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/shard-glk8/igt@runner@aborted.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9151/shard-glk2/igt@runner@aborted.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/shard-glk4/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1611]: https://gitlab.freedesktop.org/drm/intel/issues/1611
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2055]: https://gitlab.freedesktop.org/drm/intel/issues/2055
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2261]: https://gitlab.freedesktop.org/drm/intel/issues/2261
[i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
[i915#2424]: https://gitlab.freedesktop.org/drm/intel/issues/2424
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
[i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (12 -> 11)
------------------------------
Missing (1): pig-snb-2600
Build changes
-------------
* Linux: CI_DRM_9151 -> Patchwork_18720
CI-20190529: 20190529
CI_DRM_9151: 2e462bc73c344c5579c503f403adac6ee574eab6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5821: 2bf22b1cff7905f7e214c0707941929a09450257 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18720: d653a7f6fa1abad9a56cea2159f3f53458abe179 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18720/index.html
[-- Attachment #1.2: Type: text/html, Size: 17058 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/gt: Limit VFE threads based on GT
2020-10-16 17:54 ` Chris Wilson
@ 2020-11-10 0:32 ` rwright
-1 siblings, 0 replies; 10+ messages in thread
From: rwright @ 2020-11-10 0:32 UTC (permalink / raw)
To: chris; +Cc: intel-gfx, stable
On Fri, Oct 16, 2020 at 06:54:11PM +0100, Chris Wilson wrote:
> MEDIA_STATE_VFE only accepts the 'maximum number of threads' in the
> range [0, n-1] where n is #EU * (#threads/EU) with the number of threads
> based on plaform and the number of EU based on the number of slices and
> subslices. This is a fixed number per platform/gt, so appropriately
> limit the number of threads we spawn to match the device.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2024
> Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com>
> Cc: Prathap Kumar Valsan <prathap.kumar.valsan at intel.com>
> Cc: Akeem G Abodunrin <akeem.g.abodunrin at intel.com>
> Cc: Balestrieri Francesco <francesco.balestrieri at intel.com>
> Cc: Bloomfield Jon <jon.bloomfield at intel.com>
> Cc: <stable at vger.kernel.org> # v5.7+
> ---
> ...
I tested this patch and found that it prevents the GPU hang I had
reported on the HP Pavilion Mini 300-020 in
https://gitlab.freedesktop.org/drm/intel/-/issues/2413.
In more detail: I built linux-next at tag next-20201106 without
the patch, and booted the result on an Ubuntu 20.04 base system. As
expected, I observed the hang that I had previously reported as soon as
Cinnnamon started when I entered graphical.target.
I then applied this patch - that being the only change to my kernel -
and I was able to boot to graphical.target 5 times consecutively without
any GPU hang.
You may add my endorsements:
Tested-by: Randy Wright <rwright@hpe.com>
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2413
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2106
--
Randy Wright Hewlett Packard Enterprise
Phone: (970) 898-0998 Mail: rwright@hpe.com
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/gt: Limit VFE threads based on GT
@ 2020-11-10 0:32 ` rwright
0 siblings, 0 replies; 10+ messages in thread
From: rwright @ 2020-11-10 0:32 UTC (permalink / raw)
To: chris
Cc: mika.kuoppala, prathap.kumar.valsan, akeem.g.abodunrin,
francesco.balestrieri, jon.bloomfield, stable, intel-gfx
On Fri, Oct 16, 2020 at 06:54:11PM +0100, Chris Wilson wrote:
> MEDIA_STATE_VFE only accepts the 'maximum number of threads' in the
> range [0, n-1] where n is #EU * (#threads/EU) with the number of threads
> based on plaform and the number of EU based on the number of slices and
> subslices. This is a fixed number per platform/gt, so appropriately
> limit the number of threads we spawn to match the device.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2024
> Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com>
> Cc: Prathap Kumar Valsan <prathap.kumar.valsan at intel.com>
> Cc: Akeem G Abodunrin <akeem.g.abodunrin at intel.com>
> Cc: Balestrieri Francesco <francesco.balestrieri at intel.com>
> Cc: Bloomfield Jon <jon.bloomfield at intel.com>
> Cc: <stable at vger.kernel.org> # v5.7+
> ---
> ...
I tested this patch and found that it prevents the GPU hang I had
reported on the HP Pavilion Mini 300-020 in
https://gitlab.freedesktop.org/drm/intel/-/issues/2413.
In more detail: I built linux-next at tag next-20201106 without
the patch, and booted the result on an Ubuntu 20.04 base system. As
expected, I observed the hang that I had previously reported as soon as
Cinnnamon started when I entered graphical.target.
I then applied this patch - that being the only change to my kernel -
and I was able to boot to graphical.target 5 times consecutively without
any GPU hang.
You may add my endorsements:
Tested-by: Randy Wright <rwright@hpe.com>
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2413
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2106
--
Randy Wright Hewlett Packard Enterprise
Phone: (970) 898-0998 Mail: rwright@hpe.com
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/gt: Limit VFE threads based on GT
2020-10-16 17:54 ` Chris Wilson
@ 2021-01-07 19:50 ` Rodrigo Vivi
-1 siblings, 0 replies; 10+ messages in thread
From: Rodrigo Vivi @ 2021-01-07 19:50 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx, stable
On Fri, Oct 16, 2020 at 06:54:11PM +0100, Chris Wilson wrote:
> MEDIA_STATE_VFE only accepts the 'maximum number of threads' in the
> range [0, n-1] where n is #EU * (#threads/EU) with the number of threads
> based on plaform and the number of EU based on the number of slices and
> subslices. This is a fixed number per platform/gt, so appropriately
> limit the number of threads we spawn to match the device.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2024
we need to get this closed...
> Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> Cc: Balestrieri Francesco <francesco.balestrieri@intel.com>
> Cc: Bloomfield Jon <jon.bloomfield@intel.com>
> Cc: <stable@vger.kernel.org> # v5.7+
> ---
> drivers/gpu/drm/i915/gt/gen7_renderclear.c | 35 +++++++++++++++-------
> 1 file changed, 24 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> index d93d85cd3027..f3b8fea6226e 100644
> --- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> +++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> @@ -7,8 +7,6 @@
> #include "i915_drv.h"
> #include "intel_gpu_commands.h"
>
> -#define MAX_URB_ENTRIES 64
> -#define STATE_SIZE (4 * 1024)
> #define GT3_INLINE_DATA_DELAYS 0x1E00
> #define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS))
>
> @@ -34,8 +32,7 @@ struct batch_chunk {
> };
>
> struct batch_vals {
> - u32 max_primitives;
> - u32 max_urb_entries;
> + u32 max_primitives; /* == number of VFE threads */
> u32 cmd_size;
> u32 state_size;
> u32 state_start;
> @@ -50,18 +47,35 @@ static void
> batch_get_defaults(struct drm_i915_private *i915, struct batch_vals *bv)
> {
> if (IS_HASWELL(i915)) {
> - bv->max_primitives = 280;
> - bv->max_urb_entries = MAX_URB_ENTRIES;
> + switch (INTEL_INFO(i915)->gt) {
> + default:
> + case 1:
> + bv->max_primitives = 70;
> + break;
> + case 2:
> + bv->max_primitives = 140;
> + break;
> + case 3:
> + bv->max_primitives = 280;
> + break;
> + }
> bv->surface_height = 16 * 16;
> bv->surface_width = 32 * 2 * 16;
> } else {
> - bv->max_primitives = 128;
> - bv->max_urb_entries = MAX_URB_ENTRIES / 2;
> + switch (INTEL_INFO(i915)->gt) {
> + default:
> + case 1: /* including vlv */
> + bv->max_primitives = 36;
> + break;
> + case 2:
> + bv->max_primitives = 128;
> + break;
> + }
> bv->surface_height = 16 * 8;
> bv->surface_width = 32 * 16;
> }
> bv->cmd_size = bv->max_primitives * 4096;
> - bv->state_size = STATE_SIZE;
> + bv->state_size = SZ_4K;
> bv->state_start = bv->cmd_size;
> bv->batch_size = bv->cmd_size + bv->state_size;
> bv->scratch_size = bv->surface_height * bv->surface_width;
> @@ -244,7 +258,6 @@ gen7_emit_vfe_state(struct batch_chunk *batch,
> u32 urb_size, u32 curbe_size,
> u32 mode)
> {
> - u32 urb_entries = bv->max_urb_entries;
> u32 threads = bv->max_primitives - 1;
> u32 *cs = batch_alloc_items(batch, 32, 8);
>
> @@ -254,7 +267,7 @@ gen7_emit_vfe_state(struct batch_chunk *batch,
> *cs++ = 0;
>
> /* number of threads & urb entries for GPGPU vs Media Mode */
> - *cs++ = threads << 16 | urb_entries << 8 | mode << 2;
> + *cs++ = threads << 16 | 1 << 8 | mode << 2;
why urb_entries = 1 ?
the range is 0,64 and 0,128 depending on the sku.
in general there's a min of 32 URBs
>
> *cs++ = 0;
>
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/gt: Limit VFE threads based on GT
@ 2021-01-07 19:50 ` Rodrigo Vivi
0 siblings, 0 replies; 10+ messages in thread
From: Rodrigo Vivi @ 2021-01-07 19:50 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx, stable
On Fri, Oct 16, 2020 at 06:54:11PM +0100, Chris Wilson wrote:
> MEDIA_STATE_VFE only accepts the 'maximum number of threads' in the
> range [0, n-1] where n is #EU * (#threads/EU) with the number of threads
> based on plaform and the number of EU based on the number of slices and
> subslices. This is a fixed number per platform/gt, so appropriately
> limit the number of threads we spawn to match the device.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2024
we need to get this closed...
> Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> Cc: Balestrieri Francesco <francesco.balestrieri@intel.com>
> Cc: Bloomfield Jon <jon.bloomfield@intel.com>
> Cc: <stable@vger.kernel.org> # v5.7+
> ---
> drivers/gpu/drm/i915/gt/gen7_renderclear.c | 35 +++++++++++++++-------
> 1 file changed, 24 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> index d93d85cd3027..f3b8fea6226e 100644
> --- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> +++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> @@ -7,8 +7,6 @@
> #include "i915_drv.h"
> #include "intel_gpu_commands.h"
>
> -#define MAX_URB_ENTRIES 64
> -#define STATE_SIZE (4 * 1024)
> #define GT3_INLINE_DATA_DELAYS 0x1E00
> #define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS))
>
> @@ -34,8 +32,7 @@ struct batch_chunk {
> };
>
> struct batch_vals {
> - u32 max_primitives;
> - u32 max_urb_entries;
> + u32 max_primitives; /* == number of VFE threads */
> u32 cmd_size;
> u32 state_size;
> u32 state_start;
> @@ -50,18 +47,35 @@ static void
> batch_get_defaults(struct drm_i915_private *i915, struct batch_vals *bv)
> {
> if (IS_HASWELL(i915)) {
> - bv->max_primitives = 280;
> - bv->max_urb_entries = MAX_URB_ENTRIES;
> + switch (INTEL_INFO(i915)->gt) {
> + default:
> + case 1:
> + bv->max_primitives = 70;
> + break;
> + case 2:
> + bv->max_primitives = 140;
> + break;
> + case 3:
> + bv->max_primitives = 280;
> + break;
> + }
> bv->surface_height = 16 * 16;
> bv->surface_width = 32 * 2 * 16;
> } else {
> - bv->max_primitives = 128;
> - bv->max_urb_entries = MAX_URB_ENTRIES / 2;
> + switch (INTEL_INFO(i915)->gt) {
> + default:
> + case 1: /* including vlv */
> + bv->max_primitives = 36;
> + break;
> + case 2:
> + bv->max_primitives = 128;
> + break;
> + }
> bv->surface_height = 16 * 8;
> bv->surface_width = 32 * 16;
> }
> bv->cmd_size = bv->max_primitives * 4096;
> - bv->state_size = STATE_SIZE;
> + bv->state_size = SZ_4K;
> bv->state_start = bv->cmd_size;
> bv->batch_size = bv->cmd_size + bv->state_size;
> bv->scratch_size = bv->surface_height * bv->surface_width;
> @@ -244,7 +258,6 @@ gen7_emit_vfe_state(struct batch_chunk *batch,
> u32 urb_size, u32 curbe_size,
> u32 mode)
> {
> - u32 urb_entries = bv->max_urb_entries;
> u32 threads = bv->max_primitives - 1;
> u32 *cs = batch_alloc_items(batch, 32, 8);
>
> @@ -254,7 +267,7 @@ gen7_emit_vfe_state(struct batch_chunk *batch,
> *cs++ = 0;
>
> /* number of threads & urb entries for GPGPU vs Media Mode */
> - *cs++ = threads << 16 | urb_entries << 8 | mode << 2;
> + *cs++ = threads << 16 | 1 << 8 | mode << 2;
why urb_entries = 1 ?
the range is 0,64 and 0,128 depending on the sku.
in general there's a min of 32 URBs
>
> *cs++ = 0;
>
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/gt: Limit VFE threads based on GT
2021-01-07 19:50 ` Rodrigo Vivi
@ 2021-01-07 22:04 ` Chris Wilson
-1 siblings, 0 replies; 10+ messages in thread
From: Chris Wilson @ 2021-01-07 22:04 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx, stable
Quoting Rodrigo Vivi (2021-01-07 19:50:37)
> On Fri, Oct 16, 2020 at 06:54:11PM +0100, Chris Wilson wrote:
> > MEDIA_STATE_VFE only accepts the 'maximum number of threads' in the
> > range [0, n-1] where n is #EU * (#threads/EU) with the number of threads
> > based on plaform and the number of EU based on the number of slices and
> > subslices. This is a fixed number per platform/gt, so appropriately
> > limit the number of threads we spawn to match the device.
> >
> > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2024
>
> we need to get this closed...
Unfortunately this failed the validation test. And as that test is still
not in CI, I cannot say why. My vote would be to remove the
clear_residuals until it works on all target platforms. Plus we clearly
need a hsw-gt1 in CI.
> > bv->scratch_size = bv->surface_height * bv->surface_width;
> > @@ -244,7 +258,6 @@ gen7_emit_vfe_state(struct batch_chunk *batch,
> > u32 urb_size, u32 curbe_size,
> > u32 mode)
> > {
> > - u32 urb_entries = bv->max_urb_entries;
> > u32 threads = bv->max_primitives - 1;
> > u32 *cs = batch_alloc_items(batch, 32, 8);
> >
> > @@ -254,7 +267,7 @@ gen7_emit_vfe_state(struct batch_chunk *batch,
> > *cs++ = 0;
> >
> > /* number of threads & urb entries for GPGPU vs Media Mode */
> > - *cs++ = threads << 16 | urb_entries << 8 | mode << 2;
> > + *cs++ = threads << 16 | 1 << 8 | mode << 2;
>
> why urb_entries = 1 ?
We only used a single entry. There was no measurable benefit from
assigning more entries, and the importance of any side effects from doing
so unknown.
> the range is 0,64 and 0,128 depending on the sku.
>
> in general there's a min of 32 URBs
Don't forget num_entries * entry_size must fit within the URB
allocation/allotment.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/gt: Limit VFE threads based on GT
@ 2021-01-07 22:04 ` Chris Wilson
0 siblings, 0 replies; 10+ messages in thread
From: Chris Wilson @ 2021-01-07 22:04 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx, stable
Quoting Rodrigo Vivi (2021-01-07 19:50:37)
> On Fri, Oct 16, 2020 at 06:54:11PM +0100, Chris Wilson wrote:
> > MEDIA_STATE_VFE only accepts the 'maximum number of threads' in the
> > range [0, n-1] where n is #EU * (#threads/EU) with the number of threads
> > based on plaform and the number of EU based on the number of slices and
> > subslices. This is a fixed number per platform/gt, so appropriately
> > limit the number of threads we spawn to match the device.
> >
> > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2024
>
> we need to get this closed...
Unfortunately this failed the validation test. And as that test is still
not in CI, I cannot say why. My vote would be to remove the
clear_residuals until it works on all target platforms. Plus we clearly
need a hsw-gt1 in CI.
> > bv->scratch_size = bv->surface_height * bv->surface_width;
> > @@ -244,7 +258,6 @@ gen7_emit_vfe_state(struct batch_chunk *batch,
> > u32 urb_size, u32 curbe_size,
> > u32 mode)
> > {
> > - u32 urb_entries = bv->max_urb_entries;
> > u32 threads = bv->max_primitives - 1;
> > u32 *cs = batch_alloc_items(batch, 32, 8);
> >
> > @@ -254,7 +267,7 @@ gen7_emit_vfe_state(struct batch_chunk *batch,
> > *cs++ = 0;
> >
> > /* number of threads & urb entries for GPGPU vs Media Mode */
> > - *cs++ = threads << 16 | urb_entries << 8 | mode << 2;
> > + *cs++ = threads << 16 | 1 << 8 | mode << 2;
>
> why urb_entries = 1 ?
We only used a single entry. There was no measurable benefit from
assigning more entries, and the importance of any side effects from doing
so unknown.
> the range is 0,64 and 0,128 depending on the sku.
>
> in general there's a min of 32 URBs
Don't forget num_entries * entry_size must fit within the URB
allocation/allotment.
-Chris
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2021-01-07 22:05 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-10-16 17:54 [Intel-gfx] [PATCH] drm/i915/gt: Limit VFE threads based on GT Chris Wilson
2020-10-16 17:54 ` Chris Wilson
2020-10-16 18:26 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2020-10-16 21:47 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-11-10 0:32 ` [Intel-gfx] [PATCH] " rwright
2020-11-10 0:32 ` rwright
2021-01-07 19:50 ` Rodrigo Vivi
2021-01-07 19:50 ` Rodrigo Vivi
2021-01-07 22:04 ` Chris Wilson
2021-01-07 22:04 ` Chris Wilson
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