From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: anshuman.khandual@arm.com,
Catalin Marinas <catalin.marinas@arm.com>,
coresight@lists.linaro.org, linux-kernel@vger.kernel.org,
Jonathan Zhou <jonathan.zhouwen@huawei.com>,
leo.yan@linaro.org, Will Deacon <will@kernel.org>,
linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org
Subject: Re: [PATCH v6 25/26] arm64: Add TRFCR_ELx definitions
Date: Thu, 7 Jan 2021 18:01:48 -0700 [thread overview]
Message-ID: <20210108010148.GH43045@xps15> (raw)
In-Reply-To: <20210107123859.674252-26-suzuki.poulose@arm.com>
On Thu, Jan 07, 2021 at 12:38:58PM +0000, Suzuki K Poulose wrote:
> From: Jonathan Zhou <jonathan.zhouwen@huawei.com>
>
> Add definitions for the Arm v8.4 SelfHosted trace extensions registers.
>
> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Signed-off-by: Jonathan Zhou <jonathan.zhouwen@huawei.com>
> [ split the register definitions to separate patch
> rename some of the symbols ]
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Acked-by: Mathieu Poirier <mathieu.poirier@linaro.org>
> ---
> arch/arm64/include/asm/sysreg.h | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 8b5e7e5c3cc8..4acff97519b9 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -191,6 +191,7 @@
> #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
>
> #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0)
> +#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1)
>
> #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0)
> #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1)
> @@ -471,6 +472,7 @@
>
> #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0)
> #define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0)
> +#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1)
> #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0)
> #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
> #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
> @@ -829,6 +831,7 @@
> #define ID_AA64MMFR2_CNP_SHIFT 0
>
> /* id_aa64dfr0 */
> +#define ID_AA64DFR0_TRACE_FILT_SHIFT 40
> #define ID_AA64DFR0_DOUBLELOCK_SHIFT 36
> #define ID_AA64DFR0_PMSVER_SHIFT 32
> #define ID_AA64DFR0_CTX_CMPS_SHIFT 28
> @@ -1003,6 +1006,14 @@
> /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
> #define SYS_MPIDR_SAFE_VAL (BIT(31))
>
> +#define TRFCR_ELx_TS_SHIFT 5
> +#define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT)
> +#define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT)
> +#define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT)
> +#define TRFCR_EL2_CX BIT(3)
> +#define TRFCR_ELx_ExTRE BIT(1)
> +#define TRFCR_ELx_E0TRE BIT(0)
> +
> #ifdef __ASSEMBLY__
>
> .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
> --
> 2.24.1
>
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WARNING: multiple messages have this Message-ID (diff)
From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, coresight@lists.linaro.org,
leo.yan@linaro.org, mike.leach@linaro.org,
anshuman.khandual@arm.com,
Jonathan Zhou <jonathan.zhouwen@huawei.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>
Subject: Re: [PATCH v6 25/26] arm64: Add TRFCR_ELx definitions
Date: Thu, 7 Jan 2021 18:01:48 -0700 [thread overview]
Message-ID: <20210108010148.GH43045@xps15> (raw)
In-Reply-To: <20210107123859.674252-26-suzuki.poulose@arm.com>
On Thu, Jan 07, 2021 at 12:38:58PM +0000, Suzuki K Poulose wrote:
> From: Jonathan Zhou <jonathan.zhouwen@huawei.com>
>
> Add definitions for the Arm v8.4 SelfHosted trace extensions registers.
>
> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Signed-off-by: Jonathan Zhou <jonathan.zhouwen@huawei.com>
> [ split the register definitions to separate patch
> rename some of the symbols ]
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Acked-by: Mathieu Poirier <mathieu.poirier@linaro.org>
> ---
> arch/arm64/include/asm/sysreg.h | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 8b5e7e5c3cc8..4acff97519b9 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -191,6 +191,7 @@
> #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
>
> #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0)
> +#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1)
>
> #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0)
> #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1)
> @@ -471,6 +472,7 @@
>
> #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0)
> #define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0)
> +#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1)
> #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0)
> #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
> #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
> @@ -829,6 +831,7 @@
> #define ID_AA64MMFR2_CNP_SHIFT 0
>
> /* id_aa64dfr0 */
> +#define ID_AA64DFR0_TRACE_FILT_SHIFT 40
> #define ID_AA64DFR0_DOUBLELOCK_SHIFT 36
> #define ID_AA64DFR0_PMSVER_SHIFT 32
> #define ID_AA64DFR0_CTX_CMPS_SHIFT 28
> @@ -1003,6 +1006,14 @@
> /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
> #define SYS_MPIDR_SAFE_VAL (BIT(31))
>
> +#define TRFCR_ELx_TS_SHIFT 5
> +#define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT)
> +#define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT)
> +#define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT)
> +#define TRFCR_EL2_CX BIT(3)
> +#define TRFCR_ELx_ExTRE BIT(1)
> +#define TRFCR_ELx_E0TRE BIT(0)
> +
> #ifdef __ASSEMBLY__
>
> .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
> --
> 2.24.1
>
next prev parent reply other threads:[~2021-01-08 1:04 UTC|newest]
Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-07 12:38 [PATCH v6 00/26] coresight: etm4x: Support for system instructions Suzuki K Poulose
2021-01-07 12:38 ` Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 01/26] coresight: etm4x: Handle access to TRCSSPCICRn Suzuki K Poulose
2021-01-07 12:38 ` Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 02/26] coresight: etm4x: Skip accessing TRCPDCR in save/restore Suzuki K Poulose
2021-01-07 12:38 ` Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 03/26] coresight: Introduce device access abstraction Suzuki K Poulose
2021-01-07 12:38 ` Suzuki K Poulose
2021-01-07 23:38 ` Mathieu Poirier
2021-01-07 23:38 ` Mathieu Poirier
2021-01-07 12:38 ` [PATCH v6 04/26] coresight: tpiu: Prepare for using coresight " Suzuki K Poulose
2021-01-07 12:38 ` Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 05/26] coresight: Convert coresight_timeout to use " Suzuki K Poulose
2021-01-07 12:38 ` Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 06/26] coresight: Convert claim/disclaim operations to use access wrappers Suzuki K Poulose
2021-01-07 12:38 ` Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 07/26] coresight: etm4x: Always read the registers on the host CPU Suzuki K Poulose
2021-01-07 12:38 ` Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 08/26] coresight: etm4x: Convert all register accesses Suzuki K Poulose
2021-01-07 12:38 ` Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 09/26] coresight: etm4x: Add commentary on the registers Suzuki K Poulose
2021-01-07 12:38 ` Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 10/26] coresight: etm4x: Add sysreg access helpers Suzuki K Poulose
2021-01-07 12:38 ` Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 11/26] coresight: etm4x: Define DEVARCH register fields Suzuki K Poulose
2021-01-07 12:38 ` Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 12/26] coresight: etm4x: Check for Software Lock Suzuki K Poulose
2021-01-07 12:38 ` Suzuki K Poulose
2021-01-08 0:18 ` Mathieu Poirier
2021-01-08 0:18 ` Mathieu Poirier
2021-01-07 12:38 ` [PATCH v6 13/26] coresight: etm4x: Cleanup secure exception level masks Suzuki K Poulose
2021-01-07 12:38 ` Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 14/26] coresight: etm4x: Clean up " Suzuki K Poulose
2021-01-07 12:38 ` Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 15/26] coresight: etm4x: Handle ETM architecture version Suzuki K Poulose
2021-01-07 12:38 ` Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 16/26] coresight: etm4x: Detect access early on the target CPU Suzuki K Poulose
2021-01-07 12:38 ` Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 17/26] coresight: etm4x: Use TRCDEVARCH for component discovery Suzuki K Poulose
2021-01-07 12:38 ` Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 18/26] coresight: etm4x: Expose trcdevarch via sysfs Suzuki K Poulose
2021-01-07 12:38 ` Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 19/26] coresight: etm4x: Add necessary synchronization for sysreg access Suzuki K Poulose
2021-01-07 12:38 ` Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 20/26] coresight: etm4x: Detect system instructions support Suzuki K Poulose
2021-01-07 12:38 ` Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 21/26] coresight: etm4x: Refactor probing routine Suzuki K Poulose
2021-01-07 12:38 ` Suzuki K Poulose
2021-01-08 0:38 ` Mathieu Poirier
2021-01-08 0:38 ` Mathieu Poirier
2021-01-07 12:38 ` [PATCH v6 22/26] coresight: etm4x: Run arch feature detection on the CPU Suzuki K Poulose
2021-01-07 12:38 ` Suzuki K Poulose
2021-01-08 0:49 ` Mathieu Poirier
2021-01-08 0:49 ` Mathieu Poirier
2021-01-07 12:38 ` [PATCH v6 23/26] coresight: etm4x: Add support for sysreg only devices Suzuki K Poulose
2021-01-07 12:38 ` Suzuki K Poulose
2021-01-08 0:55 ` Mathieu Poirier
2021-01-08 0:55 ` Mathieu Poirier
2021-01-07 12:38 ` [PATCH v6 24/26] dts: bindings: coresight: ETM system register access only units Suzuki K Poulose
2021-01-07 12:38 ` Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 25/26] arm64: Add TRFCR_ELx definitions Suzuki K Poulose
2021-01-07 12:38 ` Suzuki K Poulose
2021-01-08 1:01 ` Mathieu Poirier [this message]
2021-01-08 1:01 ` Mathieu Poirier
2021-01-07 12:38 ` [PATCH v6 26/26] coresight: Add support for v8.4 SelfHosted tracing Suzuki K Poulose
2021-01-07 12:38 ` Suzuki K Poulose
2021-01-08 1:02 ` Mathieu Poirier
2021-01-08 1:02 ` Mathieu Poirier
2021-01-08 1:09 ` [PATCH v6 00/26] coresight: etm4x: Support for system instructions Mathieu Poirier
2021-01-08 1:09 ` Mathieu Poirier
2021-01-08 9:08 ` Suzuki K Poulose
2021-01-08 9:08 ` Suzuki K Poulose
2021-01-08 14:15 ` Suzuki K Poulose
2021-01-08 14:15 ` Suzuki K Poulose
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