* [PATCH] drm/amd/display: 64-bit division on 32-bit arch issue @ 2021-01-22 9:00 Lang Yu 2021-01-22 9:03 ` Huang Rui 0 siblings, 1 reply; 5+ messages in thread From: Lang Yu @ 2021-01-22 9:00 UTC (permalink / raw) To: amd-gfx; +Cc: Alex Deucher, Lang Yu, Huang Rui, Bhawanpreet Lakha Replace "/" with div_u64 for 32-bit arch. On 32-bit arch, the use of "/" for 64-bit division will cause build error, i.e. "__udivdi3/__divdi3 undefined!". Fixes: 27755cdf83f1 drm/amd/display: Update dcn30_apply_idle_power_optimizations() code Signed-off-by: Lang Yu <Lang.Yu@amd.com> --- drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c index dff83c6a142a..9620fb8a27dc 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c @@ -772,8 +772,8 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) cursor_cache_enable ? &cursor_attr : NULL)) { unsigned int v_total = stream->adjust.v_total_max ? stream->adjust.v_total_max : stream->timing.v_total; - unsigned int refresh_hz = (unsigned long long) stream->timing.pix_clk_100hz * - 100LL / (v_total * stream->timing.h_total); + unsigned int refresh_hz = div_u64((unsigned long long) stream->timing.pix_clk_100hz * + 100LL, (v_total * stream->timing.h_total)); /* * one frame time in microsec: @@ -800,8 +800,8 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) unsigned int denom = refresh_hz * 6528; unsigned int stutter_period = dc->current_state->perf_params.stutter_period_us; - tmr_delay = (((1000000LL + 2 * stutter_period * refresh_hz) * - (100LL + dc->debug.mall_additional_timer_percent) + denom - 1) / + tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) * + (100LL + dc->debug.mall_additional_timer_percent) + denom - 1), denom) - 64LL; /* scale should be increased until it fits into 6 bits */ @@ -815,8 +815,8 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) } denom *= 2; - tmr_delay = (((1000000LL + 2 * stutter_period * refresh_hz) * - (100LL + dc->debug.mall_additional_timer_percent) + denom - 1) / + tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) * + (100LL + dc->debug.mall_additional_timer_percent) + denom - 1), denom) - 64LL; } -- 2.25.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/amd/display: 64-bit division on 32-bit arch issue 2021-01-22 9:00 [PATCH] drm/amd/display: 64-bit division on 32-bit arch issue Lang Yu @ 2021-01-22 9:03 ` Huang Rui 2021-01-22 9:31 ` Chen, Guchun 0 siblings, 1 reply; 5+ messages in thread From: Huang Rui @ 2021-01-22 9:03 UTC (permalink / raw) To: Yu, Lang Cc: Deucher, Alexander, Lakha, Bhawanpreet, amd-gfx@lists.freedesktop.org On Fri, Jan 22, 2021 at 05:00:59PM +0800, Yu, Lang wrote: > Replace "/" with div_u64 for 32-bit arch. On 32-bit arch, > the use of "/" for 64-bit division will cause build error, > i.e. "__udivdi3/__divdi3 undefined!". > > Fixes: 27755cdf83f1 > drm/amd/display: Update dcn30_apply_idle_power_optimizations() code > > Signed-off-by: Lang Yu <Lang.Yu@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> > --- > drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c > index dff83c6a142a..9620fb8a27dc 100644 > --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c > +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c > @@ -772,8 +772,8 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) > cursor_cache_enable ? &cursor_attr : NULL)) { > unsigned int v_total = stream->adjust.v_total_max ? > stream->adjust.v_total_max : stream->timing.v_total; > - unsigned int refresh_hz = (unsigned long long) stream->timing.pix_clk_100hz * > - 100LL / (v_total * stream->timing.h_total); > + unsigned int refresh_hz = div_u64((unsigned long long) stream->timing.pix_clk_100hz * > + 100LL, (v_total * stream->timing.h_total)); > > /* > * one frame time in microsec: > @@ -800,8 +800,8 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) > unsigned int denom = refresh_hz * 6528; > unsigned int stutter_period = dc->current_state->perf_params.stutter_period_us; > > - tmr_delay = (((1000000LL + 2 * stutter_period * refresh_hz) * > - (100LL + dc->debug.mall_additional_timer_percent) + denom - 1) / > + tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) * > + (100LL + dc->debug.mall_additional_timer_percent) + denom - 1), > denom) - 64LL; > > /* scale should be increased until it fits into 6 bits */ > @@ -815,8 +815,8 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) > } > > denom *= 2; > - tmr_delay = (((1000000LL + 2 * stutter_period * refresh_hz) * > - (100LL + dc->debug.mall_additional_timer_percent) + denom - 1) / > + tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) * > + (100LL + dc->debug.mall_additional_timer_percent) + denom - 1), > denom) - 64LL; > } > > -- > 2.25.1 > _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH] drm/amd/display: 64-bit division on 32-bit arch issue 2021-01-22 9:03 ` Huang Rui @ 2021-01-22 9:31 ` Chen, Guchun 2021-01-22 12:35 ` Yu, Lang 0 siblings, 1 reply; 5+ messages in thread From: Chen, Guchun @ 2021-01-22 9:31 UTC (permalink / raw) To: Huang, Ray, Yu, Lang Cc: Deucher, Alexander, Lakha, Bhawanpreet, amd-gfx@lists.freedesktop.org [AMD Public Use] Maybe it's good to modify subject to " drm/amd/display: fix 64-bit division issue on 32-bit OS" And if header <linux/math64.h> should be included? Regards, Guchun -----Original Message----- From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Huang Rui Sent: Friday, January 22, 2021 5:04 PM To: Yu, Lang <Lang.Yu@amd.com> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com>; amd-gfx@lists.freedesktop.org Subject: Re: [PATCH] drm/amd/display: 64-bit division on 32-bit arch issue On Fri, Jan 22, 2021 at 05:00:59PM +0800, Yu, Lang wrote: > Replace "/" with div_u64 for 32-bit arch. On 32-bit arch, the use of > "/" for 64-bit division will cause build error, i.e. > "__udivdi3/__divdi3 undefined!". > > Fixes: 27755cdf83f1 > drm/amd/display: Update dcn30_apply_idle_power_optimizations() code > > Signed-off-by: Lang Yu <Lang.Yu@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> > --- > drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c > b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c > index dff83c6a142a..9620fb8a27dc 100644 > --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c > +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c > @@ -772,8 +772,8 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) > cursor_cache_enable ? &cursor_attr : NULL)) { > unsigned int v_total = stream->adjust.v_total_max ? > stream->adjust.v_total_max : stream->timing.v_total; > - unsigned int refresh_hz = (unsigned long long) stream->timing.pix_clk_100hz * > - 100LL / (v_total * stream->timing.h_total); > + unsigned int refresh_hz = div_u64((unsigned long long) stream->timing.pix_clk_100hz * > + 100LL, (v_total * stream->timing.h_total)); > > /* > * one frame time in microsec: > @@ -800,8 +800,8 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) > unsigned int denom = refresh_hz * 6528; > unsigned int stutter_period = > dc->current_state->perf_params.stutter_period_us; > > - tmr_delay = (((1000000LL + 2 * stutter_period * refresh_hz) * > - (100LL + dc->debug.mall_additional_timer_percent) + denom - 1) / > + tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) * > + (100LL + dc->debug.mall_additional_timer_percent) + denom - 1), > denom) - 64LL; > > /* scale should be increased until it fits into 6 bits */ @@ > -815,8 +815,8 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) > } > > denom *= 2; > - tmr_delay = (((1000000LL + 2 * stutter_period * refresh_hz) * > - (100LL + dc->debug.mall_additional_timer_percent) + denom - 1) / > + tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) * > + (100LL + dc->debug.mall_additional_timer_percent) + denom - > +1), > denom) - 64LL; > } > > -- > 2.25.1 > _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7Cguchun.chen%40amd.com%7Cd61b9d6686b64c78d73b08d8beb4ac34%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637469030487750031%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=zKx39HfCyPJmDR9NH1r0Vtap5HBImUxVBae7h1ORhUA%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH] drm/amd/display: 64-bit division on 32-bit arch issue 2021-01-22 9:31 ` Chen, Guchun @ 2021-01-22 12:35 ` Yu, Lang 2021-01-22 20:03 ` Lakha, Bhawanpreet 0 siblings, 1 reply; 5+ messages in thread From: Yu, Lang @ 2021-01-22 12:35 UTC (permalink / raw) To: Chen, Guchun, Huang, Ray Cc: Deucher, Alexander, Lakha, Bhawanpreet, amd-gfx@lists.freedesktop.org [AMD Public Use] The header <linux/math64.h> has been included by dm_services.h. The following is the sequence, dm_services.h -> dm_services_types.h -> os_types.h -> drm/drm_print.h -> linux/device.h -> linux/pm.h -> linux/timer.h -> linux/time.h -> linux/jiffies.h -> linux/math64.h Regards, Lang -----Original Message----- From: Chen, Guchun <Guchun.Chen@amd.com> Sent: Friday, January 22, 2021 5:32 PM To: Huang, Ray <Ray.Huang@amd.com>; Yu, Lang <Lang.Yu@amd.com> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com>; amd-gfx@lists.freedesktop.org Subject: RE: [PATCH] drm/amd/display: 64-bit division on 32-bit arch issue [AMD Public Use] Maybe it's good to modify subject to " drm/amd/display: fix 64-bit division issue on 32-bit OS" And if header <linux/math64.h> should be included? Regards, Guchun -----Original Message----- From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Huang Rui Sent: Friday, January 22, 2021 5:04 PM To: Yu, Lang <Lang.Yu@amd.com> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com>; amd-gfx@lists.freedesktop.org Subject: Re: [PATCH] drm/amd/display: 64-bit division on 32-bit arch issue On Fri, Jan 22, 2021 at 05:00:59PM +0800, Yu, Lang wrote: > Replace "/" with div_u64 for 32-bit arch. On 32-bit arch, the use of > "/" for 64-bit division will cause build error, i.e. > "__udivdi3/__divdi3 undefined!". > > Fixes: 27755cdf83f1 > drm/amd/display: Update dcn30_apply_idle_power_optimizations() code > > Signed-off-by: Lang Yu <Lang.Yu@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> > --- > drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c > b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c > index dff83c6a142a..9620fb8a27dc 100644 > --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c > +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c > @@ -772,8 +772,8 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) > cursor_cache_enable ? &cursor_attr : NULL)) { > unsigned int v_total = stream->adjust.v_total_max ? > stream->adjust.v_total_max : stream->timing.v_total; > - unsigned int refresh_hz = (unsigned long long) stream->timing.pix_clk_100hz * > - 100LL / (v_total * stream->timing.h_total); > + unsigned int refresh_hz = div_u64((unsigned long long) stream->timing.pix_clk_100hz * > + 100LL, (v_total * stream->timing.h_total)); > > /* > * one frame time in microsec: > @@ -800,8 +800,8 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) > unsigned int denom = refresh_hz * 6528; > unsigned int stutter_period = > dc->current_state->perf_params.stutter_period_us; > > - tmr_delay = (((1000000LL + 2 * stutter_period * refresh_hz) * > - (100LL + dc->debug.mall_additional_timer_percent) + denom - 1) / > + tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) * > + (100LL + dc->debug.mall_additional_timer_percent) + denom - 1), > denom) - 64LL; > > /* scale should be increased until it fits into 6 bits */ @@ > -815,8 +815,8 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) > } > > denom *= 2; > - tmr_delay = (((1000000LL + 2 * stutter_period * refresh_hz) * > - (100LL + dc->debug.mall_additional_timer_percent) + denom - 1) / > + tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) * > + (100LL + dc->debug.mall_additional_timer_percent) + denom - > +1), > denom) - 64LL; > } > > -- > 2.25.1 > _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7Cguchun.chen%40amd.com%7Cd61b9d6686b64c78d73b08d8beb4ac34%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637469030487750031%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=zKx39HfCyPJmDR9NH1r0Vtap5HBImUxVBae7h1ORhUA%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/amd/display: 64-bit division on 32-bit arch issue 2021-01-22 12:35 ` Yu, Lang @ 2021-01-22 20:03 ` Lakha, Bhawanpreet 0 siblings, 0 replies; 5+ messages in thread From: Lakha, Bhawanpreet @ 2021-01-22 20:03 UTC (permalink / raw) To: Yu, Lang, Chen, Guchun, Huang, Ray Cc: Deucher, Alexander, amd-gfx@lists.freedesktop.org [-- Attachment #1.1: Type: text/plain, Size: 5748 bytes --] [AMD Public Use] Thanks for the fix. Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Thanks, Bhawan ________________________________ From: Yu, Lang <Lang.Yu@amd.com> Sent: January 22, 2021 7:35 AM To: Chen, Guchun <Guchun.Chen@amd.com>; Huang, Ray <Ray.Huang@amd.com> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com>; amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org> Subject: RE: [PATCH] drm/amd/display: 64-bit division on 32-bit arch issue [AMD Public Use] The header <linux/math64.h> has been included by dm_services.h. The following is the sequence, dm_services.h -> dm_services_types.h -> os_types.h -> drm/drm_print.h -> linux/device.h -> linux/pm.h -> linux/timer.h -> linux/time.h -> linux/jiffies.h -> linux/math64.h Regards, Lang -----Original Message----- From: Chen, Guchun <Guchun.Chen@amd.com> Sent: Friday, January 22, 2021 5:32 PM To: Huang, Ray <Ray.Huang@amd.com>; Yu, Lang <Lang.Yu@amd.com> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com>; amd-gfx@lists.freedesktop.org Subject: RE: [PATCH] drm/amd/display: 64-bit division on 32-bit arch issue [AMD Public Use] Maybe it’s good to modify subject to " drm/amd/display: fix 64-bit division issue on 32-bit OS" And if header <linux/math64.h> should be included? Regards, Guchun -----Original Message----- From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Huang Rui Sent: Friday, January 22, 2021 5:04 PM To: Yu, Lang <Lang.Yu@amd.com> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com>; amd-gfx@lists.freedesktop.org Subject: Re: [PATCH] drm/amd/display: 64-bit division on 32-bit arch issue On Fri, Jan 22, 2021 at 05:00:59PM +0800, Yu, Lang wrote: > Replace "/" with div_u64 for 32-bit arch. On 32-bit arch, the use of > "/" for 64-bit division will cause build error, i.e. > "__udivdi3/__divdi3 undefined!". > > Fixes: 27755cdf83f1 > drm/amd/display: Update dcn30_apply_idle_power_optimizations() code > > Signed-off-by: Lang Yu <Lang.Yu@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> > --- > drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c > b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c > index dff83c6a142a..9620fb8a27dc 100644 > --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c > +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c > @@ -772,8 +772,8 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) > cursor_cache_enable ? &cursor_attr : NULL)) { > unsigned int v_total = stream->adjust.v_total_max ? > stream->adjust.v_total_max : stream->timing.v_total; > - unsigned int refresh_hz = (unsigned long long) stream->timing.pix_clk_100hz * > - 100LL / (v_total * stream->timing.h_total); > + unsigned int refresh_hz = div_u64((unsigned long long) stream->timing.pix_clk_100hz * > + 100LL, (v_total * stream->timing.h_total)); > > /* > * one frame time in microsec: > @@ -800,8 +800,8 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) > unsigned int denom = refresh_hz * 6528; > unsigned int stutter_period = > dc->current_state->perf_params.stutter_period_us; > > - tmr_delay = (((1000000LL + 2 * stutter_period * refresh_hz) * > - (100LL + dc->debug.mall_additional_timer_percent) + denom - 1) / > + tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) * > + (100LL + dc->debug.mall_additional_timer_percent) + denom - 1), > denom) - 64LL; > > /* scale should be increased until it fits into 6 bits */ @@ > -815,8 +815,8 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) > } > > denom *= 2; > - tmr_delay = (((1000000LL + 2 * stutter_period * refresh_hz) * > - (100LL + dc->debug.mall_additional_timer_percent) + denom - 1) / > + tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) * > + (100LL + dc->debug.mall_additional_timer_percent) + denom - > +1), > denom) - 64LL; > } > > -- > 2.25.1 > _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7Cguchun.chen%40amd.com%7Cd61b9d6686b64c78d73b08d8beb4ac34%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637469030487750031%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=zKx39HfCyPJmDR9NH1r0Vtap5HBImUxVBae7h1ORhUA%3D&reserved=0 [-- Attachment #1.2: Type: text/html, Size: 13310 bytes --] [-- Attachment #2: Type: text/plain, Size: 154 bytes --] _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2021-01-22 20:03 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2021-01-22 9:00 [PATCH] drm/amd/display: 64-bit division on 32-bit arch issue Lang Yu 2021-01-22 9:03 ` Huang Rui 2021-01-22 9:31 ` Chen, Guchun 2021-01-22 12:35 ` Yu, Lang 2021-01-22 20:03 ` Lakha, Bhawanpreet
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