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From: Anson Jacob <Anson.Jacob@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Eryk.Brol@amd.com, Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
	Qingqing.Zhuo@amd.com, Rodrigo.Siqueira@amd.com,
	Wenjing Liu <Wenjing.Liu@amd.com>,
	Anson.Jacob@amd.com, Aurabindo.Pillai@amd.com,
	Jun Lei <jun.lei@amd.com>,
	Bhawanpreet.Lakha@amd.com, bindu.r@amd.com
Subject: [PATCH 15/27] drm/amd/display: implement support for DID2.0 dsc passthrough
Date: Fri, 29 Jan 2021 16:27:40 -0500	[thread overview]
Message-ID: <20210129212752.38865-16-Anson.Jacob@amd.com> (raw)
In-Reply-To: <20210129212752.38865-1-Anson.Jacob@amd.com>

From: Jun Lei <jun.lei@amd.com>

[Why]
Some panels contain active converters (e.g. DP to MIPI) which only support
restricted DSC configurations.  DID2.0 adds support for such displays to
explicitly define per timing BPP restrictions on DSC.  Ignoring these
restrictions leads to blackscreen.

[How]
Add parsing in DID2.0 parser to get this bpp info.
Add support in DSC module to constraint target bpp based
on this info.

Signed-off-by: Jun Lei <jun.lei@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc_dsc.h      |  7 +++--
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h |  1 +
 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c  | 29 ++++++++++++--------
 3 files changed, 23 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
index ec55b77727d5..e99273bff46d 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
@@ -51,6 +51,7 @@ struct dc_dsc_policy {
 	int min_slice_height; // Must not be less than 8
 	uint32_t max_target_bpp;
 	uint32_t min_target_bpp;
+	uint32_t preferred_bpp_x16;
 	bool enable_dsc_when_not_needed;
 };
 
@@ -62,8 +63,8 @@ bool dc_dsc_parse_dsc_dpcd(const struct dc *dc,
 bool dc_dsc_compute_bandwidth_range(
 		const struct display_stream_compressor *dsc,
 		uint32_t dsc_min_slice_height_override,
-		uint32_t min_bpp,
-		uint32_t max_bpp,
+		uint32_t min_bpp_x16,
+		uint32_t max_bpp_x16,
 		const struct dsc_dec_dpcd_caps *dsc_sink_caps,
 		const struct dc_crtc_timing *timing,
 		struct dc_dsc_bw_range *range);
@@ -78,7 +79,7 @@ bool dc_dsc_compute_config(
 		struct dc_dsc_config *dsc_cfg);
 
 void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing,
-		uint32_t max_target_bpp_limit_override,
+		uint32_t max_target_bpp_limit_override_x16,
 		struct dc_dsc_policy *policy);
 
 void dc_dsc_policy_set_max_target_bpp_limit(uint32_t limit);
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index b41e6367b15e..09e8be5f7a1e 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -769,6 +769,7 @@ struct dc_crtc_timing {
 #endif
 
 	struct dc_crtc_timing_flags flags;
+	uint32_t dsc_fixed_bits_per_pixel_x16; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */
 	struct dc_dsc_config dsc_cfg;
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index c62d0eddc9c6..82a805088204 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -369,6 +369,11 @@ static bool decide_dsc_target_bpp_x16(
 		/* enough bandwidth without dsc */
 		*target_bpp_x16 = 0;
 		should_use_dsc = false;
+	} else if (policy->preferred_bpp_x16 > 0 &&
+			policy->preferred_bpp_x16 <= range.max_target_bpp_x16 &&
+			policy->preferred_bpp_x16 >= range.min_target_bpp_x16) {
+		*target_bpp_x16 = policy->preferred_bpp_x16;
+		should_use_dsc = true;
 	} else if (target_bandwidth_kbps >= range.max_kbps) {
 		/* use max target bpp allowed */
 		*target_bpp_x16 = range.max_target_bpp_x16;
@@ -545,7 +550,7 @@ static bool setup_dsc_config(
 		int target_bandwidth_kbps,
 		const struct dc_crtc_timing *timing,
 		int min_slice_height_override,
-		int max_dsc_target_bpp_limit_override,
+		int max_dsc_target_bpp_limit_override_x16,
 		struct dc_dsc_config *dsc_cfg)
 {
 	struct dsc_enc_caps dsc_common_caps;
@@ -564,7 +569,7 @@ static bool setup_dsc_config(
 
 	memset(dsc_cfg, 0, sizeof(struct dc_dsc_config));
 
-	dc_dsc_get_policy_for_timing(timing, max_dsc_target_bpp_limit_override, &policy);
+	dc_dsc_get_policy_for_timing(timing, max_dsc_target_bpp_limit_override_x16, &policy);
 	pic_width = timing->h_addressable + timing->h_border_left + timing->h_border_right;
 	pic_height = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
 
@@ -865,8 +870,8 @@ bool dc_dsc_parse_dsc_dpcd(const struct dc *dc, const uint8_t *dpcd_dsc_basic_da
 bool dc_dsc_compute_bandwidth_range(
 		const struct display_stream_compressor *dsc,
 		uint32_t dsc_min_slice_height_override,
-		uint32_t min_bpp,
-		uint32_t max_bpp,
+		uint32_t min_bpp_x16,
+		uint32_t max_bpp_x16,
 		const struct dsc_dec_dpcd_caps *dsc_sink_caps,
 		const struct dc_crtc_timing *timing,
 		struct dc_dsc_bw_range *range)
@@ -883,10 +888,10 @@ bool dc_dsc_compute_bandwidth_range(
 
 	if (is_dsc_possible)
 		is_dsc_possible = setup_dsc_config(dsc_sink_caps, &dsc_enc_caps, 0, timing,
-				dsc_min_slice_height_override, max_bpp, &config);
+				dsc_min_slice_height_override, max_bpp_x16, &config);
 
 	if (is_dsc_possible)
-		get_dsc_bandwidth_range(min_bpp, max_bpp, &dsc_common_caps, timing, range);
+		get_dsc_bandwidth_range(min_bpp_x16, max_bpp_x16, &dsc_common_caps, timing, range);
 
 	return is_dsc_possible;
 }
@@ -895,7 +900,7 @@ bool dc_dsc_compute_config(
 		const struct display_stream_compressor *dsc,
 		const struct dsc_dec_dpcd_caps *dsc_sink_caps,
 		uint32_t dsc_min_slice_height_override,
-		uint32_t max_target_bpp_limit_override,
+		uint32_t max_target_bpp_limit_override_x16,
 		uint32_t target_bandwidth_kbps,
 		const struct dc_crtc_timing *timing,
 		struct dc_dsc_config *dsc_cfg)
@@ -908,11 +913,11 @@ bool dc_dsc_compute_config(
 			&dsc_enc_caps,
 			target_bandwidth_kbps,
 			timing, dsc_min_slice_height_override,
-			max_target_bpp_limit_override, dsc_cfg);
+			max_target_bpp_limit_override_x16, dsc_cfg);
 	return is_dsc_possible;
 }
 
-void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, uint32_t max_target_bpp_limit_override, struct dc_dsc_policy *policy)
+void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, uint32_t max_target_bpp_limit_override_x16, struct dc_dsc_policy *policy)
 {
 	uint32_t bpc = 0;
 
@@ -967,13 +972,15 @@ void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, uint32_t
 		return;
 	}
 
+	policy->preferred_bpp_x16 = timing->dsc_fixed_bits_per_pixel_x16;
+
 	/* internal upper limit, default 16 bpp */
 	if (policy->max_target_bpp > dsc_policy_max_target_bpp_limit)
 		policy->max_target_bpp = dsc_policy_max_target_bpp_limit;
 
 	/* apply override */
-	if (max_target_bpp_limit_override && policy->max_target_bpp > max_target_bpp_limit_override)
-		policy->max_target_bpp = max_target_bpp_limit_override;
+	if (max_target_bpp_limit_override_x16 && policy->max_target_bpp > max_target_bpp_limit_override_x16 / 16)
+		policy->max_target_bpp = max_target_bpp_limit_override_x16 / 16;
 
 	/* enable DSC when not needed, default false */
 	if (dsc_policy_enable_dsc_when_not_needed)
-- 
2.25.1

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  parent reply	other threads:[~2021-01-29 21:28 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-29 21:27 [PATCH 00/27] DC Patches Jan 29, 2021 Anson Jacob
2021-01-29 21:27 ` [PATCH 01/27] drm/amd/display: Drop SOC bounding box hookup in DM/DC Anson Jacob
2021-01-29 21:27 ` [PATCH 02/27] drm/amd/display: Fix DPCD translation for LTTPR AUX_RD_INTERVAL Anson Jacob
2021-01-29 21:27 ` [PATCH 03/27] drm/amd/display: initialize i2c speed if not initialized in dcnxxx__resource.c Anson Jacob
2021-01-29 21:27 ` [PATCH 04/27] drm/amd/display: Add null pointer check to is_dig_enabled func Anson Jacob
2021-01-29 21:27 ` [PATCH 05/27] drm/amd/display: reuse current context instead of recreating one Anson Jacob
2021-02-10  2:57   ` youling257
2021-02-10  4:43     ` Alex Deucher
2021-02-10 13:48       ` youling 257
2021-01-29 21:27 ` [PATCH 06/27] drm/amd/display: Set power_gated to true for seamless boot pipe init Anson Jacob
2021-01-29 21:27 ` [PATCH 07/27] drm/amd/display: correct some hdcp variable naming Anson Jacob
2021-01-29 21:27 ` [PATCH 08/27] drm/amd/display: Add more Clock Sources to DCN2.1 Anson Jacob
2021-01-29 21:27 ` [PATCH 09/27] drm/amd/display: [FW Promotion] Release 0.0.49 Anson Jacob
2021-01-29 21:27 ` [PATCH 10/27] drm/amd/display: 3.2.120 Anson Jacob
2021-01-29 21:27 ` [PATCH 11/27] drm/amd/display: fix calculation for the pwl backlight curve Anson Jacob
2021-01-29 21:27 ` [PATCH 12/27] drm/amd/display: Revert "Fix EDID parsing after resume from suspend" Anson Jacob
2021-01-29 21:27 ` [PATCH 13/27] drm/amd/display: Release DSC before acquiring Anson Jacob
2021-01-29 21:27 ` [PATCH 14/27] drm/amd/display: Fix dc_sink kref count in emulated_link_detect Anson Jacob
2021-01-29 21:27 ` Anson Jacob [this message]
2021-01-29 21:27 ` [PATCH 16/27] drm/amd/display: fix initial bounding box values for dcn3.02 Anson Jacob
2021-01-29 21:27 ` [PATCH 17/27] drm/amd/display: Fix CW4 programming for dmub30 cached inbox Anson Jacob
2021-01-29 21:27 ` [PATCH 18/27] drm/amd/display: Enable "trigger_hotplug" debugfs on all outputs Anson Jacob
2021-01-29 21:27 ` [PATCH 19/27] drm/amd/display: Add Freesync HDMI support to DMCU Anson Jacob
2021-01-29 21:27 ` [PATCH 20/27] drm/amd/display: remove unused force_ignore_link_settings debug option Anson Jacob
2021-01-29 21:27 ` [PATCH 21/27] drm/amd/display: Free atomic state after drm_atomic_commit Anson Jacob
2021-01-29 21:27 ` [PATCH 22/27] drm/amd/display: Decrement refcount of dc_sink before reassignment Anson Jacob
2021-01-29 21:27 ` [PATCH 23/27] drm/amd/display: Workaround for some legacy DP-VGA dongles Anson Jacob
2021-01-29 21:27 ` [PATCH 24/27] drm/amd/display: Better handling of dummy p-state table Anson Jacob
2021-01-29 21:27 ` [PATCH 25/27] drm/amd/display: Reject too small viewport size when validating plane Anson Jacob
2021-01-29 21:27 ` [PATCH 26/27] drm/amd/display: [FW Promotion] Release 0.0.50 Anson Jacob
2021-01-29 21:27 ` [PATCH 27/27] drm/amd/display: 3.2.121 Anson Jacob
2021-01-29 22:06 ` [PATCH 00/27] DC Patches Jan 29, 2021 Wheeler, Daniel

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