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From: Anson Jacob <Anson.Jacob@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Eryk.Brol@amd.com, Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
	Qingqing.Zhuo@amd.com, Rodrigo.Siqueira@amd.com,
	Wenjing Liu <wenjing.liu@amd.com>,
	Anson.Jacob@amd.com, Aurabindo.Pillai@amd.com,
	George Shen <George.Shen@amd.com>,
	Bhawanpreet.Lakha@amd.com, bindu.r@amd.com
Subject: [PATCH 07/27] drm/amd/display: correct some hdcp variable naming
Date: Fri, 29 Jan 2021 16:27:32 -0500	[thread overview]
Message-ID: <20210129212752.38865-8-Anson.Jacob@amd.com> (raw)
In-Reply-To: <20210129212752.38865-1-Anson.Jacob@amd.com>

From: Wenjing Liu <wenjing.liu@amd.com>

[why]
In HDCP update stream config interface, some variables are named as
xxx_supported, but in fact the variable indicates whether or not xxx_enabled.
Correct the naming so it is less confusing to read the code.

Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Reviewed-by: George Shen <George.Shen@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c |  7 ++++---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c      | 14 +++++++-------
 drivers/gpu/drm/amd/display/dc/dm_cp_psp.h         |  7 ++++---
 drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h    |  2 +-
 .../gpu/drm/amd/display/modules/hdcp/hdcp_psp.c    |  2 +-
 drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h |  4 ++--
 6 files changed, 19 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
index c2cd184f0bbd..b297ddc24d3a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
@@ -449,11 +449,12 @@ static void update_config(void *handle, struct cp_psp_stream_config *config)
 		link->mode = mod_hdcp_signal_type_to_operation_mode(aconnector->dc_sink->sink_signal);
 
 	display->controller = CONTROLLER_ID_D0 + config->otg_inst;
-	display->dig_fe = config->stream_enc_inst;
-	link->dig_be = config->link_enc_inst;
+	display->dig_fe = config->dig_fe;
+	link->dig_be = config->dig_be;
 	link->ddc_line = aconnector->dc_link->ddc_hw_inst + 1;
 	link->dp.rev = aconnector->dc_link->dpcd_caps.dpcd_rev.raw;
-	link->dp.mst_supported = config->mst_supported;
+	link->dp.assr_enabled = config->assr_enabled;
+	link->dp.mst_enabled = config->mst_enabled;
 	display->adjust.disable = 1;
 	link->adjust.auth_delay = 3;
 	link->adjust.hdcp1.disable = 0;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 55f20d731b25..8506739a22f7 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3169,17 +3169,17 @@ static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
 {
 	struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;
 	if (cp_psp && cp_psp->funcs.update_stream_config) {
-		struct cp_psp_stream_config config;
-
-		memset(&config, 0, sizeof(config));
+		struct cp_psp_stream_config config = {0};
+		enum dp_panel_mode panel_mode =
+				dp_get_panel_mode(pipe_ctx->stream->link);
 
 		config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;
-		/*stream_enc_inst*/
-		config.stream_enc_inst = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;
-		config.link_enc_inst = pipe_ctx->stream->link->link_enc_hw_inst;
+		config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;
+		config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst;
 		config.dpms_off = dpms_off;
 		config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;
-		config.mst_supported = (pipe_ctx->stream->signal ==
+		config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP);
+		config.mst_enabled = (pipe_ctx->stream->signal ==
 				SIGNAL_TYPE_DISPLAY_PORT_MST);
 		cp_psp->funcs.update_stream_config(cp_psp->handle, &config);
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/dm_cp_psp.h b/drivers/gpu/drm/amd/display/dc/dm_cp_psp.h
index 5da7677627a1..cac0b2c0d31b 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_cp_psp.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_cp_psp.h
@@ -30,9 +30,10 @@ struct dc_link;
 
 struct cp_psp_stream_config {
 	uint8_t otg_inst;
-	uint8_t link_enc_inst;
-	uint8_t stream_enc_inst;
-	uint8_t mst_supported;
+	uint8_t dig_be;
+	uint8_t dig_fe;
+	uint8_t assr_enabled;
+	uint8_t mst_enabled;
 	void *dm_stream_ctx;
 	bool dpms_off;
 };
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
index 6c678cfb82e3..5c22cf7e6118 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
@@ -397,7 +397,7 @@ static inline uint8_t is_dp_hdcp(struct mod_hdcp *hdcp)
 static inline uint8_t is_dp_mst_hdcp(struct mod_hdcp *hdcp)
 {
 	return (hdcp->connection.link.mode == MOD_HDCP_MODE_DP &&
-			hdcp->connection.link.dp.mst_supported);
+			hdcp->connection.link.dp.mst_enabled);
 }
 
 static inline uint8_t is_hdmi_dvi_sl_hdcp(struct mod_hdcp *hdcp)
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
index 3a367a5968ae..b26ed64eaf98 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
@@ -106,7 +106,7 @@ enum mod_hdcp_status mod_hdcp_add_display_to_topology(struct mod_hdcp *hdcp,
 	dtm_cmd->dtm_in_message.topology_update_v2.dig_be = link->dig_be;
 	dtm_cmd->dtm_in_message.topology_update_v2.dig_fe = display->dig_fe;
 	if (is_dp_hdcp(hdcp))
-		dtm_cmd->dtm_in_message.topology_update_v2.is_assr = link->dp.assr_supported;
+		dtm_cmd->dtm_in_message.topology_update_v2.is_assr = link->dp.assr_enabled;
 
 	dtm_cmd->dtm_in_message.topology_update_v2.dp_mst_vcid = display->vc_id;
 	dtm_cmd->dtm_in_message.topology_update_v2.max_hdcp_supported_version =
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
index eed560eecbab..d223ed3be5d3 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
@@ -101,8 +101,8 @@ enum mod_hdcp_status {
 
 struct mod_hdcp_displayport {
 	uint8_t rev;
-	uint8_t assr_supported;
-	uint8_t mst_supported;
+	uint8_t assr_enabled;
+	uint8_t mst_enabled;
 };
 
 struct mod_hdcp_hdmi {
-- 
2.25.1

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  parent reply	other threads:[~2021-01-29 21:28 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-29 21:27 [PATCH 00/27] DC Patches Jan 29, 2021 Anson Jacob
2021-01-29 21:27 ` [PATCH 01/27] drm/amd/display: Drop SOC bounding box hookup in DM/DC Anson Jacob
2021-01-29 21:27 ` [PATCH 02/27] drm/amd/display: Fix DPCD translation for LTTPR AUX_RD_INTERVAL Anson Jacob
2021-01-29 21:27 ` [PATCH 03/27] drm/amd/display: initialize i2c speed if not initialized in dcnxxx__resource.c Anson Jacob
2021-01-29 21:27 ` [PATCH 04/27] drm/amd/display: Add null pointer check to is_dig_enabled func Anson Jacob
2021-01-29 21:27 ` [PATCH 05/27] drm/amd/display: reuse current context instead of recreating one Anson Jacob
2021-02-10  2:57   ` youling257
2021-02-10  4:43     ` Alex Deucher
2021-02-10 13:48       ` youling 257
2021-01-29 21:27 ` [PATCH 06/27] drm/amd/display: Set power_gated to true for seamless boot pipe init Anson Jacob
2021-01-29 21:27 ` Anson Jacob [this message]
2021-01-29 21:27 ` [PATCH 08/27] drm/amd/display: Add more Clock Sources to DCN2.1 Anson Jacob
2021-01-29 21:27 ` [PATCH 09/27] drm/amd/display: [FW Promotion] Release 0.0.49 Anson Jacob
2021-01-29 21:27 ` [PATCH 10/27] drm/amd/display: 3.2.120 Anson Jacob
2021-01-29 21:27 ` [PATCH 11/27] drm/amd/display: fix calculation for the pwl backlight curve Anson Jacob
2021-01-29 21:27 ` [PATCH 12/27] drm/amd/display: Revert "Fix EDID parsing after resume from suspend" Anson Jacob
2021-01-29 21:27 ` [PATCH 13/27] drm/amd/display: Release DSC before acquiring Anson Jacob
2021-01-29 21:27 ` [PATCH 14/27] drm/amd/display: Fix dc_sink kref count in emulated_link_detect Anson Jacob
2021-01-29 21:27 ` [PATCH 15/27] drm/amd/display: implement support for DID2.0 dsc passthrough Anson Jacob
2021-01-29 21:27 ` [PATCH 16/27] drm/amd/display: fix initial bounding box values for dcn3.02 Anson Jacob
2021-01-29 21:27 ` [PATCH 17/27] drm/amd/display: Fix CW4 programming for dmub30 cached inbox Anson Jacob
2021-01-29 21:27 ` [PATCH 18/27] drm/amd/display: Enable "trigger_hotplug" debugfs on all outputs Anson Jacob
2021-01-29 21:27 ` [PATCH 19/27] drm/amd/display: Add Freesync HDMI support to DMCU Anson Jacob
2021-01-29 21:27 ` [PATCH 20/27] drm/amd/display: remove unused force_ignore_link_settings debug option Anson Jacob
2021-01-29 21:27 ` [PATCH 21/27] drm/amd/display: Free atomic state after drm_atomic_commit Anson Jacob
2021-01-29 21:27 ` [PATCH 22/27] drm/amd/display: Decrement refcount of dc_sink before reassignment Anson Jacob
2021-01-29 21:27 ` [PATCH 23/27] drm/amd/display: Workaround for some legacy DP-VGA dongles Anson Jacob
2021-01-29 21:27 ` [PATCH 24/27] drm/amd/display: Better handling of dummy p-state table Anson Jacob
2021-01-29 21:27 ` [PATCH 25/27] drm/amd/display: Reject too small viewport size when validating plane Anson Jacob
2021-01-29 21:27 ` [PATCH 26/27] drm/amd/display: [FW Promotion] Release 0.0.50 Anson Jacob
2021-01-29 21:27 ` [PATCH 27/27] drm/amd/display: 3.2.121 Anson Jacob
2021-01-29 22:06 ` [PATCH 00/27] DC Patches Jan 29, 2021 Wheeler, Daniel

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