Re: [PATCH 2/2] soc: mediatek: pm-domains: Add domain_supply cap for mfg_async PD

[kernel test robot <lkp@intel.com>]

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Hi Bilal,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on soc/for-next]
[also build test ERROR on clk/clk-next linux/master next-20210125]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Bilal-Wasim/Misc-bug-fixes-in-mtk-power-domain-driver/20210201-135519
base:   https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git for-next
config: arc-randconfig-r006-20210201 (attached as .config)
compiler: arceb-elf-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/75afc46e31ee3d523fd11e48a5b9127b8d6a3718
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Bilal-Wasim/Misc-bug-fixes-in-mtk-power-domain-driver/20210201-135519
        git checkout 75afc46e31ee3d523fd11e48a5b9127b8d6a3718
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arc 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

   In file included from drivers/soc/mediatek/mtk-pm-domains.c:18:
>> drivers/soc/mediatek/mt8173-pm-domains.h:66:11: error: 'MTK_SCPD_DOMAIN_SUPPLY' undeclared here (not in a function)
      66 |   .caps = MTK_SCPD_DOMAIN_SUPPLY,
         |           ^~~~~~~~~~~~~~~~~~~~~~


vim +/MTK_SCPD_DOMAIN_SUPPLY +66 drivers/soc/mediatek/mt8173-pm-domains.h

     8	
     9	/*
    10	 * MT8173 power domain support
    11	 */
    12	
    13	static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {
    14		[MT8173_POWER_DOMAIN_VDEC] = {
    15			.sta_mask = PWR_STATUS_VDEC,
    16			.ctl_offs = SPM_VDE_PWR_CON,
    17			.sram_pdn_bits = GENMASK(11, 8),
    18			.sram_pdn_ack_bits = GENMASK(12, 12),
    19		},
    20		[MT8173_POWER_DOMAIN_VENC] = {
    21			.sta_mask = PWR_STATUS_VENC,
    22			.ctl_offs = SPM_VEN_PWR_CON,
    23			.sram_pdn_bits = GENMASK(11, 8),
    24			.sram_pdn_ack_bits = GENMASK(15, 12),
    25		},
    26		[MT8173_POWER_DOMAIN_ISP] = {
    27			.sta_mask = PWR_STATUS_ISP,
    28			.ctl_offs = SPM_ISP_PWR_CON,
    29			.sram_pdn_bits = GENMASK(11, 8),
    30			.sram_pdn_ack_bits = GENMASK(13, 12),
    31		},
    32		[MT8173_POWER_DOMAIN_MM] = {
    33			.sta_mask = PWR_STATUS_DISP,
    34			.ctl_offs = SPM_DIS_PWR_CON,
    35			.sram_pdn_bits = GENMASK(11, 8),
    36			.sram_pdn_ack_bits = GENMASK(12, 12),
    37			.bp_infracfg = {
    38				BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 |
    39						       MT8173_TOP_AXI_PROT_EN_MM_M1),
    40			},
    41		},
    42		[MT8173_POWER_DOMAIN_VENC_LT] = {
    43			.sta_mask = PWR_STATUS_VENC_LT,
    44			.ctl_offs = SPM_VEN2_PWR_CON,
    45			.sram_pdn_bits = GENMASK(11, 8),
    46			.sram_pdn_ack_bits = GENMASK(15, 12),
    47		},
    48		[MT8173_POWER_DOMAIN_AUDIO] = {
    49			.sta_mask = PWR_STATUS_AUDIO,
    50			.ctl_offs = SPM_AUDIO_PWR_CON,
    51			.sram_pdn_bits = GENMASK(11, 8),
    52			.sram_pdn_ack_bits = GENMASK(15, 12),
    53		},
    54		[MT8173_POWER_DOMAIN_USB] = {
    55			.sta_mask = PWR_STATUS_USB,
    56			.ctl_offs = SPM_USB_PWR_CON,
    57			.sram_pdn_bits = GENMASK(11, 8),
    58			.sram_pdn_ack_bits = GENMASK(15, 12),
    59			.caps = MTK_SCPD_ACTIVE_WAKEUP,
    60		},
    61		[MT8173_POWER_DOMAIN_MFG_ASYNC] = {
    62			.sta_mask = PWR_STATUS_MFG_ASYNC,
    63			.ctl_offs = SPM_MFG_ASYNC_PWR_CON,
    64			.sram_pdn_bits = GENMASK(11, 8),
    65			.sram_pdn_ack_bits = 0,
  > 66			.caps = MTK_SCPD_DOMAIN_SUPPLY,
    67		},
    68		[MT8173_POWER_DOMAIN_MFG_2D] = {
    69			.sta_mask = PWR_STATUS_MFG_2D,
    70			.ctl_offs = SPM_MFG_2D_PWR_CON,
    71			.sram_pdn_bits = GENMASK(11, 8),
    72			.sram_pdn_ack_bits = GENMASK(13, 12),
    73		},
    74		[MT8173_POWER_DOMAIN_MFG] = {
    75			.sta_mask = PWR_STATUS_MFG,
    76			.ctl_offs = SPM_MFG_PWR_CON,
    77			.sram_pdn_bits = GENMASK(13, 8),
    78			.sram_pdn_ack_bits = GENMASK(21, 16),
    79			.bp_infracfg = {
    80				BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S |
    81						       MT8173_TOP_AXI_PROT_EN_MFG_M0 |
    82						       MT8173_TOP_AXI_PROT_EN_MFG_M1 |
    83						       MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT),
    84			},
    85		},
    86	};
    87	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

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