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From: Rob Herring <robh@kernel.org>
To: Damien Le Moal <damien.lemoal@wdc.com>
Cc: devicetree@vger.kernel.org, Anup Patel <anup.patel@wdc.com>,
	Sean Anderson <seanga2@gmail.com>,
	Atish Patra <atish.patra@wdc.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	linux-riscv@lists.infradead.org
Subject: Re: [PATCH v15 04/16] dt-bindings: update sifive plic compatible string
Date: Thu, 4 Feb 2021 17:48:19 -0600	[thread overview]
Message-ID: <20210204234819.GA1348461@robh.at.kernel.org> (raw)
In-Reply-To: <20210203125913.390949-5-damien.lemoal@wdc.com>

On Wed, Feb 03, 2021 at 09:59:01PM +0900, Damien Le Moal wrote:
> Add the compatible string "canaan,k210-plic" to the Sifive plic bindings
> to indicate the use of the "sifive,plic-1.0.0" IP block in the Canaan
> Kendryte K210 SoC. The description is also updated to reflect this
> change, that is, that SoCs from other vendors may also use this plic
> implementation.
> 
> Cc: Paul Walmsley <paul.walmsley@sifive.com>
> Cc: Rob Herring <robh@kernel.org>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
> Reviewed-by: Atish Patra <atish.patra@wdc.com>
> ---
>  .../sifive,plic-1.0.0.yaml                    | 20 ++++++++++++-------
>  1 file changed, 13 insertions(+), 7 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> index b9a61c9f7530..04ed7a03c97e 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> @@ -8,10 +8,11 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
>  title: SiFive Platform-Level Interrupt Controller (PLIC)
>  
>  description:
> -  SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
> -  (PLIC) high-level specification in the RISC-V Privileged Architecture
> -  specification. The PLIC connects all external interrupts in the system to all
> -  hart contexts in the system, via the external interrupt source in each hart.
> +  SiFive SoCs and other RISC-V SoCs include an implementation of the
> +  Platform-Level Interrupt Controller (PLIC) high-level specification in
> +  the RISC-V Privileged Architecture specification. The PLIC connects all
> +  external interrupts in the system to all hart contexts in the system, via
> +  the external interrupt source in each hart.
>  
>    A hart context is a privilege mode in a hardware execution thread. For example,
>    in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
> @@ -41,9 +42,14 @@ maintainers:
>  
>  properties:
>    compatible:
> -    items:
> -      - const: sifive,fu540-c000-plic

Change this to an 'enum' and add 'canaan,k210-plic'.

> -      - const: sifive,plic-1.0.0
> +    oneOf:
> +      - items:
> +          - const: sifive,fu540-c000-plic
> +          - const: sifive,plic-1.0.0
> +
> +      - items:
> +          - const: canaan,k210-plic
> +          - const: sifive,plic-1.0.0
>  
>    reg:
>      maxItems: 1
> -- 
> 2.29.2
> 

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WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Damien Le Moal <damien.lemoal@wdc.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	linux-riscv@lists.infradead.org,
	Atish Patra <atish.patra@wdc.com>,
	Anup Patel <anup.patel@wdc.com>,
	Sean Anderson <seanga2@gmail.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	devicetree@vger.kernel.org
Subject: Re: [PATCH v15 04/16] dt-bindings: update sifive plic compatible string
Date: Thu, 4 Feb 2021 17:48:19 -0600	[thread overview]
Message-ID: <20210204234819.GA1348461@robh.at.kernel.org> (raw)
In-Reply-To: <20210203125913.390949-5-damien.lemoal@wdc.com>

On Wed, Feb 03, 2021 at 09:59:01PM +0900, Damien Le Moal wrote:
> Add the compatible string "canaan,k210-plic" to the Sifive plic bindings
> to indicate the use of the "sifive,plic-1.0.0" IP block in the Canaan
> Kendryte K210 SoC. The description is also updated to reflect this
> change, that is, that SoCs from other vendors may also use this plic
> implementation.
> 
> Cc: Paul Walmsley <paul.walmsley@sifive.com>
> Cc: Rob Herring <robh@kernel.org>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
> Reviewed-by: Atish Patra <atish.patra@wdc.com>
> ---
>  .../sifive,plic-1.0.0.yaml                    | 20 ++++++++++++-------
>  1 file changed, 13 insertions(+), 7 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> index b9a61c9f7530..04ed7a03c97e 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> @@ -8,10 +8,11 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
>  title: SiFive Platform-Level Interrupt Controller (PLIC)
>  
>  description:
> -  SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
> -  (PLIC) high-level specification in the RISC-V Privileged Architecture
> -  specification. The PLIC connects all external interrupts in the system to all
> -  hart contexts in the system, via the external interrupt source in each hart.
> +  SiFive SoCs and other RISC-V SoCs include an implementation of the
> +  Platform-Level Interrupt Controller (PLIC) high-level specification in
> +  the RISC-V Privileged Architecture specification. The PLIC connects all
> +  external interrupts in the system to all hart contexts in the system, via
> +  the external interrupt source in each hart.
>  
>    A hart context is a privilege mode in a hardware execution thread. For example,
>    in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
> @@ -41,9 +42,14 @@ maintainers:
>  
>  properties:
>    compatible:
> -    items:
> -      - const: sifive,fu540-c000-plic

Change this to an 'enum' and add 'canaan,k210-plic'.

> -      - const: sifive,plic-1.0.0
> +    oneOf:
> +      - items:
> +          - const: sifive,fu540-c000-plic
> +          - const: sifive,plic-1.0.0
> +
> +      - items:
> +          - const: canaan,k210-plic
> +          - const: sifive,plic-1.0.0
>  
>    reg:
>      maxItems: 1
> -- 
> 2.29.2
> 

  reply	other threads:[~2021-02-04 23:48 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-03 12:58 [PATCH v15 00/16] RISC-V Kendryte K210 support improvements Damien Le Moal
2021-02-03 12:58 ` [PATCH v15 01/16] clk: Add RISC-V Canaan Kendryte K210 clock driver Damien Le Moal
2021-02-03 12:58   ` Damien Le Moal
2021-02-05  0:32   ` Damien Le Moal
2021-02-05  0:32     ` Damien Le Moal
2021-02-05  3:38   ` Anup Patel
2021-02-05  3:38     ` Anup Patel
2021-02-03 12:58 ` [PATCH v15 02/16] dt-bindings: add Canaan boards compatible strings Damien Le Moal
2021-02-03 12:58   ` Damien Le Moal
2021-02-04 23:46   ` Rob Herring
2021-02-04 23:46     ` Rob Herring
2021-02-03 12:59 ` [PATCH v15 03/16] dt-bindings: update risc-v cpu properties Damien Le Moal
2021-02-03 12:59   ` Damien Le Moal
2021-02-05  4:34   ` Anup Patel
2021-02-05  4:34     ` Anup Patel
2021-02-03 12:59 ` [PATCH v15 04/16] dt-bindings: update sifive plic compatible string Damien Le Moal
2021-02-03 12:59   ` Damien Le Moal
2021-02-04 23:48   ` Rob Herring [this message]
2021-02-04 23:48     ` Rob Herring
2021-02-03 12:59 ` [PATCH v15 05/16] dt-bindings: update sifive clint " Damien Le Moal
2021-02-03 12:59   ` Damien Le Moal
2021-02-04 23:49   ` Rob Herring
2021-02-04 23:49     ` Rob Herring
2021-02-03 12:59 ` [PATCH v15 06/16] dt-bindings: update sifive uart " Damien Le Moal
2021-02-03 12:59   ` Damien Le Moal
2021-02-04 23:49   ` Rob Herring
2021-02-04 23:49     ` Rob Herring
2021-02-03 12:59 ` [PATCH v15 07/16] dt-bindings: fix sifive gpio properties Damien Le Moal
2021-02-03 12:59   ` Damien Le Moal
2021-02-03 18:02   ` Atish Patra
2021-02-03 18:02     ` Atish Patra
2021-02-03 12:59 ` [PATCH v15 08/16] dt-bindings: add resets property to dw-apb-timer Damien Le Moal
2021-02-03 12:59   ` Damien Le Moal
2021-02-04 23:49   ` Rob Herring
2021-02-04 23:49     ` Rob Herring
2021-02-03 12:59 ` [PATCH v15 09/16] riscv: Update Canaan Kendryte K210 device tree Damien Le Moal
2021-02-03 12:59   ` Damien Le Moal
2021-02-03 12:59 ` [PATCH v15 10/16] riscv: Add SiPeed MAIX BiT board " Damien Le Moal
2021-02-03 12:59   ` Damien Le Moal
2021-02-03 12:59 ` [PATCH v15 11/16] riscv: Add SiPeed MAIX DOCK " Damien Le Moal
2021-02-03 12:59   ` Damien Le Moal
2021-02-03 12:59 ` [PATCH v15 12/16] riscv: Add SiPeed MAIX GO " Damien Le Moal
2021-02-03 12:59   ` Damien Le Moal
2021-02-03 12:59 ` [PATCH v15 13/16] riscv: Add SiPeed MAIXDUINO " Damien Le Moal
2021-02-03 12:59   ` Damien Le Moal
2021-02-03 12:59 ` [PATCH v15 14/16] riscv: Add Kendryte KD233 " Damien Le Moal
2021-02-03 12:59   ` Damien Le Moal
2021-02-03 12:59 ` [PATCH v15 15/16] riscv: Update Canaan Kendryte K210 defconfig Damien Le Moal
2021-02-03 12:59 ` [PATCH v15 16/16] riscv: Add Canaan Kendryte K210 SD card defconfig Damien Le Moal
2021-02-05  3:44 ` [PATCH v15 00/16] RISC-V Kendryte K210 support improvements Palmer Dabbelt
2021-02-05  4:03   ` Damien Le Moal

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