From: Rob Herring <robh@kernel.org>
To: Damien Le Moal <damien.lemoal@wdc.com>
Cc: devicetree@vger.kernel.org, Anup Patel <anup.patel@wdc.com>,
Sean Anderson <seanga2@gmail.com>,
Atish Patra <atish.patra@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH v16 03/16] dt-bindings: update risc-v cpu properties
Date: Fri, 5 Feb 2021 13:47:11 -0600 [thread overview]
Message-ID: <20210205194711.GA3597111@robh.at.kernel.org> (raw)
In-Reply-To: <20210205065827.577285-4-damien.lemoal@wdc.com>
On Fri, 05 Feb 2021 15:58:14 +0900, Damien Le Moal wrote:
> The Canaan Kendryte K210 SoC CPU cores are based on a rocket chip
> version using a draft verion of the RISC-V ISA specifications. To avoid
> any confusion with CPU cores using stable specifications, add the
> compatible string "canaan,k210" for this SoC CPU cores.
>
> Also add the "riscv,none" value to the mmu-type property to allow a DT
> to indicate that the CPU being described does not have an MMU or that
> it has an MMU that is not usable (which is the case for the K210 SoC).
>
> Cc: Paul Walmsley <paul.walmsley@sifive.com>
> Cc: Rob Herring <robh@kernel.org>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
> Reviewed-by: Atish Patra <atish.patra@wdc.com>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Damien Le Moal <damien.lemoal@wdc.com>
Cc: devicetree@vger.kernel.org,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Sean Anderson <seanga2@gmail.com>,
Anup Patel <anup.patel@wdc.com>,
Atish Patra <atish.patra@wdc.com>,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH v16 03/16] dt-bindings: update risc-v cpu properties
Date: Fri, 5 Feb 2021 13:47:11 -0600 [thread overview]
Message-ID: <20210205194711.GA3597111@robh.at.kernel.org> (raw)
In-Reply-To: <20210205065827.577285-4-damien.lemoal@wdc.com>
On Fri, 05 Feb 2021 15:58:14 +0900, Damien Le Moal wrote:
> The Canaan Kendryte K210 SoC CPU cores are based on a rocket chip
> version using a draft verion of the RISC-V ISA specifications. To avoid
> any confusion with CPU cores using stable specifications, add the
> compatible string "canaan,k210" for this SoC CPU cores.
>
> Also add the "riscv,none" value to the mmu-type property to allow a DT
> to indicate that the CPU being described does not have an MMU or that
> it has an MMU that is not usable (which is the case for the K210 SoC).
>
> Cc: Paul Walmsley <paul.walmsley@sifive.com>
> Cc: Rob Herring <robh@kernel.org>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
> Reviewed-by: Atish Patra <atish.patra@wdc.com>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
next prev parent reply other threads:[~2021-02-05 19:47 UTC|newest]
Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-05 6:58 [PATCH v16 00/16] RISC-V Kendryte K210 support improvements Damien Le Moal
2021-02-05 6:58 ` [PATCH v16 01/16] clk: Add RISC-V Canaan Kendryte K210 clock driver Damien Le Moal
2021-02-05 6:58 ` Damien Le Moal
2021-02-05 6:58 ` [PATCH v16 02/16] dt-bindings: add Canaan boards compatible strings Damien Le Moal
2021-02-05 6:58 ` Damien Le Moal
2021-02-05 6:58 ` [PATCH v16 03/16] dt-bindings: update risc-v cpu properties Damien Le Moal
2021-02-05 6:58 ` Damien Le Moal
2021-02-05 19:47 ` Rob Herring [this message]
2021-02-05 19:47 ` Rob Herring
2021-02-05 6:58 ` [PATCH v16 04/16] dt-bindings: update sifive plic compatible string Damien Le Moal
2021-02-05 6:58 ` Damien Le Moal
2021-02-05 19:47 ` Rob Herring
2021-02-05 19:47 ` Rob Herring
2021-02-05 6:58 ` [PATCH v16 05/16] dt-bindings: update sifive clint " Damien Le Moal
2021-02-05 6:58 ` Damien Le Moal
2021-02-05 19:48 ` Rob Herring
2021-02-05 19:48 ` Rob Herring
2021-02-05 6:58 ` [PATCH v16 06/16] dt-bindings: update sifive uart " Damien Le Moal
2021-02-05 6:58 ` Damien Le Moal
2021-02-05 6:58 ` [PATCH v16 07/16] dt-bindings: fix sifive gpio properties Damien Le Moal
2021-02-05 6:58 ` Damien Le Moal
2021-02-05 6:58 ` [PATCH v16 08/16] dt-bindings: add resets property to dw-apb-timer Damien Le Moal
2021-02-05 6:58 ` Damien Le Moal
2021-02-05 6:58 ` [PATCH v16 09/16] riscv: Update Canaan Kendryte K210 device tree Damien Le Moal
2021-02-05 6:58 ` Damien Le Moal
2021-02-05 20:25 ` Rob Herring
2021-02-05 20:25 ` Rob Herring
2021-02-05 22:52 ` Sean Anderson
2021-02-05 22:52 ` Sean Anderson
2021-02-05 23:49 ` Damien Le Moal
2021-02-05 23:49 ` Damien Le Moal
2021-02-08 19:49 ` Rob Herring
2021-02-08 19:49 ` Rob Herring
2021-02-08 22:41 ` Damien Le Moal
2021-02-08 22:41 ` Damien Le Moal
2021-02-06 0:13 ` Damien Le Moal
2021-02-06 0:13 ` Damien Le Moal
2021-02-08 20:00 ` Rob Herring
2021-02-08 20:00 ` Rob Herring
2021-02-08 22:53 ` Sean Anderson
2021-02-08 22:53 ` Sean Anderson
2021-02-08 22:55 ` Damien Le Moal
2021-02-08 22:55 ` Damien Le Moal
2021-02-08 23:04 ` Sean Anderson
2021-02-08 23:04 ` Sean Anderson
2021-02-09 0:12 ` Damien Le Moal
2021-02-09 0:12 ` Damien Le Moal
2021-02-05 6:58 ` [PATCH v16 10/16] riscv: Add SiPeed MAIX BiT board " Damien Le Moal
2021-02-05 6:58 ` Damien Le Moal
2021-02-05 6:58 ` [PATCH v16 11/16] riscv: Add SiPeed MAIX DOCK " Damien Le Moal
2021-02-05 6:58 ` Damien Le Moal
2021-02-05 6:58 ` [PATCH v16 12/16] riscv: Add SiPeed MAIX GO " Damien Le Moal
2021-02-05 6:58 ` Damien Le Moal
2021-02-05 6:58 ` [PATCH v16 13/16] riscv: Add SiPeed MAIXDUINO " Damien Le Moal
2021-02-05 6:58 ` Damien Le Moal
2021-02-05 6:58 ` [PATCH v16 14/16] riscv: Add Kendryte KD233 " Damien Le Moal
2021-02-05 6:58 ` Damien Le Moal
2021-02-05 6:58 ` [PATCH v16 15/16] riscv: Update Canaan Kendryte K210 defconfig Damien Le Moal
2021-02-05 6:58 ` [PATCH v16 16/16] riscv: Add Canaan Kendryte K210 SD card defconfig Damien Le Moal
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210205194711.GA3597111@robh.at.kernel.org \
--to=robh@kernel.org \
--cc=anup.patel@wdc.com \
--cc=atish.patra@wdc.com \
--cc=damien.lemoal@wdc.com \
--cc=devicetree@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=seanga2@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.