drivers/media/i2c/ccs-pll.c:386:5: warning: stack frame size of 2976 bytes in function 'ccs_pll_calculate'

[kernel test robot <lkp@intel.com>]

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tree:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head:   61556703b610a104de324e4f061dc6cf7b218b46
commit: 9e05bbac43ebfc2fd1ff95e072730ceed807d149 media: smiapp-pll: Rename as ccs-pll
date:   9 weeks ago
config: powerpc64-randconfig-r025-20210205 (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project c9439ca36342fb6013187d0a69aef92736951476)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install powerpc64 cross compiling tool for clang build
        # apt-get install binutils-powerpc64-linux-gnu
        # https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=9e05bbac43ebfc2fd1ff95e072730ceed807d149
        git remote add linus https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
        git fetch --no-tags linus master
        git checkout 9e05bbac43ebfc2fd1ff95e072730ceed807d149
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=powerpc64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/media/i2c/ccs-pll.c:386:5: warning: stack frame size of 2976 bytes in function 'ccs_pll_calculate' [-Wframe-larger-than=]
   int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits,
       ^
   1 warning generated.


vim +/ccs_pll_calculate +386 drivers/media/i2c/ccs-pll.c

   385	
 > 386	int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits,
   387			      struct ccs_pll *pll)
   388	{
   389		const struct ccs_pll_branch_limits *op_limits = &limits->op;
   390		struct ccs_pll_branch *op_pll = &pll->op;
   391		uint16_t min_pre_pll_clk_div;
   392		uint16_t max_pre_pll_clk_div;
   393		uint32_t lane_op_clock_ratio;
   394		uint32_t mul, div;
   395		unsigned int i;
   396		int rval = -EINVAL;
   397	
   398		if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) {
   399			/*
   400			 * If there's no OP PLL at all, use the VT values
   401			 * instead. The OP values are ignored for the rest of
   402			 * the PLL calculation.
   403			 */
   404			op_limits = &limits->vt;
   405			op_pll = &pll->vt;
   406		}
   407	
   408		if (pll->flags & CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE)
   409			lane_op_clock_ratio = pll->csi2.lanes;
   410		else
   411			lane_op_clock_ratio = 1;
   412		dev_dbg(dev, "lane_op_clock_ratio: %u\n", lane_op_clock_ratio);
   413	
   414		dev_dbg(dev, "binning: %ux%u\n", pll->binning_horizontal,
   415			pll->binning_vertical);
   416	
   417		switch (pll->bus_type) {
   418		case CCS_PLL_BUS_TYPE_CSI2:
   419			/* CSI transfers 2 bits per clock per lane; thus times 2 */
   420			pll->pll_op_clk_freq_hz = pll->link_freq * 2
   421				* (pll->csi2.lanes / lane_op_clock_ratio);
   422			break;
   423		case CCS_PLL_BUS_TYPE_PARALLEL:
   424			pll->pll_op_clk_freq_hz = pll->link_freq * pll->bits_per_pixel
   425				/ DIV_ROUND_UP(pll->bits_per_pixel,
   426					       pll->parallel.bus_width);
   427			break;
   428		default:
   429			return -EINVAL;
   430		}
   431	
   432		/* Figure out limits for pre-pll divider based on extclk */
   433		dev_dbg(dev, "min / max pre_pll_clk_div: %u / %u\n",
   434			limits->min_pre_pll_clk_div, limits->max_pre_pll_clk_div);
   435		max_pre_pll_clk_div =
   436			min_t(uint16_t, limits->max_pre_pll_clk_div,
   437			      clk_div_even(pll->ext_clk_freq_hz /
   438					   limits->min_pll_ip_freq_hz));
   439		min_pre_pll_clk_div =
   440			max_t(uint16_t, limits->min_pre_pll_clk_div,
   441			      clk_div_even_up(
   442				      DIV_ROUND_UP(pll->ext_clk_freq_hz,
   443						   limits->max_pll_ip_freq_hz)));
   444		dev_dbg(dev, "pre-pll check: min / max pre_pll_clk_div: %u / %u\n",
   445			min_pre_pll_clk_div, max_pre_pll_clk_div);
   446	
   447		i = gcd(pll->pll_op_clk_freq_hz, pll->ext_clk_freq_hz);
   448		mul = div_u64(pll->pll_op_clk_freq_hz, i);
   449		div = pll->ext_clk_freq_hz / i;
   450		dev_dbg(dev, "mul %u / div %u\n", mul, div);
   451	
   452		min_pre_pll_clk_div =
   453			max_t(uint16_t, min_pre_pll_clk_div,
   454			      clk_div_even_up(
   455				      DIV_ROUND_UP(mul * pll->ext_clk_freq_hz,
   456						   limits->max_pll_op_freq_hz)));
   457		dev_dbg(dev, "pll_op check: min / max pre_pll_clk_div: %u / %u\n",
   458			min_pre_pll_clk_div, max_pre_pll_clk_div);
   459	
   460		for (pll->pre_pll_clk_div = min_pre_pll_clk_div;
   461		     pll->pre_pll_clk_div <= max_pre_pll_clk_div;
   462		     pll->pre_pll_clk_div += 2 - (pll->pre_pll_clk_div & 1)) {
   463			rval = __ccs_pll_calculate(dev, limits, op_limits, pll, op_pll,
   464						   mul, div, lane_op_clock_ratio);
   465			if (rval)
   466				continue;
   467	
   468			print_pll(dev, pll);
   469			return 0;
   470		}
   471	
   472		dev_dbg(dev, "unable to compute pre_pll divisor\n");
   473	
   474		return rval;
   475	}
   476	EXPORT_SYMBOL_GPL(ccs_pll_calculate);
   477	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

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