From: Guenter Roeck <linux@roeck-us.net>
To: Hsin-Yi Wang <hsinyi@chromium.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org,
Philipp Zabel <p.zabel@pengutronix.de>,
David Airlie <airlied@linux.ie>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
Matthias Brugger <matthias.bgg@gmail.com>,
linux-mediatek@lists.infradead.org,
Yongqiang Niu <yongqiang.niu@mediatek.com>,
CK Hu <ck.hu@mediatek.com>, Daniel Vetter <daniel@ffwll.ch>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v6 2/8] drm/mediatek: add component POSTMASK
Date: Tue, 9 Feb 2021 07:32:06 -0800 [thread overview]
Message-ID: <20210209153206.GA19067@roeck-us.net> (raw)
In-Reply-To: <20210202081237.774442-3-hsinyi@chromium.org>
On Tue, Feb 02, 2021 at 04:12:31PM +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu <yongqiang.niu@mediatek.com>
>
> This patch add component POSTMASK.
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> ---
[ ... ]
>
> +void mtk_postmask_config(struct device *dev, unsigned int w,
static
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs,
> + DISP_POSTMASK_SIZE);
> + mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg,
> + priv->regs, DISP_POSTMASK_CFG);
> +}
> +
> +void mtk_postmask_start(struct device *dev)
static
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + writel(POSTMASK_EN, priv->regs + DISP_POSTMASK_EN);
> +}
> +
> +void mtk_postmask_stop(struct device *dev)
static
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + writel_relaxed(0x0, priv->regs + DISP_POSTMASK_EN);
> +}
> +
> static void mtk_aal_config(struct device *dev, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> @@ -413,6 +445,14 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = {
> .bgclr_in_off = mtk_ovl_bgclr_in_off,
> };
>
> +static const struct mtk_ddp_comp_funcs ddp_postmask = {
> + .clk_enable = mtk_ddp_clk_enable,
> + .clk_disable = mtk_ddp_clk_disable,
> + .config = mtk_postmask_config,
> + .start = mtk_postmask_start,
> + .stop = mtk_postmask_stop,
> +};
> +
> static const struct mtk_ddp_comp_funcs ddp_rdma = {
> .clk_enable = mtk_rdma_clk_enable,
> .clk_disable = mtk_rdma_clk_disable,
> @@ -448,6 +488,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> [MTK_DISP_MUTEX] = "mutex",
> [MTK_DISP_OD] = "od",
> [MTK_DISP_BLS] = "bls",
> + [MTK_DISP_POSTMASK] = "postmask",
> };
>
> struct mtk_ddp_comp_match {
> @@ -457,36 +498,37 @@ struct mtk_ddp_comp_match {
> };
>
> static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> - [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal },
> - [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal },
> - [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL },
> - [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr },
> - [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color },
> - [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color },
> - [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither },
> - [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
> - [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
> - [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi },
> - [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
> - [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
> - [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi },
> - [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
> - [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od },
> - [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },
> - [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl },
> - [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl },
> - [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
> - [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
> - [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl },
> - [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
> - [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
> - [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
> - [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma },
> - [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma },
> - [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma },
> - [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe },
> - [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL },
> - [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },
> + [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal },
> + [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal },
> + [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL },
> + [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr },
> + [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color },
> + [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color },
> + [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither },
> + [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
> + [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
> + [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi },
> + [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
> + [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
> + [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi },
> + [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
> + [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od },
> + [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },
> + [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl },
> + [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl },
> + [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
> + [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
> + [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl },
> + [DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask },
> + [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
> + [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
> + [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
> + [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma },
> + [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma },
> + [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma },
> + [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe },
> + [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL },
> + [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },
> };
>
> static bool mtk_drm_find_comp_in_ddp(struct device *dev,
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index bb914d976cf5d..cd1dec6b4cdf2 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -30,6 +30,7 @@ enum mtk_ddp_comp_type {
> MTK_DISP_UFOE,
> MTK_DSI,
> MTK_DPI,
> + MTK_DISP_POSTMASK,
> MTK_DISP_PWM,
> MTK_DISP_MUTEX,
> MTK_DISP_OD,
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: Guenter Roeck <linux@roeck-us.net>
To: Hsin-Yi Wang <hsinyi@chromium.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org,
Philipp Zabel <p.zabel@pengutronix.de>,
David Airlie <airlied@linux.ie>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
Matthias Brugger <matthias.bgg@gmail.com>,
linux-mediatek@lists.infradead.org,
Yongqiang Niu <yongqiang.niu@mediatek.com>,
CK Hu <ck.hu@mediatek.com>, Daniel Vetter <daniel@ffwll.ch>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v6 2/8] drm/mediatek: add component POSTMASK
Date: Tue, 9 Feb 2021 07:32:06 -0800 [thread overview]
Message-ID: <20210209153206.GA19067@roeck-us.net> (raw)
In-Reply-To: <20210202081237.774442-3-hsinyi@chromium.org>
On Tue, Feb 02, 2021 at 04:12:31PM +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu <yongqiang.niu@mediatek.com>
>
> This patch add component POSTMASK.
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> ---
[ ... ]
>
> +void mtk_postmask_config(struct device *dev, unsigned int w,
static
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs,
> + DISP_POSTMASK_SIZE);
> + mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg,
> + priv->regs, DISP_POSTMASK_CFG);
> +}
> +
> +void mtk_postmask_start(struct device *dev)
static
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + writel(POSTMASK_EN, priv->regs + DISP_POSTMASK_EN);
> +}
> +
> +void mtk_postmask_stop(struct device *dev)
static
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + writel_relaxed(0x0, priv->regs + DISP_POSTMASK_EN);
> +}
> +
> static void mtk_aal_config(struct device *dev, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> @@ -413,6 +445,14 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = {
> .bgclr_in_off = mtk_ovl_bgclr_in_off,
> };
>
> +static const struct mtk_ddp_comp_funcs ddp_postmask = {
> + .clk_enable = mtk_ddp_clk_enable,
> + .clk_disable = mtk_ddp_clk_disable,
> + .config = mtk_postmask_config,
> + .start = mtk_postmask_start,
> + .stop = mtk_postmask_stop,
> +};
> +
> static const struct mtk_ddp_comp_funcs ddp_rdma = {
> .clk_enable = mtk_rdma_clk_enable,
> .clk_disable = mtk_rdma_clk_disable,
> @@ -448,6 +488,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> [MTK_DISP_MUTEX] = "mutex",
> [MTK_DISP_OD] = "od",
> [MTK_DISP_BLS] = "bls",
> + [MTK_DISP_POSTMASK] = "postmask",
> };
>
> struct mtk_ddp_comp_match {
> @@ -457,36 +498,37 @@ struct mtk_ddp_comp_match {
> };
>
> static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> - [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal },
> - [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal },
> - [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL },
> - [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr },
> - [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color },
> - [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color },
> - [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither },
> - [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
> - [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
> - [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi },
> - [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
> - [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
> - [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi },
> - [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
> - [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od },
> - [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },
> - [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl },
> - [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl },
> - [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
> - [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
> - [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl },
> - [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
> - [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
> - [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
> - [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma },
> - [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma },
> - [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma },
> - [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe },
> - [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL },
> - [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },
> + [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal },
> + [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal },
> + [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL },
> + [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr },
> + [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color },
> + [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color },
> + [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither },
> + [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
> + [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
> + [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi },
> + [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
> + [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
> + [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi },
> + [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
> + [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od },
> + [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },
> + [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl },
> + [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl },
> + [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
> + [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
> + [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl },
> + [DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask },
> + [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
> + [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
> + [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
> + [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma },
> + [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma },
> + [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma },
> + [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe },
> + [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL },
> + [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },
> };
>
> static bool mtk_drm_find_comp_in_ddp(struct device *dev,
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index bb914d976cf5d..cd1dec6b4cdf2 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -30,6 +30,7 @@ enum mtk_ddp_comp_type {
> MTK_DISP_UFOE,
> MTK_DSI,
> MTK_DPI,
> + MTK_DISP_POSTMASK,
> MTK_DISP_PWM,
> MTK_DISP_MUTEX,
> MTK_DISP_OD,
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Guenter Roeck <linux@roeck-us.net>
To: Hsin-Yi Wang <hsinyi@chromium.org>
Cc: CK Hu <ck.hu@mediatek.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Matthias Brugger <matthias.bgg@gmail.com>,
Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org,
Yongqiang Niu <yongqiang.niu@mediatek.com>,
David Airlie <airlied@linux.ie>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
linux-mediatek@lists.infradead.org,
Daniel Vetter <daniel@ffwll.ch>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v6 2/8] drm/mediatek: add component POSTMASK
Date: Tue, 9 Feb 2021 07:32:06 -0800 [thread overview]
Message-ID: <20210209153206.GA19067@roeck-us.net> (raw)
In-Reply-To: <20210202081237.774442-3-hsinyi@chromium.org>
On Tue, Feb 02, 2021 at 04:12:31PM +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu <yongqiang.niu@mediatek.com>
>
> This patch add component POSTMASK.
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> ---
[ ... ]
>
> +void mtk_postmask_config(struct device *dev, unsigned int w,
static
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs,
> + DISP_POSTMASK_SIZE);
> + mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg,
> + priv->regs, DISP_POSTMASK_CFG);
> +}
> +
> +void mtk_postmask_start(struct device *dev)
static
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + writel(POSTMASK_EN, priv->regs + DISP_POSTMASK_EN);
> +}
> +
> +void mtk_postmask_stop(struct device *dev)
static
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + writel_relaxed(0x0, priv->regs + DISP_POSTMASK_EN);
> +}
> +
> static void mtk_aal_config(struct device *dev, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> @@ -413,6 +445,14 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = {
> .bgclr_in_off = mtk_ovl_bgclr_in_off,
> };
>
> +static const struct mtk_ddp_comp_funcs ddp_postmask = {
> + .clk_enable = mtk_ddp_clk_enable,
> + .clk_disable = mtk_ddp_clk_disable,
> + .config = mtk_postmask_config,
> + .start = mtk_postmask_start,
> + .stop = mtk_postmask_stop,
> +};
> +
> static const struct mtk_ddp_comp_funcs ddp_rdma = {
> .clk_enable = mtk_rdma_clk_enable,
> .clk_disable = mtk_rdma_clk_disable,
> @@ -448,6 +488,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> [MTK_DISP_MUTEX] = "mutex",
> [MTK_DISP_OD] = "od",
> [MTK_DISP_BLS] = "bls",
> + [MTK_DISP_POSTMASK] = "postmask",
> };
>
> struct mtk_ddp_comp_match {
> @@ -457,36 +498,37 @@ struct mtk_ddp_comp_match {
> };
>
> static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> - [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal },
> - [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal },
> - [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL },
> - [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr },
> - [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color },
> - [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color },
> - [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither },
> - [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
> - [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
> - [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi },
> - [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
> - [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
> - [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi },
> - [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
> - [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od },
> - [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },
> - [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl },
> - [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl },
> - [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
> - [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
> - [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl },
> - [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
> - [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
> - [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
> - [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma },
> - [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma },
> - [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma },
> - [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe },
> - [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL },
> - [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },
> + [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal },
> + [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal },
> + [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL },
> + [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr },
> + [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color },
> + [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color },
> + [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither },
> + [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
> + [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
> + [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi },
> + [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
> + [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
> + [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi },
> + [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
> + [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od },
> + [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },
> + [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl },
> + [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl },
> + [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
> + [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
> + [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl },
> + [DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask },
> + [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
> + [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
> + [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
> + [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma },
> + [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma },
> + [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma },
> + [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe },
> + [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL },
> + [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },
> };
>
> static bool mtk_drm_find_comp_in_ddp(struct device *dev,
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index bb914d976cf5d..cd1dec6b4cdf2 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -30,6 +30,7 @@ enum mtk_ddp_comp_type {
> MTK_DISP_UFOE,
> MTK_DSI,
> MTK_DPI,
> + MTK_DISP_POSTMASK,
> MTK_DISP_PWM,
> MTK_DISP_MUTEX,
> MTK_DISP_OD,
WARNING: multiple messages have this Message-ID (diff)
From: Guenter Roeck <linux@roeck-us.net>
To: Hsin-Yi Wang <hsinyi@chromium.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org, David Airlie <airlied@linux.ie>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
Matthias Brugger <matthias.bgg@gmail.com>,
linux-mediatek@lists.infradead.org,
Yongqiang Niu <yongqiang.niu@mediatek.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v6 2/8] drm/mediatek: add component POSTMASK
Date: Tue, 9 Feb 2021 07:32:06 -0800 [thread overview]
Message-ID: <20210209153206.GA19067@roeck-us.net> (raw)
In-Reply-To: <20210202081237.774442-3-hsinyi@chromium.org>
On Tue, Feb 02, 2021 at 04:12:31PM +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu <yongqiang.niu@mediatek.com>
>
> This patch add component POSTMASK.
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> ---
[ ... ]
>
> +void mtk_postmask_config(struct device *dev, unsigned int w,
static
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs,
> + DISP_POSTMASK_SIZE);
> + mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg,
> + priv->regs, DISP_POSTMASK_CFG);
> +}
> +
> +void mtk_postmask_start(struct device *dev)
static
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + writel(POSTMASK_EN, priv->regs + DISP_POSTMASK_EN);
> +}
> +
> +void mtk_postmask_stop(struct device *dev)
static
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + writel_relaxed(0x0, priv->regs + DISP_POSTMASK_EN);
> +}
> +
> static void mtk_aal_config(struct device *dev, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> @@ -413,6 +445,14 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = {
> .bgclr_in_off = mtk_ovl_bgclr_in_off,
> };
>
> +static const struct mtk_ddp_comp_funcs ddp_postmask = {
> + .clk_enable = mtk_ddp_clk_enable,
> + .clk_disable = mtk_ddp_clk_disable,
> + .config = mtk_postmask_config,
> + .start = mtk_postmask_start,
> + .stop = mtk_postmask_stop,
> +};
> +
> static const struct mtk_ddp_comp_funcs ddp_rdma = {
> .clk_enable = mtk_rdma_clk_enable,
> .clk_disable = mtk_rdma_clk_disable,
> @@ -448,6 +488,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> [MTK_DISP_MUTEX] = "mutex",
> [MTK_DISP_OD] = "od",
> [MTK_DISP_BLS] = "bls",
> + [MTK_DISP_POSTMASK] = "postmask",
> };
>
> struct mtk_ddp_comp_match {
> @@ -457,36 +498,37 @@ struct mtk_ddp_comp_match {
> };
>
> static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> - [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal },
> - [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal },
> - [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL },
> - [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr },
> - [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color },
> - [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color },
> - [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither },
> - [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
> - [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
> - [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi },
> - [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
> - [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
> - [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi },
> - [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
> - [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od },
> - [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },
> - [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl },
> - [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl },
> - [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
> - [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
> - [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl },
> - [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
> - [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
> - [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
> - [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma },
> - [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma },
> - [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma },
> - [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe },
> - [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL },
> - [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },
> + [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal },
> + [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal },
> + [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL },
> + [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr },
> + [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color },
> + [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color },
> + [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither },
> + [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
> + [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
> + [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi },
> + [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
> + [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
> + [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi },
> + [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
> + [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od },
> + [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },
> + [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl },
> + [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl },
> + [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
> + [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
> + [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl },
> + [DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask },
> + [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
> + [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
> + [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
> + [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma },
> + [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma },
> + [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma },
> + [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe },
> + [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL },
> + [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },
> };
>
> static bool mtk_drm_find_comp_in_ddp(struct device *dev,
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index bb914d976cf5d..cd1dec6b4cdf2 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -30,6 +30,7 @@ enum mtk_ddp_comp_type {
> MTK_DISP_UFOE,
> MTK_DSI,
> MTK_DPI,
> + MTK_DISP_POSTMASK,
> MTK_DISP_PWM,
> MTK_DISP_MUTEX,
> MTK_DISP_OD,
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next prev parent reply other threads:[~2021-02-09 15:32 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-02 8:12 [PATCH v6 0/8] drm/mediatek: add support for mediatek SOC MT8192 Hsin-Yi Wang
2021-02-02 8:12 ` Hsin-Yi Wang
2021-02-02 8:12 ` Hsin-Yi Wang
2021-02-02 8:12 ` Hsin-Yi Wang
2021-02-02 8:12 ` [PATCH v6 1/8] drm/mediatek: add component OVL_2L2 Hsin-Yi Wang
2021-02-02 8:12 ` Hsin-Yi Wang
2021-02-02 8:12 ` Hsin-Yi Wang
2021-02-02 8:12 ` Hsin-Yi Wang
2021-02-02 8:12 ` [PATCH v6 2/8] drm/mediatek: add component POSTMASK Hsin-Yi Wang
2021-02-02 8:12 ` Hsin-Yi Wang
2021-02-02 8:12 ` Hsin-Yi Wang
2021-02-02 8:12 ` Hsin-Yi Wang
2021-02-02 9:09 ` CK Hu
2021-02-02 9:09 ` CK Hu
2021-02-02 9:09 ` CK Hu
2021-02-02 9:09 ` CK Hu
2021-02-09 15:32 ` Guenter Roeck [this message]
2021-02-09 15:32 ` Guenter Roeck
2021-02-09 15:32 ` Guenter Roeck
2021-02-09 15:32 ` Guenter Roeck
2021-02-02 8:12 ` [PATCH v6 3/8] drm/mediatek: add component RDMA4 Hsin-Yi Wang
2021-02-02 8:12 ` Hsin-Yi Wang
2021-02-02 8:12 ` Hsin-Yi Wang
2021-02-02 8:12 ` Hsin-Yi Wang
2021-02-02 8:12 ` [PATCH v6 4/8] drm/mediatek: separate ccorr module Hsin-Yi Wang
2021-02-02 8:12 ` Hsin-Yi Wang
2021-02-02 8:12 ` Hsin-Yi Wang
2021-02-02 8:12 ` Hsin-Yi Wang
2021-02-03 16:13 ` Chun-Kuang Hu
2021-02-03 16:13 ` Chun-Kuang Hu
2021-02-03 16:13 ` Chun-Kuang Hu
2021-02-03 16:13 ` Chun-Kuang Hu
2021-02-02 8:12 ` [PATCH v6 5/8] drm/mediatek: Fix ccorr size config Hsin-Yi Wang
2021-02-02 8:12 ` Hsin-Yi Wang
2021-02-02 8:12 ` Hsin-Yi Wang
2021-02-02 8:12 ` Hsin-Yi Wang
2021-02-03 16:13 ` Chun-Kuang Hu
2021-02-03 16:13 ` Chun-Kuang Hu
2021-02-03 16:13 ` Chun-Kuang Hu
2021-02-03 16:13 ` Chun-Kuang Hu
2021-02-02 8:12 ` [PATCH v6 6/8] drm/mediatek: add matrix_bits private data for ccorr Hsin-Yi Wang
2021-02-02 8:12 ` Hsin-Yi Wang
2021-02-02 8:12 ` Hsin-Yi Wang
2021-02-02 8:12 ` Hsin-Yi Wang
2021-02-02 9:11 ` CK Hu
2021-02-02 9:11 ` CK Hu
2021-02-02 9:11 ` CK Hu
2021-02-02 9:11 ` CK Hu
2021-02-03 16:14 ` Chun-Kuang Hu
2021-02-03 16:14 ` Chun-Kuang Hu
2021-02-03 16:14 ` Chun-Kuang Hu
2021-02-03 16:14 ` Chun-Kuang Hu
2021-02-02 8:12 ` [PATCH v6 7/8] soc: mediatek: add mtk mutex support for MT8192 Hsin-Yi Wang
2021-02-02 8:12 ` Hsin-Yi Wang
2021-02-02 8:12 ` Hsin-Yi Wang
2021-02-02 8:12 ` Hsin-Yi Wang
2021-02-02 8:12 ` [PATCH v6 8/8] drm/mediatek: add support for mediatek SOC MT8192 Hsin-Yi Wang
2021-02-02 8:12 ` Hsin-Yi Wang
2021-02-02 8:12 ` Hsin-Yi Wang
2021-02-02 8:12 ` Hsin-Yi Wang
2021-02-02 9:12 ` CK Hu
2021-02-02 9:12 ` CK Hu
2021-02-02 9:12 ` CK Hu
2021-02-02 9:12 ` CK Hu
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