* [PATCH v3 1/2] mhi: pci_generic: Parametrable element count for events @ 2021-02-16 17:52 Loic Poulain 2021-02-16 17:52 ` [PATCH v3 2/2] mhi: pci_generic: Introduce quectel EM1XXGR-L support Loic Poulain 2021-02-24 9:32 ` [PATCH v3 1/2] mhi: pci_generic: Parametrable element count for events Manivannan Sadhasivam 0 siblings, 2 replies; 4+ messages in thread From: Loic Poulain @ 2021-02-16 17:52 UTC (permalink / raw) To: manivannan.sadhasivam, hemantk Cc: linux-arm-msm, carl.yin, mpearson, cchen50, jwjiang, ivan.zhang, naveen.kumar, ivan.mikhanchuk, Loic Poulain Not all hardwares need to use the same number of event ring elements. This change makes this parametrable. Signed-off-by: Loic Poulain <loic.poulain@linaro.org> --- v2: add this change to the series v3: no change drivers/bus/mhi/pci_generic.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 8187fcf..c58bf96 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -71,9 +71,9 @@ struct mhi_pci_dev_info { .doorbell_mode_switch = false, \ } -#define MHI_EVENT_CONFIG_CTRL(ev_ring) \ +#define MHI_EVENT_CONFIG_CTRL(ev_ring, el_count) \ { \ - .num_elements = 64, \ + .num_elements = el_count, \ .irq_moderation_ms = 0, \ .irq = (ev_ring) + 1, \ .priority = 1, \ @@ -114,9 +114,9 @@ struct mhi_pci_dev_info { .doorbell_mode_switch = true, \ } -#define MHI_EVENT_CONFIG_DATA(ev_ring) \ +#define MHI_EVENT_CONFIG_DATA(ev_ring, el_count) \ { \ - .num_elements = 128, \ + .num_elements = el_count, \ .irq_moderation_ms = 5, \ .irq = (ev_ring) + 1, \ .priority = 1, \ @@ -127,9 +127,9 @@ struct mhi_pci_dev_info { .offload_channel = false, \ } -#define MHI_EVENT_CONFIG_HW_DATA(ev_ring, ch_num) \ +#define MHI_EVENT_CONFIG_HW_DATA(ev_ring, el_count, ch_num) \ { \ - .num_elements = 2048, \ + .num_elements = el_count, \ .irq_moderation_ms = 1, \ .irq = (ev_ring) + 1, \ .priority = 1, \ @@ -156,12 +156,12 @@ static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { static struct mhi_event_config modem_qcom_v1_mhi_events[] = { /* first ring is control+data ring */ - MHI_EVENT_CONFIG_CTRL(0), + MHI_EVENT_CONFIG_CTRL(0, 64), /* DIAG dedicated event ring */ - MHI_EVENT_CONFIG_DATA(1), + MHI_EVENT_CONFIG_DATA(1, 128), /* Hardware channels request dedicated hardware event rings */ - MHI_EVENT_CONFIG_HW_DATA(2, 100), - MHI_EVENT_CONFIG_HW_DATA(3, 101) + MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), + MHI_EVENT_CONFIG_HW_DATA(3, 2048, 101) }; static struct mhi_controller_config modem_qcom_v1_mhiv_config = { -- 2.7.4 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v3 2/2] mhi: pci_generic: Introduce quectel EM1XXGR-L support 2021-02-16 17:52 [PATCH v3 1/2] mhi: pci_generic: Parametrable element count for events Loic Poulain @ 2021-02-16 17:52 ` Loic Poulain 2021-02-24 9:34 ` Manivannan Sadhasivam 2021-02-24 9:32 ` [PATCH v3 1/2] mhi: pci_generic: Parametrable element count for events Manivannan Sadhasivam 1 sibling, 1 reply; 4+ messages in thread From: Loic Poulain @ 2021-02-16 17:52 UTC (permalink / raw) To: manivannan.sadhasivam, hemantk Cc: linux-arm-msm, carl.yin, mpearson, cchen50, jwjiang, ivan.zhang, naveen.kumar, ivan.mikhanchuk, Loic Poulain Add support for EM1XXGR-L modems, this modem series is based on SDX24 qcom chip. The modem is mainly based on MBIM protocol for both the data and control path. The drivers for these channels (mhi-net-mbim and mhi_uci) are not yet part of the kernel but will be integrated by different series. Signed-off-by: Loic Poulain <loic.poulain@linaro.org> --- v2: Specify 256 elements for the hardware event rings v3: increase hw event elements to 1024 (aligned with downstream) drivers/bus/mhi/pci_generic.c | 73 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index c58bf96..42b3952 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -114,6 +114,36 @@ struct mhi_pci_dev_info { .doorbell_mode_switch = true, \ } +#define MHI_CHANNEL_CONFIG_UL_SBL(ch_num, ch_name, el_count, ev_ring) \ + { \ + .num = ch_num, \ + .name = ch_name, \ + .num_elements = el_count, \ + .event_ring = ev_ring, \ + .dir = DMA_TO_DEVICE, \ + .ee_mask = BIT(MHI_EE_SBL), \ + .pollcfg = 0, \ + .doorbell = MHI_DB_BRST_DISABLE, \ + .lpm_notify = false, \ + .offload_channel = false, \ + .doorbell_mode_switch = false, \ + } \ + +#define MHI_CHANNEL_CONFIG_DL_SBL(ch_num, ch_name, el_count, ev_ring) \ + { \ + .num = ch_num, \ + .name = ch_name, \ + .num_elements = el_count, \ + .event_ring = ev_ring, \ + .dir = DMA_FROM_DEVICE, \ + .ee_mask = BIT(MHI_EE_SBL), \ + .pollcfg = 0, \ + .doorbell = MHI_DB_BRST_DISABLE, \ + .lpm_notify = false, \ + .offload_channel = false, \ + .doorbell_mode_switch = false, \ + } + #define MHI_EVENT_CONFIG_DATA(ev_ring, el_count) \ { \ .num_elements = el_count, \ @@ -182,9 +212,52 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = { .dma_data_width = 32 }; +static const struct mhi_channel_config mhi_quectel_em1xx_channels[] = { + MHI_CHANNEL_CONFIG_UL(0, "NMEA", 32, 0), + MHI_CHANNEL_CONFIG_DL(1, "NMEA", 32, 0), + MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), + MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0), + MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1), + MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1), + MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), + MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), + MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), + MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), + MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), + MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), +}; + +static struct mhi_event_config mhi_quectel_em1xx_events[] = { + MHI_EVENT_CONFIG_CTRL(0, 128), + MHI_EVENT_CONFIG_DATA(1, 128), + MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), + MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101) +}; + +static struct mhi_controller_config modem_quectel_em1xx_config = { + .max_channels = 128, + .timeout_ms = 8000, + .num_channels = ARRAY_SIZE(mhi_quectel_em1xx_channels), + .ch_cfg = mhi_quectel_em1xx_channels, + .num_events = ARRAY_SIZE(mhi_quectel_em1xx_events), + .event_cfg = mhi_quectel_em1xx_events, +}; + +static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = { + .name = "quectel-em1xx", + .edl = "quectel/prog_firehose_sdx24.mbn", + .config = &modem_quectel_em1xx_config, + .bar_num = MHI_PCI_DEFAULT_BAR_NUM, + .dma_data_width = 32 +}; + static const struct pci_device_id mhi_pci_id_table[] = { { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306), .driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info }, + { PCI_DEVICE(0x1eac, 0x1001), /* EM120R-GL (sdx24) */ + .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, + { PCI_DEVICE(0x1eac, 0x1002), /* EM160R-GL (sdx24) */ + .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, { } }; MODULE_DEVICE_TABLE(pci, mhi_pci_id_table); -- 2.7.4 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v3 2/2] mhi: pci_generic: Introduce quectel EM1XXGR-L support 2021-02-16 17:52 ` [PATCH v3 2/2] mhi: pci_generic: Introduce quectel EM1XXGR-L support Loic Poulain @ 2021-02-24 9:34 ` Manivannan Sadhasivam 0 siblings, 0 replies; 4+ messages in thread From: Manivannan Sadhasivam @ 2021-02-24 9:34 UTC (permalink / raw) To: Loic Poulain Cc: hemantk, linux-arm-msm, carl.yin, mpearson, cchen50, jwjiang, ivan.zhang, naveen.kumar, ivan.mikhanchuk On Tue, Feb 16, 2021 at 06:52:28PM +0100, Loic Poulain wrote: > Add support for EM1XXGR-L modems, this modem series is based on SDX24 > qcom chip. The modem is mainly based on MBIM protocol for both the > data and control path. The drivers for these channels (mhi-net-mbim and > mhi_uci) are not yet part of the kernel but will be integrated by > different series. > > Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Thanks, Mani > --- > v2: Specify 256 elements for the hardware event rings > v3: increase hw event elements to 1024 (aligned with downstream) > > drivers/bus/mhi/pci_generic.c | 73 +++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 73 insertions(+) > > diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c > index c58bf96..42b3952 100644 > --- a/drivers/bus/mhi/pci_generic.c > +++ b/drivers/bus/mhi/pci_generic.c > @@ -114,6 +114,36 @@ struct mhi_pci_dev_info { > .doorbell_mode_switch = true, \ > } > > +#define MHI_CHANNEL_CONFIG_UL_SBL(ch_num, ch_name, el_count, ev_ring) \ > + { \ > + .num = ch_num, \ > + .name = ch_name, \ > + .num_elements = el_count, \ > + .event_ring = ev_ring, \ > + .dir = DMA_TO_DEVICE, \ > + .ee_mask = BIT(MHI_EE_SBL), \ > + .pollcfg = 0, \ > + .doorbell = MHI_DB_BRST_DISABLE, \ > + .lpm_notify = false, \ > + .offload_channel = false, \ > + .doorbell_mode_switch = false, \ > + } \ > + > +#define MHI_CHANNEL_CONFIG_DL_SBL(ch_num, ch_name, el_count, ev_ring) \ > + { \ > + .num = ch_num, \ > + .name = ch_name, \ > + .num_elements = el_count, \ > + .event_ring = ev_ring, \ > + .dir = DMA_FROM_DEVICE, \ > + .ee_mask = BIT(MHI_EE_SBL), \ > + .pollcfg = 0, \ > + .doorbell = MHI_DB_BRST_DISABLE, \ > + .lpm_notify = false, \ > + .offload_channel = false, \ > + .doorbell_mode_switch = false, \ > + } > + > #define MHI_EVENT_CONFIG_DATA(ev_ring, el_count) \ > { \ > .num_elements = el_count, \ > @@ -182,9 +212,52 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = { > .dma_data_width = 32 > }; > > +static const struct mhi_channel_config mhi_quectel_em1xx_channels[] = { > + MHI_CHANNEL_CONFIG_UL(0, "NMEA", 32, 0), > + MHI_CHANNEL_CONFIG_DL(1, "NMEA", 32, 0), > + MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), > + MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0), > + MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1), > + MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1), > + MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), > + MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), > + MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), > + MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), > + MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), > + MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), > +}; > + > +static struct mhi_event_config mhi_quectel_em1xx_events[] = { > + MHI_EVENT_CONFIG_CTRL(0, 128), > + MHI_EVENT_CONFIG_DATA(1, 128), > + MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), > + MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101) > +}; > + > +static struct mhi_controller_config modem_quectel_em1xx_config = { > + .max_channels = 128, > + .timeout_ms = 8000, > + .num_channels = ARRAY_SIZE(mhi_quectel_em1xx_channels), > + .ch_cfg = mhi_quectel_em1xx_channels, > + .num_events = ARRAY_SIZE(mhi_quectel_em1xx_events), > + .event_cfg = mhi_quectel_em1xx_events, > +}; > + > +static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = { > + .name = "quectel-em1xx", > + .edl = "quectel/prog_firehose_sdx24.mbn", > + .config = &modem_quectel_em1xx_config, > + .bar_num = MHI_PCI_DEFAULT_BAR_NUM, > + .dma_data_width = 32 > +}; > + > static const struct pci_device_id mhi_pci_id_table[] = { > { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306), > .driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info }, > + { PCI_DEVICE(0x1eac, 0x1001), /* EM120R-GL (sdx24) */ > + .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, > + { PCI_DEVICE(0x1eac, 0x1002), /* EM160R-GL (sdx24) */ > + .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, > { } > }; > MODULE_DEVICE_TABLE(pci, mhi_pci_id_table); > -- > 2.7.4 > ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v3 1/2] mhi: pci_generic: Parametrable element count for events 2021-02-16 17:52 [PATCH v3 1/2] mhi: pci_generic: Parametrable element count for events Loic Poulain 2021-02-16 17:52 ` [PATCH v3 2/2] mhi: pci_generic: Introduce quectel EM1XXGR-L support Loic Poulain @ 2021-02-24 9:32 ` Manivannan Sadhasivam 1 sibling, 0 replies; 4+ messages in thread From: Manivannan Sadhasivam @ 2021-02-24 9:32 UTC (permalink / raw) To: Loic Poulain Cc: hemantk, linux-arm-msm, carl.yin, mpearson, cchen50, jwjiang, ivan.zhang, naveen.kumar, ivan.mikhanchuk On Tue, Feb 16, 2021 at 06:52:27PM +0100, Loic Poulain wrote: > Not all hardwares need to use the same number of event ring elements. > This change makes this parametrable. > > Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Thanks, Mani > --- > v2: add this change to the series > v3: no change > > drivers/bus/mhi/pci_generic.c | 20 ++++++++++---------- > 1 file changed, 10 insertions(+), 10 deletions(-) > > diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c > index 8187fcf..c58bf96 100644 > --- a/drivers/bus/mhi/pci_generic.c > +++ b/drivers/bus/mhi/pci_generic.c > @@ -71,9 +71,9 @@ struct mhi_pci_dev_info { > .doorbell_mode_switch = false, \ > } > > -#define MHI_EVENT_CONFIG_CTRL(ev_ring) \ > +#define MHI_EVENT_CONFIG_CTRL(ev_ring, el_count) \ > { \ > - .num_elements = 64, \ > + .num_elements = el_count, \ > .irq_moderation_ms = 0, \ > .irq = (ev_ring) + 1, \ > .priority = 1, \ > @@ -114,9 +114,9 @@ struct mhi_pci_dev_info { > .doorbell_mode_switch = true, \ > } > > -#define MHI_EVENT_CONFIG_DATA(ev_ring) \ > +#define MHI_EVENT_CONFIG_DATA(ev_ring, el_count) \ > { \ > - .num_elements = 128, \ > + .num_elements = el_count, \ > .irq_moderation_ms = 5, \ > .irq = (ev_ring) + 1, \ > .priority = 1, \ > @@ -127,9 +127,9 @@ struct mhi_pci_dev_info { > .offload_channel = false, \ > } > > -#define MHI_EVENT_CONFIG_HW_DATA(ev_ring, ch_num) \ > +#define MHI_EVENT_CONFIG_HW_DATA(ev_ring, el_count, ch_num) \ > { \ > - .num_elements = 2048, \ > + .num_elements = el_count, \ > .irq_moderation_ms = 1, \ > .irq = (ev_ring) + 1, \ > .priority = 1, \ > @@ -156,12 +156,12 @@ static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { > > static struct mhi_event_config modem_qcom_v1_mhi_events[] = { > /* first ring is control+data ring */ > - MHI_EVENT_CONFIG_CTRL(0), > + MHI_EVENT_CONFIG_CTRL(0, 64), > /* DIAG dedicated event ring */ > - MHI_EVENT_CONFIG_DATA(1), > + MHI_EVENT_CONFIG_DATA(1, 128), > /* Hardware channels request dedicated hardware event rings */ > - MHI_EVENT_CONFIG_HW_DATA(2, 100), > - MHI_EVENT_CONFIG_HW_DATA(3, 101) > + MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), > + MHI_EVENT_CONFIG_HW_DATA(3, 2048, 101) > }; > > static struct mhi_controller_config modem_qcom_v1_mhiv_config = { > -- > 2.7.4 > ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2021-02-24 9:35 UTC | newest] Thread overview: 4+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2021-02-16 17:52 [PATCH v3 1/2] mhi: pci_generic: Parametrable element count for events Loic Poulain 2021-02-16 17:52 ` [PATCH v3 2/2] mhi: pci_generic: Introduce quectel EM1XXGR-L support Loic Poulain 2021-02-24 9:34 ` Manivannan Sadhasivam 2021-02-24 9:32 ` [PATCH v3 1/2] mhi: pci_generic: Parametrable element count for events Manivannan Sadhasivam
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