* [PATCH v4 00/28] cpu: Introduce SysemuCPUOps structure, remove watchpoints from usermode
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Thomas Huth, Cornelia Huck, Richard Henderson,
Laurent Vivier, Philippe Mathieu-Daudé, qemu-s390x, qemu-arm,
qemu-ppc, Claudio Fontana, Paolo Bonzini, Alex Bennée
Hi,
This series is inspired on Claudio TCG work.
Instead of separate TCG from other accelerators, here we
separate sysemu operations (system VS user).
Patches 1-6 are generic cleanups.
Patches 7-15 move from CPUClass to SysemuCPUOps
Patch 16 restricts SysemuCPUOps to sysemu
Patches 17-26 remove watchpoint code from user emulation
Patches 27-28 remove USER_ONLY #ifdef'ry from "cpu.h"
Since v3:
- SysemuCPUOps const (Richard)
- added missing xtensa #ifdef'ry
- added missing aa64/sve #ifdef'ry
- added Laurent R-b
Since v2:
- fixed lm32/unicore32
- remove USER_ONLY ifdef'ry from "cpu.h" (Claudio)
Since v1:
- Name 'sysemu' (Claudio)
- change each field progressively (Richard)
$ git backport-diff -u v3
Key:
[----] : patches are identical
[####] : number of functional differences between upstream/downstream patch
[down] : patch is downstream-only
The flags [FC] indicate (F)unctional and (C)ontextual differences, respective=
ly
001/28:[----] [--] 'target: Set CPUClass::vmsd instead of DeviceClass::vmsd'
002/28:[----] [--] 'cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from=
_attrs'
003/28:[----] [--] 'cpu: Introduce cpu_virtio_is_big_endian()'
004/28:[----] [--] 'cpu: Directly use cpu_write_elf*() fallback handlers in p=
lace'
005/28:[----] [--] 'cpu: Directly use get_paging_enabled() fallback handlers =
in place'
006/28:[----] [--] 'cpu: Directly use get_memory_mapping() fallback handlers =
in place'
007/28:[0044] [FC] 'cpu: Introduce SysemuCPUOps structure'
008/28:[----] [-C] 'cpu: Move CPUClass::vmsd to SysemuCPUOps'
009/28:[----] [-C] 'cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps'
010/28:[----] [-C] 'cpu: Move CPUClass::get_crash_info to SysemuCPUOps'
011/28:[----] [-C] 'cpu: Move CPUClass::write_elf* to SysemuCPUOps'
012/28:[----] [-C] 'cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps'
013/28:[----] [-C] 'cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps'
014/28:[----] [-C] 'cpu: Move CPUClass::get_memory_mapping to SysemuCPUOps'
015/28:[----] [-C] 'cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps'
016/28:[----] [--] 'cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c'
017/28:[----] [--] 'linux-user: Remove dead code'
018/28:[----] [--] 'gdbstub: Remove watchpoint dead code in gdbserver_fork()'
019/28:[----] [--] 'target/arm/internals: Fix code style for checkpatch.pl'
020/28:[----] [--] 'target/arm: Move code blocks around'
021/28:[----] [--] 'target/arm: Refactor some function bodies'
022/28:[0012] [FC] 'target/arm: Restrict watchpoint code to system emulation'
023/28:[----] [--] 'target/i386: Restrict watchpoint code to system emulation'
024/28:[down] 'target/xtensa: Restrict watchpoint code to system emulation'
025/28:[----] [--] 'accel/tcg/cpu-exec: Restrict watchpoint code to system em=
ulation'
026/28:[----] [--] 'cpu: Remove watchpoint stubs for user emulation'
027/28:[----] [--] 'cpu: Fix code style for checkpatch.pl'
028/28:[----] [--] 'cpu: Move sysemu specific declarations to 'sysemu-cpu-ops=
.h''
Regards,
Phil.
Philippe Mathieu-Daud=C3=A9 (28):
target: Set CPUClass::vmsd instead of DeviceClass::vmsd
cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs
cpu: Introduce cpu_virtio_is_big_endian()
cpu: Directly use cpu_write_elf*() fallback handlers in place
cpu: Directly use get_paging_enabled() fallback handlers in place
cpu: Directly use get_memory_mapping() fallback handlers in place
cpu: Introduce SysemuCPUOps structure
cpu: Move CPUClass::vmsd to SysemuCPUOps
cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps
cpu: Move CPUClass::get_crash_info to SysemuCPUOps
cpu: Move CPUClass::write_elf* to SysemuCPUOps
cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps
cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps
cpu: Move CPUClass::get_memory_mapping to SysemuCPUOps
cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps
cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c
linux-user: Remove dead code
gdbstub: Remove watchpoint dead code in gdbserver_fork()
target/arm/internals: Fix code style for checkpatch.pl
target/arm: Move code blocks around
target/arm: Refactor some function bodies
target/arm: Restrict watchpoint code to system emulation
target/i386: Restrict watchpoint code to system emulation
target/xtensa: Restrict watchpoint code to system emulation
accel/tcg/cpu-exec: Restrict watchpoint code to system emulation
cpu: Remove watchpoint stubs for user emulation
cpu: Fix code style for checkpatch.pl
cpu: Move sysemu specific declarations to 'sysemu-cpu-ops.h'
include/hw/core/cpu.h | 258 +------------------------------
include/hw/core/sysemu-cpu-ops.h | 244 +++++++++++++++++++++++++++++
target/alpha/cpu.h | 3 +
target/arm/cpu.h | 3 +
target/arm/internals.h | 34 ++--
target/avr/cpu.h | 1 +
target/cris/cpu.h | 3 +
target/hexagon/cpu.h | 3 +
target/hppa/cpu.h | 3 +
target/i386/cpu.h | 3 +
target/lm32/cpu.h | 3 +
target/m68k/cpu.h | 3 +
target/microblaze/cpu.h | 1 +
target/mips/cpu.h | 3 +
target/moxie/cpu.h | 3 +
target/nios2/cpu.h | 1 +
target/openrisc/cpu.h | 3 +
target/ppc/cpu.h | 3 +
target/riscv/cpu.h | 3 +
target/rx/cpu.h | 1 +
target/s390x/cpu.h | 3 +
target/sh4/cpu.h | 3 +
target/sparc/cpu.h | 3 +
target/tilegx/cpu.h | 3 +
target/tricore/cpu.h | 3 +
target/unicore32/cpu.h | 3 +
target/xtensa/cpu.h | 3 +
accel/tcg/cpu-exec.c | 5 +-
cpu.c | 19 ++-
gdbstub.c | 2 +-
hw/core/cpu.c | 113 ++++++++------
hw/virtio/virtio.c | 4 +-
linux-user/main.c | 5 -
softmmu/physmem.c | 1 +
target/alpha/cpu.c | 10 +-
target/arm/cpu.c | 22 ++-
target/arm/debug_helper.c | 102 ++++++------
target/arm/helper.c | 9 +-
target/arm/sve_helper.c | 12 ++
target/avr/cpu.c | 8 +-
target/cris/cpu.c | 10 +-
target/hppa/cpu.c | 10 +-
target/i386/cpu.c | 31 ++--
target/lm32/cpu.c | 10 +-
target/m68k/cpu.c | 10 +-
target/microblaze/cpu.c | 10 +-
target/mips/cpu.c | 10 +-
target/moxie/cpu.c | 10 +-
target/nios2/cpu.c | 15 +-
target/openrisc/cpu.c | 10 +-
target/riscv/cpu.c | 12 +-
target/rx/cpu.c | 16 +-
target/s390x/cpu.c | 14 +-
target/sh4/cpu.c | 10 +-
target/sparc/cpu.c | 10 +-
target/tricore/cpu.c | 13 +-
target/unicore32/cpu.c | 8 +-
target/xtensa/cpu.c | 10 +-
target/xtensa/helper.c | 4 +
target/ppc/translate_init.c.inc | 20 +--
60 files changed, 702 insertions(+), 453 deletions(-)
create mode 100644 include/hw/core/sysemu-cpu-ops.h
--=20
2.26.2
^ permalink raw reply [flat|nested] 79+ messages in thread
* [PATCH v4 01/28] target: Set CPUClass::vmsd instead of DeviceClass::vmsd
2021-03-03 21:46 ` Philippe Mathieu-Daudé
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Claudio Fontana, qemu-arm, Peter Maydell, Paolo Bonzini,
Richard Henderson, qemu-s390x, Thomas Huth, qemu-ppc,
Laurent Vivier, Cornelia Huck, Alex Bennée,
Philippe Mathieu-Daudé, Edgar E. Iglesias, Stafford Horne,
Yoshinori Sato, Guan Xuetao, Max Filippov
The cpu model is the single device available in user-mode.
Since we want to restrict some fields to user-mode emulation,
we prefer to set the vmsd field of CPUClass, rather than the
DeviceClass one.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/alpha/cpu.c | 2 +-
target/cris/cpu.c | 2 +-
target/hppa/cpu.c | 2 +-
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/openrisc/cpu.c | 2 +-
target/sh4/cpu.c | 2 +-
target/unicore32/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
9 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 27192b62e22..faabffe0796 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -237,7 +237,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = alpha_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
- dc->vmsd = &vmstate_alpha_cpu;
+ cc->vmsd = &vmstate_alpha_cpu;
#endif
cc->disas_set_info = alpha_cpu_disas_set_info;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index ed983380fca..29a865b75d2 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -293,7 +293,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = cris_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
- dc->vmsd = &vmstate_cris_cpu;
+ cc->vmsd = &vmstate_cris_cpu;
#endif
cc->gdb_num_core_regs = 49;
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index d8fad52d1fe..4f142de6e45 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -162,7 +162,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = hppa_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug;
- dc->vmsd = &vmstate_hppa_cpu;
+ cc->vmsd = &vmstate_hppa_cpu;
#endif
cc->disas_set_info = hppa_cpu_disas_set_info;
cc->gdb_num_core_regs = 128;
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 37d2ed9dc79..c98fb1e33be 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -533,7 +533,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_write_register = m68k_cpu_gdb_write_register;
#if defined(CONFIG_SOFTMMU)
cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
- dc->vmsd = &vmstate_m68k_cpu;
+ cc->vmsd = &vmstate_m68k_cpu;
#endif
cc->disas_set_info = m68k_cpu_disas_set_info;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 433ba202037..335dfdc734e 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -387,7 +387,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug;
- dc->vmsd = &vmstate_mb_cpu;
+ cc->vmsd = &vmstate_mb_cpu;
#endif
device_class_set_props(dc, mb_properties);
cc->gdb_num_core_regs = 32 + 27;
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 2c64842f46b..79d246d1930 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -204,7 +204,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = openrisc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
- dc->vmsd = &vmstate_openrisc_cpu;
+ cc->vmsd = &vmstate_openrisc_cpu;
#endif
cc->gdb_num_core_regs = 32 + 3;
cc->disas_set_info = openrisc_disas_set_info;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index ac65c88f1f8..bd44de53729 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -262,7 +262,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_num_core_regs = 59;
- dc->vmsd = &vmstate_sh_cpu;
+ cc->vmsd = &vmstate_sh_cpu;
cc->tcg_ops = &superh_tcg_ops;
}
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index 0258884f845..12894ffac6a 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -146,7 +146,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = uc32_cpu_dump_state;
cc->set_pc = uc32_cpu_set_pc;
cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
- dc->vmsd = &vmstate_uc32_cpu;
+ cc->vmsd = &vmstate_uc32_cpu;
cc->tcg_ops = &uc32_tcg_ops;
}
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index e2b2c7a71c1..6bedd5b97b8 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -218,7 +218,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
#endif
cc->disas_set_info = xtensa_cpu_disas_set_info;
- dc->vmsd = &vmstate_xtensa_cpu;
+ cc->vmsd = &vmstate_xtensa_cpu;
cc->tcg_ops = &xtensa_tcg_ops;
}
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread* [PATCH v4 01/28] target: Set CPUClass::vmsd instead of DeviceClass::vmsd
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Thomas Huth, Yoshinori Sato, Cornelia Huck,
Richard Henderson, Laurent Vivier, Philippe Mathieu-Daudé,
Max Filippov, qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana,
Edgar E. Iglesias, Paolo Bonzini, Stafford Horne, Guan Xuetao,
Alex Bennée
The cpu model is the single device available in user-mode.
Since we want to restrict some fields to user-mode emulation,
we prefer to set the vmsd field of CPUClass, rather than the
DeviceClass one.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/alpha/cpu.c | 2 +-
target/cris/cpu.c | 2 +-
target/hppa/cpu.c | 2 +-
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/openrisc/cpu.c | 2 +-
target/sh4/cpu.c | 2 +-
target/unicore32/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
9 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 27192b62e22..faabffe0796 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -237,7 +237,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = alpha_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
- dc->vmsd = &vmstate_alpha_cpu;
+ cc->vmsd = &vmstate_alpha_cpu;
#endif
cc->disas_set_info = alpha_cpu_disas_set_info;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index ed983380fca..29a865b75d2 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -293,7 +293,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = cris_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
- dc->vmsd = &vmstate_cris_cpu;
+ cc->vmsd = &vmstate_cris_cpu;
#endif
cc->gdb_num_core_regs = 49;
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index d8fad52d1fe..4f142de6e45 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -162,7 +162,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = hppa_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug;
- dc->vmsd = &vmstate_hppa_cpu;
+ cc->vmsd = &vmstate_hppa_cpu;
#endif
cc->disas_set_info = hppa_cpu_disas_set_info;
cc->gdb_num_core_regs = 128;
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 37d2ed9dc79..c98fb1e33be 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -533,7 +533,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_write_register = m68k_cpu_gdb_write_register;
#if defined(CONFIG_SOFTMMU)
cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
- dc->vmsd = &vmstate_m68k_cpu;
+ cc->vmsd = &vmstate_m68k_cpu;
#endif
cc->disas_set_info = m68k_cpu_disas_set_info;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 433ba202037..335dfdc734e 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -387,7 +387,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug;
- dc->vmsd = &vmstate_mb_cpu;
+ cc->vmsd = &vmstate_mb_cpu;
#endif
device_class_set_props(dc, mb_properties);
cc->gdb_num_core_regs = 32 + 27;
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 2c64842f46b..79d246d1930 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -204,7 +204,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = openrisc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
- dc->vmsd = &vmstate_openrisc_cpu;
+ cc->vmsd = &vmstate_openrisc_cpu;
#endif
cc->gdb_num_core_regs = 32 + 3;
cc->disas_set_info = openrisc_disas_set_info;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index ac65c88f1f8..bd44de53729 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -262,7 +262,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_num_core_regs = 59;
- dc->vmsd = &vmstate_sh_cpu;
+ cc->vmsd = &vmstate_sh_cpu;
cc->tcg_ops = &superh_tcg_ops;
}
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index 0258884f845..12894ffac6a 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -146,7 +146,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = uc32_cpu_dump_state;
cc->set_pc = uc32_cpu_set_pc;
cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
- dc->vmsd = &vmstate_uc32_cpu;
+ cc->vmsd = &vmstate_uc32_cpu;
cc->tcg_ops = &uc32_tcg_ops;
}
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index e2b2c7a71c1..6bedd5b97b8 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -218,7 +218,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
#endif
cc->disas_set_info = xtensa_cpu_disas_set_info;
- dc->vmsd = &vmstate_xtensa_cpu;
+ cc->vmsd = &vmstate_xtensa_cpu;
cc->tcg_ops = &xtensa_tcg_ops;
}
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v4 02/28] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs
2021-03-03 21:46 ` Philippe Mathieu-Daudé
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Claudio Fontana, qemu-arm, Peter Maydell, Paolo Bonzini,
Richard Henderson, qemu-s390x, Thomas Huth, qemu-ppc,
Laurent Vivier, Cornelia Huck, Alex Bennée,
Philippe Mathieu-Daudé, Eduardo Habkost, Marcel Apfelbaum
To be able to later extract the cpu_get_phys_page_debug() and
cpu_asidx_from_attrs() handlers from CPUClass, un-inline them
from "hw/core/cpu.h".
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 33 ++++-----------------------------
hw/core/cpu.c | 32 ++++++++++++++++++++++++++++++++
2 files changed, 36 insertions(+), 29 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index c005d3dc2d8..2d43f78819f 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -578,18 +578,8 @@ void cpu_dump_statistics(CPUState *cpu, int flags);
*
* Returns: Corresponding physical page address or -1 if no page found.
*/
-static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
- MemTxAttrs *attrs)
-{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- if (cc->get_phys_page_attrs_debug) {
- return cc->get_phys_page_attrs_debug(cpu, addr, attrs);
- }
- /* Fallback for CPUs which don't implement the _attrs_ hook */
- *attrs = MEMTXATTRS_UNSPECIFIED;
- return cc->get_phys_page_debug(cpu, addr);
-}
+hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
+ MemTxAttrs *attrs);
/**
* cpu_get_phys_page_debug:
@@ -601,12 +591,7 @@ static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
*
* Returns: Corresponding physical page address or -1 if no page found.
*/
-static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
-{
- MemTxAttrs attrs = {};
-
- return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs);
-}
+hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
/** cpu_asidx_from_attrs:
* @cpu: CPU
@@ -615,17 +600,7 @@ static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
* Returns the address space index specifying the CPU AddressSpace
* to use for a memory access with the given transaction attributes.
*/
-static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
-{
- CPUClass *cc = CPU_GET_CLASS(cpu);
- int ret = 0;
-
- if (cc->asidx_from_attrs) {
- ret = cc->asidx_from_attrs(cpu, attrs);
- assert(ret < cpu->num_ases && ret >= 0);
- }
- return ret;
-}
+int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs);
#endif /* CONFIG_USER_ONLY */
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 00330ba07de..4dce35f832f 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -94,6 +94,38 @@ static void cpu_common_get_memory_mapping(CPUState *cpu,
error_setg(errp, "Obtaining memory mappings is unsupported on this CPU.");
}
+hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
+ MemTxAttrs *attrs)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (cc->get_phys_page_attrs_debug) {
+ return cc->get_phys_page_attrs_debug(cpu, addr, attrs);
+ }
+ /* Fallback for CPUs which don't implement the _attrs_ hook */
+ *attrs = MEMTXATTRS_UNSPECIFIED;
+ return cc->get_phys_page_debug(cpu, addr);
+}
+
+hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
+{
+ MemTxAttrs attrs = {};
+
+ return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs);
+}
+
+int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+ int ret = 0;
+
+ if (cc->asidx_from_attrs) {
+ ret = cc->asidx_from_attrs(cpu, attrs);
+ assert(ret < cpu->num_ases && ret >= 0);
+ }
+ return ret;
+}
+
/* Resetting the IRQ comes from across the code base so we take the
* BQL here if we need to. cpu_interrupt assumes it is held.*/
void cpu_reset_interrupt(CPUState *cpu, int mask)
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread* [PATCH v4 02/28] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Thomas Huth, Eduardo Habkost, Cornelia Huck,
Richard Henderson, Laurent Vivier, Philippe Mathieu-Daudé,
qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana, Paolo Bonzini,
Alex Bennée
To be able to later extract the cpu_get_phys_page_debug() and
cpu_asidx_from_attrs() handlers from CPUClass, un-inline them
from "hw/core/cpu.h".
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 33 ++++-----------------------------
hw/core/cpu.c | 32 ++++++++++++++++++++++++++++++++
2 files changed, 36 insertions(+), 29 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index c005d3dc2d8..2d43f78819f 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -578,18 +578,8 @@ void cpu_dump_statistics(CPUState *cpu, int flags);
*
* Returns: Corresponding physical page address or -1 if no page found.
*/
-static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
- MemTxAttrs *attrs)
-{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- if (cc->get_phys_page_attrs_debug) {
- return cc->get_phys_page_attrs_debug(cpu, addr, attrs);
- }
- /* Fallback for CPUs which don't implement the _attrs_ hook */
- *attrs = MEMTXATTRS_UNSPECIFIED;
- return cc->get_phys_page_debug(cpu, addr);
-}
+hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
+ MemTxAttrs *attrs);
/**
* cpu_get_phys_page_debug:
@@ -601,12 +591,7 @@ static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
*
* Returns: Corresponding physical page address or -1 if no page found.
*/
-static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
-{
- MemTxAttrs attrs = {};
-
- return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs);
-}
+hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
/** cpu_asidx_from_attrs:
* @cpu: CPU
@@ -615,17 +600,7 @@ static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
* Returns the address space index specifying the CPU AddressSpace
* to use for a memory access with the given transaction attributes.
*/
-static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
-{
- CPUClass *cc = CPU_GET_CLASS(cpu);
- int ret = 0;
-
- if (cc->asidx_from_attrs) {
- ret = cc->asidx_from_attrs(cpu, attrs);
- assert(ret < cpu->num_ases && ret >= 0);
- }
- return ret;
-}
+int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs);
#endif /* CONFIG_USER_ONLY */
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 00330ba07de..4dce35f832f 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -94,6 +94,38 @@ static void cpu_common_get_memory_mapping(CPUState *cpu,
error_setg(errp, "Obtaining memory mappings is unsupported on this CPU.");
}
+hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
+ MemTxAttrs *attrs)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (cc->get_phys_page_attrs_debug) {
+ return cc->get_phys_page_attrs_debug(cpu, addr, attrs);
+ }
+ /* Fallback for CPUs which don't implement the _attrs_ hook */
+ *attrs = MEMTXATTRS_UNSPECIFIED;
+ return cc->get_phys_page_debug(cpu, addr);
+}
+
+hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
+{
+ MemTxAttrs attrs = {};
+
+ return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs);
+}
+
+int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+ int ret = 0;
+
+ if (cc->asidx_from_attrs) {
+ ret = cc->asidx_from_attrs(cpu, attrs);
+ assert(ret < cpu->num_ases && ret >= 0);
+ }
+ return ret;
+}
+
/* Resetting the IRQ comes from across the code base so we take the
* BQL here if we need to. cpu_interrupt assumes it is held.*/
void cpu_reset_interrupt(CPUState *cpu, int mask)
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v4 03/28] cpu: Introduce cpu_virtio_is_big_endian()
2021-03-03 21:46 ` Philippe Mathieu-Daudé
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Claudio Fontana, qemu-arm, Peter Maydell, Paolo Bonzini,
Richard Henderson, qemu-s390x, Thomas Huth, qemu-ppc,
Laurent Vivier, Cornelia Huck, Alex Bennée,
Philippe Mathieu-Daudé, Eduardo Habkost, Marcel Apfelbaum,
Michael S. Tsirkin
Introduce the cpu_virtio_is_big_endian() generic helper to avoid
calling CPUClass internal virtio_is_big_endian() one.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 9 +++++++++
hw/core/cpu.c | 8 ++++++--
hw/virtio/virtio.c | 4 +---
3 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 2d43f78819f..b12028c3c03 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -602,6 +602,15 @@ hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
*/
int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs);
+/**
+ * cpu_virtio_is_big_endian:
+ * @cpu: CPU
+
+ * Returns %true if a CPU which supports runtime configurable endianness
+ * is currently big-endian.
+ */
+bool cpu_virtio_is_big_endian(CPUState *cpu);
+
#endif /* CONFIG_USER_ONLY */
/**
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 4dce35f832f..daaff56a79e 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -218,8 +218,13 @@ static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)
return 0;
}
-static bool cpu_common_virtio_is_big_endian(CPUState *cpu)
+bool cpu_virtio_is_big_endian(CPUState *cpu)
{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (cc->virtio_is_big_endian) {
+ return cc->virtio_is_big_endian(cpu);
+ }
return target_words_bigendian();
}
@@ -438,7 +443,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->write_elf64_note = cpu_common_write_elf64_note;
k->gdb_read_register = cpu_common_gdb_read_register;
k->gdb_write_register = cpu_common_gdb_write_register;
- k->virtio_is_big_endian = cpu_common_virtio_is_big_endian;
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
dc->realize = cpu_common_realizefn;
dc->unrealize = cpu_common_unrealizefn;
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index 1fd1917ca0f..fe6a4be99e4 100644
--- a/hw/virtio/virtio.c
+++ b/hw/virtio/virtio.c
@@ -1973,9 +1973,7 @@ static enum virtio_device_endian virtio_default_endian(void)
static enum virtio_device_endian virtio_current_cpu_endian(void)
{
- CPUClass *cc = CPU_GET_CLASS(current_cpu);
-
- if (cc->virtio_is_big_endian(current_cpu)) {
+ if (cpu_virtio_is_big_endian(current_cpu)) {
return VIRTIO_DEVICE_ENDIAN_BIG;
} else {
return VIRTIO_DEVICE_ENDIAN_LITTLE;
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread* [PATCH v4 03/28] cpu: Introduce cpu_virtio_is_big_endian()
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Thomas Huth, Eduardo Habkost, Michael S. Tsirkin,
Cornelia Huck, Richard Henderson, Laurent Vivier,
Philippe Mathieu-Daudé, qemu-s390x, qemu-arm, qemu-ppc,
Claudio Fontana, Paolo Bonzini, Alex Bennée
Introduce the cpu_virtio_is_big_endian() generic helper to avoid
calling CPUClass internal virtio_is_big_endian() one.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 9 +++++++++
hw/core/cpu.c | 8 ++++++--
hw/virtio/virtio.c | 4 +---
3 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 2d43f78819f..b12028c3c03 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -602,6 +602,15 @@ hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
*/
int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs);
+/**
+ * cpu_virtio_is_big_endian:
+ * @cpu: CPU
+
+ * Returns %true if a CPU which supports runtime configurable endianness
+ * is currently big-endian.
+ */
+bool cpu_virtio_is_big_endian(CPUState *cpu);
+
#endif /* CONFIG_USER_ONLY */
/**
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 4dce35f832f..daaff56a79e 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -218,8 +218,13 @@ static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)
return 0;
}
-static bool cpu_common_virtio_is_big_endian(CPUState *cpu)
+bool cpu_virtio_is_big_endian(CPUState *cpu)
{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (cc->virtio_is_big_endian) {
+ return cc->virtio_is_big_endian(cpu);
+ }
return target_words_bigendian();
}
@@ -438,7 +443,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->write_elf64_note = cpu_common_write_elf64_note;
k->gdb_read_register = cpu_common_gdb_read_register;
k->gdb_write_register = cpu_common_gdb_write_register;
- k->virtio_is_big_endian = cpu_common_virtio_is_big_endian;
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
dc->realize = cpu_common_realizefn;
dc->unrealize = cpu_common_unrealizefn;
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index 1fd1917ca0f..fe6a4be99e4 100644
--- a/hw/virtio/virtio.c
+++ b/hw/virtio/virtio.c
@@ -1973,9 +1973,7 @@ static enum virtio_device_endian virtio_default_endian(void)
static enum virtio_device_endian virtio_current_cpu_endian(void)
{
- CPUClass *cc = CPU_GET_CLASS(current_cpu);
-
- if (cc->virtio_is_big_endian(current_cpu)) {
+ if (cpu_virtio_is_big_endian(current_cpu)) {
return VIRTIO_DEVICE_ENDIAN_BIG;
} else {
return VIRTIO_DEVICE_ENDIAN_LITTLE;
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread* Re: [PATCH v4 03/28] cpu: Introduce cpu_virtio_is_big_endian()
2021-03-03 21:46 ` Philippe Mathieu-Daudé
@ 2021-03-03 22:08 ` Michael S. Tsirkin
-1 siblings, 0 replies; 79+ messages in thread
From: Michael S. Tsirkin @ 2021-03-03 22:08 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Claudio Fontana, qemu-arm, Peter Maydell,
Paolo Bonzini, Richard Henderson, qemu-s390x, Thomas Huth,
qemu-ppc, Laurent Vivier, Cornelia Huck, Alex Bennée,
Eduardo Habkost, Marcel Apfelbaum
On Wed, Mar 03, 2021 at 10:46:43PM +0100, Philippe Mathieu-Daudé wrote:
> Introduce the cpu_virtio_is_big_endian() generic helper to avoid
> calling CPUClass internal virtio_is_big_endian() one.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Using virtio in the name here probably because virtio wants this?
That doesn't sound like a good naming strategy, name should
tell us what function does not how it's used.
> ---
> include/hw/core/cpu.h | 9 +++++++++
> hw/core/cpu.c | 8 ++++++--
> hw/virtio/virtio.c | 4 +---
> 3 files changed, 16 insertions(+), 5 deletions(-)
>
> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
> index 2d43f78819f..b12028c3c03 100644
> --- a/include/hw/core/cpu.h
> +++ b/include/hw/core/cpu.h
> @@ -602,6 +602,15 @@ hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
> */
> int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs);
>
> +/**
> + * cpu_virtio_is_big_endian:
> + * @cpu: CPU
> +
> + * Returns %true if a CPU which supports runtime configurable endianness
> + * is currently big-endian.
> + */
> +bool cpu_virtio_is_big_endian(CPUState *cpu);
> +
> #endif /* CONFIG_USER_ONLY */
>
> /**
> diff --git a/hw/core/cpu.c b/hw/core/cpu.c
> index 4dce35f832f..daaff56a79e 100644
> --- a/hw/core/cpu.c
> +++ b/hw/core/cpu.c
> @@ -218,8 +218,13 @@ static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)
> return 0;
> }
>
> -static bool cpu_common_virtio_is_big_endian(CPUState *cpu)
> +bool cpu_virtio_is_big_endian(CPUState *cpu)
> {
> + CPUClass *cc = CPU_GET_CLASS(cpu);
> +
> + if (cc->virtio_is_big_endian) {
> + return cc->virtio_is_big_endian(cpu);
> + }
> return target_words_bigendian();
> }
>
> @@ -438,7 +443,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
> k->write_elf64_note = cpu_common_write_elf64_note;
> k->gdb_read_register = cpu_common_gdb_read_register;
> k->gdb_write_register = cpu_common_gdb_write_register;
> - k->virtio_is_big_endian = cpu_common_virtio_is_big_endian;
> set_bit(DEVICE_CATEGORY_CPU, dc->categories);
> dc->realize = cpu_common_realizefn;
> dc->unrealize = cpu_common_unrealizefn;
> diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
> index 1fd1917ca0f..fe6a4be99e4 100644
> --- a/hw/virtio/virtio.c
> +++ b/hw/virtio/virtio.c
> @@ -1973,9 +1973,7 @@ static enum virtio_device_endian virtio_default_endian(void)
>
> static enum virtio_device_endian virtio_current_cpu_endian(void)
> {
> - CPUClass *cc = CPU_GET_CLASS(current_cpu);
> -
> - if (cc->virtio_is_big_endian(current_cpu)) {
> + if (cpu_virtio_is_big_endian(current_cpu)) {
> return VIRTIO_DEVICE_ENDIAN_BIG;
> } else {
> return VIRTIO_DEVICE_ENDIAN_LITTLE;
> --
> 2.26.2
^ permalink raw reply [flat|nested] 79+ messages in thread* Re: [PATCH v4 03/28] cpu: Introduce cpu_virtio_is_big_endian()
@ 2021-03-03 22:08 ` Michael S. Tsirkin
0 siblings, 0 replies; 79+ messages in thread
From: Michael S. Tsirkin @ 2021-03-03 22:08 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Peter Maydell, Thomas Huth, Eduardo Habkost, Cornelia Huck,
Richard Henderson, qemu-devel, Laurent Vivier, qemu-s390x,
qemu-arm, qemu-ppc, Claudio Fontana, Paolo Bonzini,
Alex Bennée
On Wed, Mar 03, 2021 at 10:46:43PM +0100, Philippe Mathieu-Daudé wrote:
> Introduce the cpu_virtio_is_big_endian() generic helper to avoid
> calling CPUClass internal virtio_is_big_endian() one.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Using virtio in the name here probably because virtio wants this?
That doesn't sound like a good naming strategy, name should
tell us what function does not how it's used.
> ---
> include/hw/core/cpu.h | 9 +++++++++
> hw/core/cpu.c | 8 ++++++--
> hw/virtio/virtio.c | 4 +---
> 3 files changed, 16 insertions(+), 5 deletions(-)
>
> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
> index 2d43f78819f..b12028c3c03 100644
> --- a/include/hw/core/cpu.h
> +++ b/include/hw/core/cpu.h
> @@ -602,6 +602,15 @@ hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
> */
> int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs);
>
> +/**
> + * cpu_virtio_is_big_endian:
> + * @cpu: CPU
> +
> + * Returns %true if a CPU which supports runtime configurable endianness
> + * is currently big-endian.
> + */
> +bool cpu_virtio_is_big_endian(CPUState *cpu);
> +
> #endif /* CONFIG_USER_ONLY */
>
> /**
> diff --git a/hw/core/cpu.c b/hw/core/cpu.c
> index 4dce35f832f..daaff56a79e 100644
> --- a/hw/core/cpu.c
> +++ b/hw/core/cpu.c
> @@ -218,8 +218,13 @@ static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)
> return 0;
> }
>
> -static bool cpu_common_virtio_is_big_endian(CPUState *cpu)
> +bool cpu_virtio_is_big_endian(CPUState *cpu)
> {
> + CPUClass *cc = CPU_GET_CLASS(cpu);
> +
> + if (cc->virtio_is_big_endian) {
> + return cc->virtio_is_big_endian(cpu);
> + }
> return target_words_bigendian();
> }
>
> @@ -438,7 +443,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
> k->write_elf64_note = cpu_common_write_elf64_note;
> k->gdb_read_register = cpu_common_gdb_read_register;
> k->gdb_write_register = cpu_common_gdb_write_register;
> - k->virtio_is_big_endian = cpu_common_virtio_is_big_endian;
> set_bit(DEVICE_CATEGORY_CPU, dc->categories);
> dc->realize = cpu_common_realizefn;
> dc->unrealize = cpu_common_unrealizefn;
> diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
> index 1fd1917ca0f..fe6a4be99e4 100644
> --- a/hw/virtio/virtio.c
> +++ b/hw/virtio/virtio.c
> @@ -1973,9 +1973,7 @@ static enum virtio_device_endian virtio_default_endian(void)
>
> static enum virtio_device_endian virtio_current_cpu_endian(void)
> {
> - CPUClass *cc = CPU_GET_CLASS(current_cpu);
> -
> - if (cc->virtio_is_big_endian(current_cpu)) {
> + if (cpu_virtio_is_big_endian(current_cpu)) {
> return VIRTIO_DEVICE_ENDIAN_BIG;
> } else {
> return VIRTIO_DEVICE_ENDIAN_LITTLE;
> --
> 2.26.2
^ permalink raw reply [flat|nested] 79+ messages in thread* Re: [PATCH v4 03/28] cpu: Introduce cpu_virtio_is_big_endian()
2021-03-03 22:08 ` Michael S. Tsirkin
@ 2021-03-03 22:15 ` Michael S. Tsirkin
-1 siblings, 0 replies; 79+ messages in thread
From: Michael S. Tsirkin @ 2021-03-03 22:15 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Claudio Fontana, qemu-arm, Peter Maydell,
Paolo Bonzini, Richard Henderson, qemu-s390x, Thomas Huth,
qemu-ppc, Laurent Vivier, Cornelia Huck, Alex Bennée,
Eduardo Habkost, Marcel Apfelbaum
On Wed, Mar 03, 2021 at 05:08:36PM -0500, Michael S. Tsirkin wrote:
> On Wed, Mar 03, 2021 at 10:46:43PM +0100, Philippe Mathieu-Daudé wrote:
> > Introduce the cpu_virtio_is_big_endian() generic helper to avoid
> > calling CPUClass internal virtio_is_big_endian() one.
> >
> > Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> Using virtio in the name here probably because virtio wants this?
> That doesn't sound like a good naming strategy, name should
> tell us what function does not how it's used.
On a more concrete proposal, how about using this change
to rename the virtio_is_big_endian field to guest_is_big_endian(),
and put the wrapper somewhere in a virtio header instead?
> > ---
> > include/hw/core/cpu.h | 9 +++++++++
> > hw/core/cpu.c | 8 ++++++--
> > hw/virtio/virtio.c | 4 +---
> > 3 files changed, 16 insertions(+), 5 deletions(-)
> >
> > diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
> > index 2d43f78819f..b12028c3c03 100644
> > --- a/include/hw/core/cpu.h
> > +++ b/include/hw/core/cpu.h
> > @@ -602,6 +602,15 @@ hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
> > */
> > int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs);
> >
> > +/**
> > + * cpu_virtio_is_big_endian:
> > + * @cpu: CPU
> > +
> > + * Returns %true if a CPU which supports runtime configurable endianness
> > + * is currently big-endian.
> > + */
> > +bool cpu_virtio_is_big_endian(CPUState *cpu);
> > +
> > #endif /* CONFIG_USER_ONLY */
> >
> > /**
> > diff --git a/hw/core/cpu.c b/hw/core/cpu.c
> > index 4dce35f832f..daaff56a79e 100644
> > --- a/hw/core/cpu.c
> > +++ b/hw/core/cpu.c
> > @@ -218,8 +218,13 @@ static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)
> > return 0;
> > }
> >
> > -static bool cpu_common_virtio_is_big_endian(CPUState *cpu)
> > +bool cpu_virtio_is_big_endian(CPUState *cpu)
> > {
> > + CPUClass *cc = CPU_GET_CLASS(cpu);
> > +
> > + if (cc->virtio_is_big_endian) {
> > + return cc->virtio_is_big_endian(cpu);
> > + }
> > return target_words_bigendian();
> > }
> >
> > @@ -438,7 +443,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
> > k->write_elf64_note = cpu_common_write_elf64_note;
> > k->gdb_read_register = cpu_common_gdb_read_register;
> > k->gdb_write_register = cpu_common_gdb_write_register;
> > - k->virtio_is_big_endian = cpu_common_virtio_is_big_endian;
> > set_bit(DEVICE_CATEGORY_CPU, dc->categories);
> > dc->realize = cpu_common_realizefn;
> > dc->unrealize = cpu_common_unrealizefn;
> > diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
> > index 1fd1917ca0f..fe6a4be99e4 100644
> > --- a/hw/virtio/virtio.c
> > +++ b/hw/virtio/virtio.c
> > @@ -1973,9 +1973,7 @@ static enum virtio_device_endian virtio_default_endian(void)
> >
> > static enum virtio_device_endian virtio_current_cpu_endian(void)
> > {
> > - CPUClass *cc = CPU_GET_CLASS(current_cpu);
> > -
> > - if (cc->virtio_is_big_endian(current_cpu)) {
> > + if (cpu_virtio_is_big_endian(current_cpu)) {
> > return VIRTIO_DEVICE_ENDIAN_BIG;
> > } else {
> > return VIRTIO_DEVICE_ENDIAN_LITTLE;
> > --
> > 2.26.2
^ permalink raw reply [flat|nested] 79+ messages in thread* Re: [PATCH v4 03/28] cpu: Introduce cpu_virtio_is_big_endian()
@ 2021-03-03 22:15 ` Michael S. Tsirkin
0 siblings, 0 replies; 79+ messages in thread
From: Michael S. Tsirkin @ 2021-03-03 22:15 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Peter Maydell, Thomas Huth, Eduardo Habkost, Cornelia Huck,
Richard Henderson, qemu-devel, Laurent Vivier, qemu-s390x,
qemu-arm, qemu-ppc, Claudio Fontana, Paolo Bonzini,
Alex Bennée
On Wed, Mar 03, 2021 at 05:08:36PM -0500, Michael S. Tsirkin wrote:
> On Wed, Mar 03, 2021 at 10:46:43PM +0100, Philippe Mathieu-Daudé wrote:
> > Introduce the cpu_virtio_is_big_endian() generic helper to avoid
> > calling CPUClass internal virtio_is_big_endian() one.
> >
> > Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> Using virtio in the name here probably because virtio wants this?
> That doesn't sound like a good naming strategy, name should
> tell us what function does not how it's used.
On a more concrete proposal, how about using this change
to rename the virtio_is_big_endian field to guest_is_big_endian(),
and put the wrapper somewhere in a virtio header instead?
> > ---
> > include/hw/core/cpu.h | 9 +++++++++
> > hw/core/cpu.c | 8 ++++++--
> > hw/virtio/virtio.c | 4 +---
> > 3 files changed, 16 insertions(+), 5 deletions(-)
> >
> > diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
> > index 2d43f78819f..b12028c3c03 100644
> > --- a/include/hw/core/cpu.h
> > +++ b/include/hw/core/cpu.h
> > @@ -602,6 +602,15 @@ hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
> > */
> > int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs);
> >
> > +/**
> > + * cpu_virtio_is_big_endian:
> > + * @cpu: CPU
> > +
> > + * Returns %true if a CPU which supports runtime configurable endianness
> > + * is currently big-endian.
> > + */
> > +bool cpu_virtio_is_big_endian(CPUState *cpu);
> > +
> > #endif /* CONFIG_USER_ONLY */
> >
> > /**
> > diff --git a/hw/core/cpu.c b/hw/core/cpu.c
> > index 4dce35f832f..daaff56a79e 100644
> > --- a/hw/core/cpu.c
> > +++ b/hw/core/cpu.c
> > @@ -218,8 +218,13 @@ static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)
> > return 0;
> > }
> >
> > -static bool cpu_common_virtio_is_big_endian(CPUState *cpu)
> > +bool cpu_virtio_is_big_endian(CPUState *cpu)
> > {
> > + CPUClass *cc = CPU_GET_CLASS(cpu);
> > +
> > + if (cc->virtio_is_big_endian) {
> > + return cc->virtio_is_big_endian(cpu);
> > + }
> > return target_words_bigendian();
> > }
> >
> > @@ -438,7 +443,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
> > k->write_elf64_note = cpu_common_write_elf64_note;
> > k->gdb_read_register = cpu_common_gdb_read_register;
> > k->gdb_write_register = cpu_common_gdb_write_register;
> > - k->virtio_is_big_endian = cpu_common_virtio_is_big_endian;
> > set_bit(DEVICE_CATEGORY_CPU, dc->categories);
> > dc->realize = cpu_common_realizefn;
> > dc->unrealize = cpu_common_unrealizefn;
> > diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
> > index 1fd1917ca0f..fe6a4be99e4 100644
> > --- a/hw/virtio/virtio.c
> > +++ b/hw/virtio/virtio.c
> > @@ -1973,9 +1973,7 @@ static enum virtio_device_endian virtio_default_endian(void)
> >
> > static enum virtio_device_endian virtio_current_cpu_endian(void)
> > {
> > - CPUClass *cc = CPU_GET_CLASS(current_cpu);
> > -
> > - if (cc->virtio_is_big_endian(current_cpu)) {
> > + if (cpu_virtio_is_big_endian(current_cpu)) {
> > return VIRTIO_DEVICE_ENDIAN_BIG;
> > } else {
> > return VIRTIO_DEVICE_ENDIAN_LITTLE;
> > --
> > 2.26.2
^ permalink raw reply [flat|nested] 79+ messages in thread* Re: [PATCH v4 03/28] cpu: Introduce cpu_virtio_is_big_endian()
2021-03-03 22:15 ` Michael S. Tsirkin
@ 2021-03-03 22:18 ` Richard Henderson
-1 siblings, 0 replies; 79+ messages in thread
From: Richard Henderson @ 2021-03-03 22:18 UTC (permalink / raw)
To: Michael S. Tsirkin, Philippe Mathieu-Daudé
Cc: qemu-devel, Claudio Fontana, qemu-arm, Peter Maydell,
Paolo Bonzini, qemu-s390x, Thomas Huth, qemu-ppc, Laurent Vivier,
Cornelia Huck, Alex Bennée, Eduardo Habkost,
Marcel Apfelbaum
On 3/3/21 2:15 PM, Michael S. Tsirkin wrote:
> On Wed, Mar 03, 2021 at 05:08:36PM -0500, Michael S. Tsirkin wrote:
>> On Wed, Mar 03, 2021 at 10:46:43PM +0100, Philippe Mathieu-Daudé wrote:
>>> Introduce the cpu_virtio_is_big_endian() generic helper to avoid
>>> calling CPUClass internal virtio_is_big_endian() one.
>>>
>>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>>
>> Using virtio in the name here probably because virtio wants this?
>> That doesn't sound like a good naming strategy, name should
>> tell us what function does not how it's used.
>
> On a more concrete proposal, how about using this change
> to rename the virtio_is_big_endian field to guest_is_big_endian(),
> and put the wrapper somewhere in a virtio header instead?
We already one for normal guest endianness. This one is for when virtio
specifically differs from that.
r~
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v4 03/28] cpu: Introduce cpu_virtio_is_big_endian()
@ 2021-03-03 22:18 ` Richard Henderson
0 siblings, 0 replies; 79+ messages in thread
From: Richard Henderson @ 2021-03-03 22:18 UTC (permalink / raw)
To: Michael S. Tsirkin, Philippe Mathieu-Daudé
Cc: Peter Maydell, Thomas Huth, Eduardo Habkost, Cornelia Huck,
qemu-devel, Laurent Vivier, qemu-s390x, qemu-arm, qemu-ppc,
Claudio Fontana, Paolo Bonzini, Alex Bennée
On 3/3/21 2:15 PM, Michael S. Tsirkin wrote:
> On Wed, Mar 03, 2021 at 05:08:36PM -0500, Michael S. Tsirkin wrote:
>> On Wed, Mar 03, 2021 at 10:46:43PM +0100, Philippe Mathieu-Daudé wrote:
>>> Introduce the cpu_virtio_is_big_endian() generic helper to avoid
>>> calling CPUClass internal virtio_is_big_endian() one.
>>>
>>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>>
>> Using virtio in the name here probably because virtio wants this?
>> That doesn't sound like a good naming strategy, name should
>> tell us what function does not how it's used.
>
> On a more concrete proposal, how about using this change
> to rename the virtio_is_big_endian field to guest_is_big_endian(),
> and put the wrapper somewhere in a virtio header instead?
We already one for normal guest endianness. This one is for when virtio
specifically differs from that.
r~
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v4 03/28] cpu: Introduce cpu_virtio_is_big_endian()
2021-03-03 22:18 ` Richard Henderson
@ 2021-03-03 22:24 ` Richard Henderson
-1 siblings, 0 replies; 79+ messages in thread
From: Richard Henderson @ 2021-03-03 22:24 UTC (permalink / raw)
To: Michael S. Tsirkin, Philippe Mathieu-Daudé
Cc: qemu-devel, Claudio Fontana, qemu-arm, Peter Maydell,
Paolo Bonzini, qemu-s390x, Thomas Huth, qemu-ppc, Laurent Vivier,
Cornelia Huck, Alex Bennée, Eduardo Habkost,
Marcel Apfelbaum
On 3/3/21 2:18 PM, Richard Henderson wrote:
> On 3/3/21 2:15 PM, Michael S. Tsirkin wrote:
>> On Wed, Mar 03, 2021 at 05:08:36PM -0500, Michael S. Tsirkin wrote:
>>> On Wed, Mar 03, 2021 at 10:46:43PM +0100, Philippe Mathieu-Daudé wrote:
>>>> Introduce the cpu_virtio_is_big_endian() generic helper to avoid
>>>> calling CPUClass internal virtio_is_big_endian() one.
>>>>
>>>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>>>
>>> Using virtio in the name here probably because virtio wants this?
>>> That doesn't sound like a good naming strategy, name should
>>> tell us what function does not how it's used.
>>
>> On a more concrete proposal, how about using this change
>> to rename the virtio_is_big_endian field to guest_is_big_endian(),
>> and put the wrapper somewhere in a virtio header instead?
>
> We already one for normal guest endianness. This one is for when virtio
> specifically differs from that.
Hmph. I remembered incorrectly. I thought we had a bit of ppc weirdness in
which endianness was reversed for virtio, but no.
I'm ok with the renaming.
r~
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v4 03/28] cpu: Introduce cpu_virtio_is_big_endian()
@ 2021-03-03 22:24 ` Richard Henderson
0 siblings, 0 replies; 79+ messages in thread
From: Richard Henderson @ 2021-03-03 22:24 UTC (permalink / raw)
To: Michael S. Tsirkin, Philippe Mathieu-Daudé
Cc: Peter Maydell, Thomas Huth, Eduardo Habkost, Cornelia Huck,
qemu-devel, Laurent Vivier, qemu-s390x, qemu-arm, qemu-ppc,
Claudio Fontana, Paolo Bonzini, Alex Bennée
On 3/3/21 2:18 PM, Richard Henderson wrote:
> On 3/3/21 2:15 PM, Michael S. Tsirkin wrote:
>> On Wed, Mar 03, 2021 at 05:08:36PM -0500, Michael S. Tsirkin wrote:
>>> On Wed, Mar 03, 2021 at 10:46:43PM +0100, Philippe Mathieu-Daudé wrote:
>>>> Introduce the cpu_virtio_is_big_endian() generic helper to avoid
>>>> calling CPUClass internal virtio_is_big_endian() one.
>>>>
>>>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>>>
>>> Using virtio in the name here probably because virtio wants this?
>>> That doesn't sound like a good naming strategy, name should
>>> tell us what function does not how it's used.
>>
>> On a more concrete proposal, how about using this change
>> to rename the virtio_is_big_endian field to guest_is_big_endian(),
>> and put the wrapper somewhere in a virtio header instead?
>
> We already one for normal guest endianness. This one is for when virtio
> specifically differs from that.
Hmph. I remembered incorrectly. I thought we had a bit of ppc weirdness in
which endianness was reversed for virtio, but no.
I'm ok with the renaming.
r~
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v4 03/28] cpu: Introduce cpu_virtio_is_big_endian()
2021-03-03 22:08 ` Michael S. Tsirkin
@ 2021-03-04 7:51 ` Greg Kurz
-1 siblings, 0 replies; 79+ messages in thread
From: Greg Kurz @ 2021-03-04 7:51 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: Philippe Mathieu-Daudé, Peter Maydell, Thomas Huth,
Eduardo Habkost, Cornelia Huck, Richard Henderson, qemu-devel,
Laurent Vivier, qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana,
Paolo Bonzini, Alex Bennée
On Wed, 3 Mar 2021 17:08:32 -0500
"Michael S. Tsirkin" <mst@redhat.com> wrote:
> On Wed, Mar 03, 2021 at 10:46:43PM +0100, Philippe Mathieu-Daudé wrote:
> > Introduce the cpu_virtio_is_big_endian() generic helper to avoid
> > calling CPUClass internal virtio_is_big_endian() one.
> >
> > Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> Using virtio in the name here probably because virtio wants this?
> That doesn't sound like a good naming strategy, name should
> tell us what function does not how it's used.
>
I tend to agree but there was a consensus to deliberately put
virtio in the name when this was first introduced, so that
nobody else ever try to use it, as recorded in the commit log.
commit bf7663c4bd8f8f619d6dbb5780025d92ace250a8
Author: Greg Kurz <groug@kaod.org>
Date: Tue Jun 24 19:33:21 2014 +0200
cpu: introduce CPUClass::virtio_is_big_endian()
If we want to support targets that can change endianness (modern PPC and
ARM for the moment), we need to add a per-CPU class method to be called
from the virtio code. The virtio_ prefix in the name is a hint for people
to avoid misusage (aka. anywhere but from the virtio code).
The default behaviour is to return the compile-time default target
endianness.
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Is there something new on this front ? I'm not convinced that anything
but legacy virtio en POWER (or any other target that can change endian
at runtime) needs this. The next step I see for this is_big_endian()
stuff is deprecation and removal. In the meantime, I think we should
keep the virtio wording to prevent additional users for this.
> > ---
> > include/hw/core/cpu.h | 9 +++++++++
> > hw/core/cpu.c | 8 ++++++--
> > hw/virtio/virtio.c | 4 +---
> > 3 files changed, 16 insertions(+), 5 deletions(-)
> >
> > diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
> > index 2d43f78819f..b12028c3c03 100644
> > --- a/include/hw/core/cpu.h
> > +++ b/include/hw/core/cpu.h
> > @@ -602,6 +602,15 @@ hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
> > */
> > int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs);
> >
> > +/**
> > + * cpu_virtio_is_big_endian:
> > + * @cpu: CPU
> > +
> > + * Returns %true if a CPU which supports runtime configurable endianness
> > + * is currently big-endian.
> > + */
> > +bool cpu_virtio_is_big_endian(CPUState *cpu);
> > +
> > #endif /* CONFIG_USER_ONLY */
> >
> > /**
> > diff --git a/hw/core/cpu.c b/hw/core/cpu.c
> > index 4dce35f832f..daaff56a79e 100644
> > --- a/hw/core/cpu.c
> > +++ b/hw/core/cpu.c
> > @@ -218,8 +218,13 @@ static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)
> > return 0;
> > }
> >
> > -static bool cpu_common_virtio_is_big_endian(CPUState *cpu)
> > +bool cpu_virtio_is_big_endian(CPUState *cpu)
> > {
> > + CPUClass *cc = CPU_GET_CLASS(cpu);
> > +
> > + if (cc->virtio_is_big_endian) {
> > + return cc->virtio_is_big_endian(cpu);
> > + }
> > return target_words_bigendian();
> > }
> >
> > @@ -438,7 +443,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
> > k->write_elf64_note = cpu_common_write_elf64_note;
> > k->gdb_read_register = cpu_common_gdb_read_register;
> > k->gdb_write_register = cpu_common_gdb_write_register;
> > - k->virtio_is_big_endian = cpu_common_virtio_is_big_endian;
> > set_bit(DEVICE_CATEGORY_CPU, dc->categories);
> > dc->realize = cpu_common_realizefn;
> > dc->unrealize = cpu_common_unrealizefn;
> > diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
> > index 1fd1917ca0f..fe6a4be99e4 100644
> > --- a/hw/virtio/virtio.c
> > +++ b/hw/virtio/virtio.c
> > @@ -1973,9 +1973,7 @@ static enum virtio_device_endian virtio_default_endian(void)
> >
> > static enum virtio_device_endian virtio_current_cpu_endian(void)
> > {
> > - CPUClass *cc = CPU_GET_CLASS(current_cpu);
> > -
> > - if (cc->virtio_is_big_endian(current_cpu)) {
> > + if (cpu_virtio_is_big_endian(current_cpu)) {
> > return VIRTIO_DEVICE_ENDIAN_BIG;
> > } else {
> > return VIRTIO_DEVICE_ENDIAN_LITTLE;
> > --
> > 2.26.2
>
>
^ permalink raw reply [flat|nested] 79+ messages in thread* Re: [PATCH v4 03/28] cpu: Introduce cpu_virtio_is_big_endian()
@ 2021-03-04 7:51 ` Greg Kurz
0 siblings, 0 replies; 79+ messages in thread
From: Greg Kurz @ 2021-03-04 7:51 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: Peter Maydell, Thomas Huth, Eduardo Habkost, Cornelia Huck,
Richard Henderson, Philippe Mathieu-Daudé, qemu-devel,
qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana, Paolo Bonzini,
Alex Bennée, Laurent Vivier
On Wed, 3 Mar 2021 17:08:32 -0500
"Michael S. Tsirkin" <mst@redhat.com> wrote:
> On Wed, Mar 03, 2021 at 10:46:43PM +0100, Philippe Mathieu-Daudé wrote:
> > Introduce the cpu_virtio_is_big_endian() generic helper to avoid
> > calling CPUClass internal virtio_is_big_endian() one.
> >
> > Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> Using virtio in the name here probably because virtio wants this?
> That doesn't sound like a good naming strategy, name should
> tell us what function does not how it's used.
>
I tend to agree but there was a consensus to deliberately put
virtio in the name when this was first introduced, so that
nobody else ever try to use it, as recorded in the commit log.
commit bf7663c4bd8f8f619d6dbb5780025d92ace250a8
Author: Greg Kurz <groug@kaod.org>
Date: Tue Jun 24 19:33:21 2014 +0200
cpu: introduce CPUClass::virtio_is_big_endian()
If we want to support targets that can change endianness (modern PPC and
ARM for the moment), we need to add a per-CPU class method to be called
from the virtio code. The virtio_ prefix in the name is a hint for people
to avoid misusage (aka. anywhere but from the virtio code).
The default behaviour is to return the compile-time default target
endianness.
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Is there something new on this front ? I'm not convinced that anything
but legacy virtio en POWER (or any other target that can change endian
at runtime) needs this. The next step I see for this is_big_endian()
stuff is deprecation and removal. In the meantime, I think we should
keep the virtio wording to prevent additional users for this.
> > ---
> > include/hw/core/cpu.h | 9 +++++++++
> > hw/core/cpu.c | 8 ++++++--
> > hw/virtio/virtio.c | 4 +---
> > 3 files changed, 16 insertions(+), 5 deletions(-)
> >
> > diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
> > index 2d43f78819f..b12028c3c03 100644
> > --- a/include/hw/core/cpu.h
> > +++ b/include/hw/core/cpu.h
> > @@ -602,6 +602,15 @@ hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
> > */
> > int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs);
> >
> > +/**
> > + * cpu_virtio_is_big_endian:
> > + * @cpu: CPU
> > +
> > + * Returns %true if a CPU which supports runtime configurable endianness
> > + * is currently big-endian.
> > + */
> > +bool cpu_virtio_is_big_endian(CPUState *cpu);
> > +
> > #endif /* CONFIG_USER_ONLY */
> >
> > /**
> > diff --git a/hw/core/cpu.c b/hw/core/cpu.c
> > index 4dce35f832f..daaff56a79e 100644
> > --- a/hw/core/cpu.c
> > +++ b/hw/core/cpu.c
> > @@ -218,8 +218,13 @@ static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)
> > return 0;
> > }
> >
> > -static bool cpu_common_virtio_is_big_endian(CPUState *cpu)
> > +bool cpu_virtio_is_big_endian(CPUState *cpu)
> > {
> > + CPUClass *cc = CPU_GET_CLASS(cpu);
> > +
> > + if (cc->virtio_is_big_endian) {
> > + return cc->virtio_is_big_endian(cpu);
> > + }
> > return target_words_bigendian();
> > }
> >
> > @@ -438,7 +443,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
> > k->write_elf64_note = cpu_common_write_elf64_note;
> > k->gdb_read_register = cpu_common_gdb_read_register;
> > k->gdb_write_register = cpu_common_gdb_write_register;
> > - k->virtio_is_big_endian = cpu_common_virtio_is_big_endian;
> > set_bit(DEVICE_CATEGORY_CPU, dc->categories);
> > dc->realize = cpu_common_realizefn;
> > dc->unrealize = cpu_common_unrealizefn;
> > diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
> > index 1fd1917ca0f..fe6a4be99e4 100644
> > --- a/hw/virtio/virtio.c
> > +++ b/hw/virtio/virtio.c
> > @@ -1973,9 +1973,7 @@ static enum virtio_device_endian virtio_default_endian(void)
> >
> > static enum virtio_device_endian virtio_current_cpu_endian(void)
> > {
> > - CPUClass *cc = CPU_GET_CLASS(current_cpu);
> > -
> > - if (cc->virtio_is_big_endian(current_cpu)) {
> > + if (cpu_virtio_is_big_endian(current_cpu)) {
> > return VIRTIO_DEVICE_ENDIAN_BIG;
> > } else {
> > return VIRTIO_DEVICE_ENDIAN_LITTLE;
> > --
> > 2.26.2
>
>
^ permalink raw reply [flat|nested] 79+ messages in thread* Re: [PATCH v4 03/28] cpu: Introduce cpu_virtio_is_big_endian()
2021-03-04 7:51 ` Greg Kurz
(?)
@ 2021-04-22 10:33 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 10:33 UTC (permalink / raw)
To: Greg Kurz, Michael S. Tsirkin
Cc: Peter Maydell, Thomas Huth, Eduardo Habkost, Cornelia Huck,
Richard Henderson, qemu-devel, Laurent Vivier, qemu-s390x,
qemu-arm, qemu-ppc, Claudio Fontana, Paolo Bonzini
Hi Michael,
On 3/4/21 8:51 AM, Greg Kurz wrote:
> On Wed, 3 Mar 2021 17:08:32 -0500
> "Michael S. Tsirkin" <mst@redhat.com> wrote:
>
>> On Wed, Mar 03, 2021 at 10:46:43PM +0100, Philippe Mathieu-Daudé wrote:
>>> Introduce the cpu_virtio_is_big_endian() generic helper to avoid
>>> calling CPUClass internal virtio_is_big_endian() one.
>>>
>>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>>
>> Using virtio in the name here probably because virtio wants this?
>> That doesn't sound like a good naming strategy, name should
>> tell us what function does not how it's used.
>>
>
> I tend to agree but there was a consensus to deliberately put
> virtio in the name when this was first introduced, so that
> nobody else ever try to use it, as recorded in the commit log.
>
> commit bf7663c4bd8f8f619d6dbb5780025d92ace250a8
> Author: Greg Kurz <groug@kaod.org>
> Date: Tue Jun 24 19:33:21 2014 +0200
>
> cpu: introduce CPUClass::virtio_is_big_endian()
>
> If we want to support targets that can change endianness (modern PPC and
> ARM for the moment), we need to add a per-CPU class method to be called
> from the virtio code. The virtio_ prefix in the name is a hint for people
> to avoid misusage (aka. anywhere but from the virtio code).
>
> The default behaviour is to return the compile-time default target
> endianness.
>
> Suggested-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com>
> Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
>
> Is there something new on this front ? I'm not convinced that anything
> but legacy virtio en POWER (or any other target that can change endian
> at runtime) needs this. The next step I see for this is_big_endian()
> stuff is deprecation and removal. In the meantime, I think we should
> keep the virtio wording to prevent additional users for this.
On 3/3/21 11:15 PM, Michael S. Tsirkin wrote:
> On a more concrete proposal, how about using this change
> to rename the virtio_is_big_endian field to guest_is_big_endian(),
> and put the wrapper somewhere in a virtio header instead?
Due to Greg comment, I'll keep cpu_virtio_is_big_endian() in
the v5 respin. This doesn't seem a real blocker for the rest
of the changeset. We can settle the name and send a patch on
top.
Regards,
Phil.
^ permalink raw reply [flat|nested] 79+ messages in thread
* [PATCH v4 04/28] cpu: Directly use cpu_write_elf*() fallback handlers in place
2021-03-03 21:46 ` Philippe Mathieu-Daudé
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Claudio Fontana, qemu-arm, Peter Maydell, Paolo Bonzini,
Richard Henderson, qemu-s390x, Thomas Huth, qemu-ppc,
Laurent Vivier, Cornelia Huck, Alex Bennée,
Philippe Mathieu-Daudé, Eduardo Habkost, Marcel Apfelbaum
No code directly accesses CPUClass::write_elf*() handlers out
of hw/core/cpu.c (the rest are assignation in target/ code):
$ git grep -F -- '->write_elf'
hw/core/cpu.c:157: return (*cc->write_elf32_qemunote)(f, cpu, opaque);
hw/core/cpu.c:171: return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
hw/core/cpu.c:186: return (*cc->write_elf64_qemunote)(f, cpu, opaque);
hw/core/cpu.c:200: return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
hw/core/cpu.c:440: k->write_elf32_qemunote = cpu_common_write_elf32_qemunote;
hw/core/cpu.c:441: k->write_elf32_note = cpu_common_write_elf32_note;
hw/core/cpu.c:442: k->write_elf64_qemunote = cpu_common_write_elf64_qemunote;
hw/core/cpu.c:443: k->write_elf64_note = cpu_common_write_elf64_note;
target/arm/cpu.c:2304: cc->write_elf64_note = arm_cpu_write_elf64_note;
target/arm/cpu.c:2305: cc->write_elf32_note = arm_cpu_write_elf32_note;
target/i386/cpu.c:7425: cc->write_elf64_note = x86_cpu_write_elf64_note;
target/i386/cpu.c:7426: cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
target/i386/cpu.c:7427: cc->write_elf32_note = x86_cpu_write_elf32_note;
target/i386/cpu.c:7428: cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
target/ppc/translate_init.c.inc:10891: cc->write_elf64_note = ppc64_cpu_write_elf64_note;
target/ppc/translate_init.c.inc:10892: cc->write_elf32_note = ppc32_cpu_write_elf32_note;
target/s390x/cpu.c:522: cc->write_elf64_note = s390_cpu_write_elf64_note;
Check the handler presence in place and remove the common fallback code.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/core/cpu.c | 43 ++++++++++++-------------------------------
1 file changed, 12 insertions(+), 31 deletions(-)
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index daaff56a79e..a9ee2c74ec5 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -154,60 +154,45 @@ int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
+ if (!cc->write_elf32_qemunote) {
+ return 0;
+ }
return (*cc->write_elf32_qemunote)(f, cpu, opaque);
}
-static int cpu_common_write_elf32_qemunote(WriteCoreDumpFunction f,
- CPUState *cpu, void *opaque)
-{
- return 0;
-}
-
int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
int cpuid, void *opaque)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
+ if (!cc->write_elf32_note) {
+ return -1;
+ }
return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
}
-static int cpu_common_write_elf32_note(WriteCoreDumpFunction f,
- CPUState *cpu, int cpuid,
- void *opaque)
-{
- return -1;
-}
-
int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
void *opaque)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
+ if (!cc->write_elf64_qemunote) {
+ return 0;
+ }
return (*cc->write_elf64_qemunote)(f, cpu, opaque);
}
-static int cpu_common_write_elf64_qemunote(WriteCoreDumpFunction f,
- CPUState *cpu, void *opaque)
-{
- return 0;
-}
-
int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
int cpuid, void *opaque)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
+ if (!cc->write_elf64_note) {
+ return -1;
+ }
return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
}
-static int cpu_common_write_elf64_note(WriteCoreDumpFunction f,
- CPUState *cpu, int cpuid,
- void *opaque)
-{
- return -1;
-}
-
-
static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
{
return 0;
@@ -437,10 +422,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->has_work = cpu_common_has_work;
k->get_paging_enabled = cpu_common_get_paging_enabled;
k->get_memory_mapping = cpu_common_get_memory_mapping;
- k->write_elf32_qemunote = cpu_common_write_elf32_qemunote;
- k->write_elf32_note = cpu_common_write_elf32_note;
- k->write_elf64_qemunote = cpu_common_write_elf64_qemunote;
- k->write_elf64_note = cpu_common_write_elf64_note;
k->gdb_read_register = cpu_common_gdb_read_register;
k->gdb_write_register = cpu_common_gdb_write_register;
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread* [PATCH v4 04/28] cpu: Directly use cpu_write_elf*() fallback handlers in place
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Thomas Huth, Eduardo Habkost, Cornelia Huck,
Richard Henderson, Laurent Vivier, Philippe Mathieu-Daudé,
qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana, Paolo Bonzini,
Alex Bennée
No code directly accesses CPUClass::write_elf*() handlers out
of hw/core/cpu.c (the rest are assignation in target/ code):
$ git grep -F -- '->write_elf'
hw/core/cpu.c:157: return (*cc->write_elf32_qemunote)(f, cpu, opaque);
hw/core/cpu.c:171: return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
hw/core/cpu.c:186: return (*cc->write_elf64_qemunote)(f, cpu, opaque);
hw/core/cpu.c:200: return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
hw/core/cpu.c:440: k->write_elf32_qemunote = cpu_common_write_elf32_qemunote;
hw/core/cpu.c:441: k->write_elf32_note = cpu_common_write_elf32_note;
hw/core/cpu.c:442: k->write_elf64_qemunote = cpu_common_write_elf64_qemunote;
hw/core/cpu.c:443: k->write_elf64_note = cpu_common_write_elf64_note;
target/arm/cpu.c:2304: cc->write_elf64_note = arm_cpu_write_elf64_note;
target/arm/cpu.c:2305: cc->write_elf32_note = arm_cpu_write_elf32_note;
target/i386/cpu.c:7425: cc->write_elf64_note = x86_cpu_write_elf64_note;
target/i386/cpu.c:7426: cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
target/i386/cpu.c:7427: cc->write_elf32_note = x86_cpu_write_elf32_note;
target/i386/cpu.c:7428: cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
target/ppc/translate_init.c.inc:10891: cc->write_elf64_note = ppc64_cpu_write_elf64_note;
target/ppc/translate_init.c.inc:10892: cc->write_elf32_note = ppc32_cpu_write_elf32_note;
target/s390x/cpu.c:522: cc->write_elf64_note = s390_cpu_write_elf64_note;
Check the handler presence in place and remove the common fallback code.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/core/cpu.c | 43 ++++++++++++-------------------------------
1 file changed, 12 insertions(+), 31 deletions(-)
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index daaff56a79e..a9ee2c74ec5 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -154,60 +154,45 @@ int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
+ if (!cc->write_elf32_qemunote) {
+ return 0;
+ }
return (*cc->write_elf32_qemunote)(f, cpu, opaque);
}
-static int cpu_common_write_elf32_qemunote(WriteCoreDumpFunction f,
- CPUState *cpu, void *opaque)
-{
- return 0;
-}
-
int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
int cpuid, void *opaque)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
+ if (!cc->write_elf32_note) {
+ return -1;
+ }
return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
}
-static int cpu_common_write_elf32_note(WriteCoreDumpFunction f,
- CPUState *cpu, int cpuid,
- void *opaque)
-{
- return -1;
-}
-
int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
void *opaque)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
+ if (!cc->write_elf64_qemunote) {
+ return 0;
+ }
return (*cc->write_elf64_qemunote)(f, cpu, opaque);
}
-static int cpu_common_write_elf64_qemunote(WriteCoreDumpFunction f,
- CPUState *cpu, void *opaque)
-{
- return 0;
-}
-
int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
int cpuid, void *opaque)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
+ if (!cc->write_elf64_note) {
+ return -1;
+ }
return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
}
-static int cpu_common_write_elf64_note(WriteCoreDumpFunction f,
- CPUState *cpu, int cpuid,
- void *opaque)
-{
- return -1;
-}
-
-
static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
{
return 0;
@@ -437,10 +422,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->has_work = cpu_common_has_work;
k->get_paging_enabled = cpu_common_get_paging_enabled;
k->get_memory_mapping = cpu_common_get_memory_mapping;
- k->write_elf32_qemunote = cpu_common_write_elf32_qemunote;
- k->write_elf32_note = cpu_common_write_elf32_note;
- k->write_elf64_qemunote = cpu_common_write_elf64_qemunote;
- k->write_elf64_note = cpu_common_write_elf64_note;
k->gdb_read_register = cpu_common_gdb_read_register;
k->gdb_write_register = cpu_common_gdb_write_register;
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v4 05/28] cpu: Directly use get_paging_enabled() fallback handlers in place
2021-03-03 21:46 ` Philippe Mathieu-Daudé
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Claudio Fontana, qemu-arm, Peter Maydell, Paolo Bonzini,
Richard Henderson, qemu-s390x, Thomas Huth, qemu-ppc,
Laurent Vivier, Cornelia Huck, Alex Bennée,
Philippe Mathieu-Daudé, Eduardo Habkost, Marcel Apfelbaum
No code uses CPUClass::get_paging_enabled() outside of hw/core/cpu.c:
$ git grep -F -- '->get_paging_enabled'
hw/core/cpu.c:74: return cc->get_paging_enabled(cpu);
hw/core/cpu.c:438: k->get_paging_enabled = cpu_common_get_paging_enabled;
target/i386/cpu.c:7418: cc->get_paging_enabled = x86_cpu_get_paging_enabled;
Check the handler presence in place and remove the common fallback code.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/core/cpu.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index a9ee2c74ec5..1de00bbb474 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -71,11 +71,10 @@ bool cpu_paging_enabled(const CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- return cc->get_paging_enabled(cpu);
-}
+ if (cc->get_paging_enabled) {
+ return cc->get_paging_enabled(cpu);
+ }
-static bool cpu_common_get_paging_enabled(const CPUState *cpu)
-{
return false;
}
@@ -420,7 +419,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->parse_features = cpu_common_parse_features;
k->get_arch_id = cpu_common_get_arch_id;
k->has_work = cpu_common_has_work;
- k->get_paging_enabled = cpu_common_get_paging_enabled;
k->get_memory_mapping = cpu_common_get_memory_mapping;
k->gdb_read_register = cpu_common_gdb_read_register;
k->gdb_write_register = cpu_common_gdb_write_register;
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread* [PATCH v4 05/28] cpu: Directly use get_paging_enabled() fallback handlers in place
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Thomas Huth, Eduardo Habkost, Cornelia Huck,
Richard Henderson, Laurent Vivier, Philippe Mathieu-Daudé,
qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana, Paolo Bonzini,
Alex Bennée
No code uses CPUClass::get_paging_enabled() outside of hw/core/cpu.c:
$ git grep -F -- '->get_paging_enabled'
hw/core/cpu.c:74: return cc->get_paging_enabled(cpu);
hw/core/cpu.c:438: k->get_paging_enabled = cpu_common_get_paging_enabled;
target/i386/cpu.c:7418: cc->get_paging_enabled = x86_cpu_get_paging_enabled;
Check the handler presence in place and remove the common fallback code.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/core/cpu.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index a9ee2c74ec5..1de00bbb474 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -71,11 +71,10 @@ bool cpu_paging_enabled(const CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- return cc->get_paging_enabled(cpu);
-}
+ if (cc->get_paging_enabled) {
+ return cc->get_paging_enabled(cpu);
+ }
-static bool cpu_common_get_paging_enabled(const CPUState *cpu)
-{
return false;
}
@@ -420,7 +419,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->parse_features = cpu_common_parse_features;
k->get_arch_id = cpu_common_get_arch_id;
k->has_work = cpu_common_has_work;
- k->get_paging_enabled = cpu_common_get_paging_enabled;
k->get_memory_mapping = cpu_common_get_memory_mapping;
k->gdb_read_register = cpu_common_gdb_read_register;
k->gdb_write_register = cpu_common_gdb_write_register;
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v4 06/28] cpu: Directly use get_memory_mapping() fallback handlers in place
2021-03-03 21:46 ` Philippe Mathieu-Daudé
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Claudio Fontana, qemu-arm, Peter Maydell, Paolo Bonzini,
Richard Henderson, qemu-s390x, Thomas Huth, qemu-ppc,
Laurent Vivier, Cornelia Huck, Alex Bennée,
Philippe Mathieu-Daudé, Eduardo Habkost, Marcel Apfelbaum
No code uses CPUClass::get_memory_mapping() outside of hw/core/cpu.c:
$ git grep -F -- '->get_memory_mapping'
hw/core/cpu.c:87: cc->get_memory_mapping(cpu, list, errp);
hw/core/cpu.c:439: k->get_memory_mapping = cpu_common_get_memory_mapping;
target/i386/cpu.c:7422: cc->get_memory_mapping = x86_cpu_get_memory_mapping;
Check the handler presence in place and remove the common fallback code.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/core/cpu.c | 11 ++++-------
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 1de00bbb474..5abf8bed2e4 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -83,13 +83,11 @@ void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- cc->get_memory_mapping(cpu, list, errp);
-}
+ if (cc->get_memory_mapping) {
+ cc->get_memory_mapping(cpu, list, errp);
+ return;
+ }
-static void cpu_common_get_memory_mapping(CPUState *cpu,
- MemoryMappingList *list,
- Error **errp)
-{
error_setg(errp, "Obtaining memory mappings is unsupported on this CPU.");
}
@@ -419,7 +417,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->parse_features = cpu_common_parse_features;
k->get_arch_id = cpu_common_get_arch_id;
k->has_work = cpu_common_has_work;
- k->get_memory_mapping = cpu_common_get_memory_mapping;
k->gdb_read_register = cpu_common_gdb_read_register;
k->gdb_write_register = cpu_common_gdb_write_register;
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread* [PATCH v4 06/28] cpu: Directly use get_memory_mapping() fallback handlers in place
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Thomas Huth, Eduardo Habkost, Cornelia Huck,
Richard Henderson, Laurent Vivier, Philippe Mathieu-Daudé,
qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana, Paolo Bonzini,
Alex Bennée
No code uses CPUClass::get_memory_mapping() outside of hw/core/cpu.c:
$ git grep -F -- '->get_memory_mapping'
hw/core/cpu.c:87: cc->get_memory_mapping(cpu, list, errp);
hw/core/cpu.c:439: k->get_memory_mapping = cpu_common_get_memory_mapping;
target/i386/cpu.c:7422: cc->get_memory_mapping = x86_cpu_get_memory_mapping;
Check the handler presence in place and remove the common fallback code.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/core/cpu.c | 11 ++++-------
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 1de00bbb474..5abf8bed2e4 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -83,13 +83,11 @@ void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- cc->get_memory_mapping(cpu, list, errp);
-}
+ if (cc->get_memory_mapping) {
+ cc->get_memory_mapping(cpu, list, errp);
+ return;
+ }
-static void cpu_common_get_memory_mapping(CPUState *cpu,
- MemoryMappingList *list,
- Error **errp)
-{
error_setg(errp, "Obtaining memory mappings is unsupported on this CPU.");
}
@@ -419,7 +417,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->parse_features = cpu_common_parse_features;
k->get_arch_id = cpu_common_get_arch_id;
k->has_work = cpu_common_has_work;
- k->get_memory_mapping = cpu_common_get_memory_mapping;
k->gdb_read_register = cpu_common_gdb_read_register;
k->gdb_write_register = cpu_common_gdb_write_register;
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v4 07/28] cpu: Introduce SysemuCPUOps structure
2021-03-03 21:46 ` Philippe Mathieu-Daudé
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Claudio Fontana, qemu-arm, Peter Maydell, Paolo Bonzini,
Richard Henderson, qemu-s390x, Thomas Huth, qemu-ppc,
Laurent Vivier, Cornelia Huck, Alex Bennée,
Philippe Mathieu-Daudé, Eduardo Habkost, Marcel Apfelbaum,
Michael Rolnik, Sarah Harris, Edgar E. Iglesias, Michael Walle,
Aurelien Jarno, Jiaxun Yang, Aleksandar Rikalo, Anthony Green,
Chris Wulff, Marek Vasut, Stafford Horne, David Gibson, Greg Kurz,
Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, Yoshinori Sato, David Hildenbrand,
Mark Cave-Ayland, Artyom Tarasenko, Guan Xuetao, Max Filippov,
open list:RISC-V TCG CPUs
Introduce a structure to hold handler specific to sysemu.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 5 +++++
include/hw/core/sysemu-cpu-ops.h | 21 +++++++++++++++++++++
target/alpha/cpu.c | 6 ++++++
target/arm/cpu.c | 6 ++++++
target/avr/cpu.c | 4 ++++
target/cris/cpu.c | 6 ++++++
target/hppa/cpu.c | 6 ++++++
target/i386/cpu.c | 6 ++++++
target/lm32/cpu.c | 6 ++++++
target/m68k/cpu.c | 6 ++++++
target/microblaze/cpu.c | 6 ++++++
target/mips/cpu.c | 6 ++++++
target/moxie/cpu.c | 4 ++++
target/nios2/cpu.c | 6 ++++++
target/openrisc/cpu.c | 6 ++++++
target/riscv/cpu.c | 6 ++++++
target/rx/cpu.c | 8 ++++++++
target/s390x/cpu.c | 6 ++++++
target/sh4/cpu.c | 6 ++++++
target/sparc/cpu.c | 6 ++++++
target/tricore/cpu.c | 4 ++++
target/unicore32/cpu.c | 4 ++++
target/xtensa/cpu.c | 6 ++++++
target/ppc/translate_init.c.inc | 6 ++++++
24 files changed, 152 insertions(+)
create mode 100644 include/hw/core/sysemu-cpu-ops.h
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index b12028c3c03..3c26471d0fa 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -80,6 +80,8 @@ struct TCGCPUOps;
/* see accel-cpu.h */
struct AccelCPUClass;
+#include "hw/core/sysemu-cpu-ops.h"
+
/**
* CPUClass:
* @class_by_name: Callback to map -cpu command line model name to an
@@ -190,6 +192,9 @@ struct CPUClass {
bool gdb_stop_before_watchpoint;
struct AccelCPUClass *accel_cpu;
+ /* when system emulation is not available, this pointer is NULL */
+ const struct SysemuCPUOps *sysemu_ops;
+
/* when TCG is not available, this pointer is NULL */
struct TCGCPUOps *tcg_ops;
};
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
new file mode 100644
index 00000000000..e54a08ea25e
--- /dev/null
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -0,0 +1,21 @@
+/*
+ * CPU operations specific to system emulation
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef SYSEMU_CPU_OPS_H
+#define SYSEMU_CPU_OPS_H
+
+#include "hw/core/cpu.h"
+
+/*
+ * struct SysemuCPUOps: System operations specific to a CPU class
+ */
+typedef struct SysemuCPUOps {
+} SysemuCPUOps;
+
+#endif /* SYSEMU_CPU_OPS_H */
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index faabffe0796..663b1a4fc4e 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -206,6 +206,11 @@ static void alpha_cpu_initfn(Object *obj)
#endif
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps alpha_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps alpha_tcg_ops = {
@@ -238,6 +243,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_alpha_cpu;
+ cc->sysemu_ops = &alpha_sysemu_ops;
#endif
cc->disas_set_info = alpha_cpu_disas_set_info;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index b8bc89e71fc..1fe3c4ab273 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2260,6 +2260,11 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
return g_strdup("arm");
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps arm_sysemu_ops = {
+};
+#endif
+
#ifdef CONFIG_TCG
static struct TCGCPUOps arm_tcg_ops = {
.initialize = arm_translate_init,
@@ -2303,6 +2308,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
cc->write_elf64_note = arm_cpu_write_elf64_note;
cc->write_elf32_note = arm_cpu_write_elf32_note;
+ cc->sysemu_ops = &arm_sysemu_ops;
#endif
cc->gdb_num_core_regs = 26;
cc->gdb_core_xml_file = "arm-core.xml";
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 0f4596932ba..78ef4473c50 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -184,6 +184,9 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
qemu_fprintf(f, "\n");
}
+static const struct SysemuCPUOps avr_sysemu_ops = {
+};
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps avr_tcg_ops = {
@@ -214,6 +217,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
cc->vmsd = &vms_avr_cpu;
+ cc->sysemu_ops = &avr_sysemu_ops;
cc->disas_set_info = avr_cpu_disas_set_info;
cc->gdb_read_register = avr_cpu_gdb_read_register;
cc->gdb_write_register = avr_cpu_gdb_write_register;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index 29a865b75d2..2e447bbf8bc 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -193,6 +193,11 @@ static void cris_cpu_initfn(Object *obj)
#endif
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps cris_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps crisv10_tcg_ops = {
@@ -294,6 +299,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_cris_cpu;
+ cc->sysemu_ops = &cris_sysemu_ops;
#endif
cc->gdb_num_core_regs = 49;
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 4f142de6e45..4bc4fdbf105 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -131,6 +131,11 @@ static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
return object_class_by_name(TYPE_HPPA_CPU);
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps hppa_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps hppa_tcg_ops = {
@@ -163,6 +168,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_hppa_cpu;
+ cc->sysemu_ops = &hppa_sysemu_ops;
#endif
cc->disas_set_info = hppa_cpu_disas_set_info;
cc->gdb_num_core_regs = 128;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 50008431c35..d9ed1972eeb 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7386,6 +7386,11 @@ static Property x86_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST()
};
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps i386_sysemu_ops = {
+};
+#endif
+
static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
{
X86CPUClass *xcc = X86_CPU_CLASS(oc);
@@ -7427,6 +7432,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->write_elf32_note = x86_cpu_write_elf32_note;
cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
cc->vmsd = &vmstate_x86_cpu;
+ cc->sysemu_ops = &i386_sysemu_ops;
#endif /* !CONFIG_USER_ONLY */
cc->gdb_arch_name = x86_gdb_arch_name;
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index c23d72874c0..15935ae7ceb 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -210,6 +210,11 @@ static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model)
return oc;
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps lm32_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps lm32_tcg_ops = {
@@ -242,6 +247,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_lm32_cpu;
+ cc->sysemu_ops = &lm32_sysemu_ops;
#endif
cc->gdb_num_core_regs = 32 + 7;
cc->gdb_stop_before_watchpoint = true;
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index c98fb1e33be..caa606303f7 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -502,6 +502,11 @@ static const VMStateDescription vmstate_m68k_cpu = {
};
#endif
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps m68k_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps m68k_tcg_ops = {
@@ -534,6 +539,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
#if defined(CONFIG_SOFTMMU)
cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_m68k_cpu;
+ cc->sysemu_ops = &m68k_sysemu_ops;
#endif
cc->disas_set_info = m68k_cpu_disas_set_info;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 335dfdc734e..99c3def0ce6 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -352,6 +352,11 @@ static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
return object_class_by_name(TYPE_MICROBLAZE_CPU);
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps mb_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps mb_tcg_ops = {
@@ -388,6 +393,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug;
cc->vmsd = &vmstate_mb_cpu;
+ cc->sysemu_ops = &mb_sysemu_ops;
#endif
device_class_set_props(dc, mb_properties);
cc->gdb_num_core_regs = 32 + 27;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index bf70c77295f..c8edc1f6ffa 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -680,6 +680,11 @@ static Property mips_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST()
};
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps mips_sysemu_ops = {
+};
+#endif
+
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
/*
@@ -721,6 +726,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_mips_cpu;
+ cc->sysemu_ops = &mips_sysemu_ops;
#endif
cc->disas_set_info = mips_cpu_disas_set_info;
cc->gdb_num_core_regs = 73;
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index 83bec34d36c..2cd631a7304 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -94,6 +94,9 @@ static ObjectClass *moxie_cpu_class_by_name(const char *cpu_model)
return oc;
}
+static const struct SysemuCPUOps moxie_sysemu_ops = {
+};
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps moxie_tcg_ops = {
@@ -125,6 +128,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
cc->vmsd = &vmstate_moxie_cpu;
#endif
cc->disas_set_info = moxie_cpu_disas_set_info;
+ cc->sysemu_ops = &moxie_sysemu_ops;
cc->tcg_ops = &moxie_tcg_ops;
}
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index e9c9fc3a389..296ccc0ed3c 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -207,6 +207,11 @@ static Property nios2_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps nios2_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps nios2_tcg_ops = {
@@ -238,6 +243,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
cc->disas_set_info = nios2_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = nios2_cpu_get_phys_page_debug;
+ cc->sysemu_ops = &nios2_sysemu_ops;
#endif
cc->gdb_read_register = nios2_cpu_gdb_read_register;
cc->gdb_write_register = nios2_cpu_gdb_write_register;
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 79d246d1930..7819413eeb3 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -174,6 +174,11 @@ static void openrisc_any_initfn(Object *obj)
| (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps openrisc_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps openrisc_tcg_ops = {
@@ -205,6 +210,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_openrisc_cpu;
+ cc->sysemu_ops = &openrisc_sysemu_ops;
#endif
cc->gdb_num_core_regs = 32 + 3;
cc->disas_set_info = openrisc_disas_set_info;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 16f1a342388..5e7efcf3feb 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -580,6 +580,11 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
return NULL;
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps riscv_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps riscv_tcg_ops = {
@@ -624,6 +629,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
/* For now, mark unmigratable: */
cc->vmsd = &vmstate_riscv_cpu;
+ cc->sysemu_ops = &riscv_sysemu_ops;
#endif
cc->gdb_arch_name = riscv_gdb_arch_name;
cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 7ac6618b26b..bbee1cb913f 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -173,6 +173,11 @@ static void rx_cpu_init(Object *obj)
qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2);
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps rx_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps rx_tcg_ops = {
@@ -202,6 +207,9 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
cc->dump_state = rx_cpu_dump_state;
cc->set_pc = rx_cpu_set_pc;
+#ifndef CONFIG_USER_ONLY
+ cc->sysemu_ops = &rx_sysemu_ops;
+#endif
cc->gdb_read_register = rx_cpu_gdb_read_register;
cc->gdb_write_register = rx_cpu_gdb_write_register;
cc->get_phys_page_debug = rx_cpu_get_phys_page_debug;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index d35eb39a1bb..36085035d1f 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -477,6 +477,11 @@ static void s390_cpu_reset_full(DeviceState *dev)
return s390_cpu_reset(s, S390_CPU_RESET_CLEAR);
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps s390_sysemu_ops = {
+};
+#endif
+
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
@@ -520,6 +525,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->vmsd = &vmstate_s390_cpu;
cc->get_crash_info = s390_cpu_get_crash_info;
cc->write_elf64_note = s390_cpu_write_elf64_note;
+ cc->sysemu_ops = &s390_sysemu_ops;
#endif
cc->disas_set_info = s390_cpu_disas_set_info;
cc->gdb_num_core_regs = S390_NUM_CORE_REGS;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index bd44de53729..c3cdb08e0b2 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -223,6 +223,11 @@ static const VMStateDescription vmstate_sh_cpu = {
.unmigratable = 1,
};
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps sh4_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps superh_tcg_ops = {
@@ -257,6 +262,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = superh_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
+ cc->sysemu_ops = &sh4_sysemu_ops;
#endif
cc->disas_set_info = superh_cpu_disas_set_info;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index aece2c7dc83..a5dde9f7dd9 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -848,6 +848,11 @@ static Property sparc_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST()
};
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps sparc_sysemu_ops = {
+};
+#endif
+
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
@@ -890,6 +895,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_sparc_cpu;
+ cc->sysemu_ops = &sparc_sysemu_ops;
#endif
cc->disas_set_info = cpu_sparc_disas_set_info;
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 0b1e139bcba..8865fa18fce 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -142,6 +142,9 @@ static void tc27x_initfn(Object *obj)
set_feature(&cpu->env, TRICORE_FEATURE_161);
}
+static const struct SysemuCPUOps tricore_sysemu_ops = {
+};
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps tricore_tcg_ops = {
@@ -171,6 +174,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
cc->dump_state = tricore_cpu_dump_state;
cc->set_pc = tricore_cpu_set_pc;
cc->get_phys_page_debug = tricore_cpu_get_phys_page_debug;
+ cc->sysemu_ops = &tricore_sysemu_ops;
cc->tcg_ops = &tricore_tcg_ops;
}
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index 12894ffac6a..1c89168f172 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -120,6 +120,9 @@ static const VMStateDescription vmstate_uc32_cpu = {
.unmigratable = 1,
};
+static const struct SysemuCPUOps uc32_sysemu_ops = {
+};
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps uc32_tcg_ops = {
@@ -147,6 +150,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = uc32_cpu_set_pc;
cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_uc32_cpu;
+ cc->sysemu_ops = &uc32_sysemu_ops;
cc->tcg_ops = &uc32_tcg_ops;
}
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 6bedd5b97b8..28ad2a44878 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -181,6 +181,11 @@ static const VMStateDescription vmstate_xtensa_cpu = {
.unmigratable = 1,
};
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps xtensa_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps xtensa_tcg_ops = {
@@ -215,6 +220,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = xtensa_cpu_gdb_write_register;
cc->gdb_stop_before_watchpoint = true;
#ifndef CONFIG_USER_ONLY
+ cc->sysemu_ops = &xtensa_sysemu_ops;
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
#endif
cc->disas_set_info = xtensa_cpu_disas_set_info;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index e7324e85cdb..6d50af8c67b 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10843,6 +10843,11 @@ static Property ppc_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps ppc_sysemu_ops = {
+};
+#endif
+
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
@@ -10886,6 +10891,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_ppc_cpu;
+ cc->sysemu_ops = &ppc_sysemu_ops;
#endif
#if defined(CONFIG_SOFTMMU)
cc->write_elf64_note = ppc64_cpu_write_elf64_note;
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread* [PATCH v4 07/28] cpu: Introduce SysemuCPUOps structure
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Sarah Harris, Chris Wulff, Sagar Karandikar,
David Hildenbrand, Anthony Green, Mark Cave-Ayland,
Aleksandar Rikalo, Philippe Mathieu-Daudé, Max Filippov,
Alistair Francis, Edgar E. Iglesias, Guan Xuetao, Marek Vasut,
Yoshinori Sato, Claudio Fontana, Palmer Dabbelt, Artyom Tarasenko,
Thomas Huth, Eduardo Habkost, Richard Henderson, Greg Kurz,
qemu-s390x, qemu-arm, Michael Rolnik, Stafford Horne,
Alex Bennée, David Gibson, open list:RISC-V TCG CPUs,
Bastian Koppelmann, Cornelia Huck, Laurent Vivier, Michael Walle,
qemu-ppc, Paolo Bonzini, Aurelien Jarno
Introduce a structure to hold handler specific to sysemu.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 5 +++++
include/hw/core/sysemu-cpu-ops.h | 21 +++++++++++++++++++++
target/alpha/cpu.c | 6 ++++++
target/arm/cpu.c | 6 ++++++
target/avr/cpu.c | 4 ++++
target/cris/cpu.c | 6 ++++++
target/hppa/cpu.c | 6 ++++++
target/i386/cpu.c | 6 ++++++
target/lm32/cpu.c | 6 ++++++
target/m68k/cpu.c | 6 ++++++
target/microblaze/cpu.c | 6 ++++++
target/mips/cpu.c | 6 ++++++
target/moxie/cpu.c | 4 ++++
target/nios2/cpu.c | 6 ++++++
target/openrisc/cpu.c | 6 ++++++
target/riscv/cpu.c | 6 ++++++
target/rx/cpu.c | 8 ++++++++
target/s390x/cpu.c | 6 ++++++
target/sh4/cpu.c | 6 ++++++
target/sparc/cpu.c | 6 ++++++
target/tricore/cpu.c | 4 ++++
target/unicore32/cpu.c | 4 ++++
target/xtensa/cpu.c | 6 ++++++
target/ppc/translate_init.c.inc | 6 ++++++
24 files changed, 152 insertions(+)
create mode 100644 include/hw/core/sysemu-cpu-ops.h
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index b12028c3c03..3c26471d0fa 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -80,6 +80,8 @@ struct TCGCPUOps;
/* see accel-cpu.h */
struct AccelCPUClass;
+#include "hw/core/sysemu-cpu-ops.h"
+
/**
* CPUClass:
* @class_by_name: Callback to map -cpu command line model name to an
@@ -190,6 +192,9 @@ struct CPUClass {
bool gdb_stop_before_watchpoint;
struct AccelCPUClass *accel_cpu;
+ /* when system emulation is not available, this pointer is NULL */
+ const struct SysemuCPUOps *sysemu_ops;
+
/* when TCG is not available, this pointer is NULL */
struct TCGCPUOps *tcg_ops;
};
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
new file mode 100644
index 00000000000..e54a08ea25e
--- /dev/null
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -0,0 +1,21 @@
+/*
+ * CPU operations specific to system emulation
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef SYSEMU_CPU_OPS_H
+#define SYSEMU_CPU_OPS_H
+
+#include "hw/core/cpu.h"
+
+/*
+ * struct SysemuCPUOps: System operations specific to a CPU class
+ */
+typedef struct SysemuCPUOps {
+} SysemuCPUOps;
+
+#endif /* SYSEMU_CPU_OPS_H */
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index faabffe0796..663b1a4fc4e 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -206,6 +206,11 @@ static void alpha_cpu_initfn(Object *obj)
#endif
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps alpha_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps alpha_tcg_ops = {
@@ -238,6 +243,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_alpha_cpu;
+ cc->sysemu_ops = &alpha_sysemu_ops;
#endif
cc->disas_set_info = alpha_cpu_disas_set_info;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index b8bc89e71fc..1fe3c4ab273 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2260,6 +2260,11 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
return g_strdup("arm");
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps arm_sysemu_ops = {
+};
+#endif
+
#ifdef CONFIG_TCG
static struct TCGCPUOps arm_tcg_ops = {
.initialize = arm_translate_init,
@@ -2303,6 +2308,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
cc->write_elf64_note = arm_cpu_write_elf64_note;
cc->write_elf32_note = arm_cpu_write_elf32_note;
+ cc->sysemu_ops = &arm_sysemu_ops;
#endif
cc->gdb_num_core_regs = 26;
cc->gdb_core_xml_file = "arm-core.xml";
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 0f4596932ba..78ef4473c50 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -184,6 +184,9 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
qemu_fprintf(f, "\n");
}
+static const struct SysemuCPUOps avr_sysemu_ops = {
+};
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps avr_tcg_ops = {
@@ -214,6 +217,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
cc->vmsd = &vms_avr_cpu;
+ cc->sysemu_ops = &avr_sysemu_ops;
cc->disas_set_info = avr_cpu_disas_set_info;
cc->gdb_read_register = avr_cpu_gdb_read_register;
cc->gdb_write_register = avr_cpu_gdb_write_register;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index 29a865b75d2..2e447bbf8bc 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -193,6 +193,11 @@ static void cris_cpu_initfn(Object *obj)
#endif
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps cris_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps crisv10_tcg_ops = {
@@ -294,6 +299,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_cris_cpu;
+ cc->sysemu_ops = &cris_sysemu_ops;
#endif
cc->gdb_num_core_regs = 49;
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 4f142de6e45..4bc4fdbf105 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -131,6 +131,11 @@ static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
return object_class_by_name(TYPE_HPPA_CPU);
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps hppa_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps hppa_tcg_ops = {
@@ -163,6 +168,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_hppa_cpu;
+ cc->sysemu_ops = &hppa_sysemu_ops;
#endif
cc->disas_set_info = hppa_cpu_disas_set_info;
cc->gdb_num_core_regs = 128;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 50008431c35..d9ed1972eeb 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7386,6 +7386,11 @@ static Property x86_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST()
};
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps i386_sysemu_ops = {
+};
+#endif
+
static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
{
X86CPUClass *xcc = X86_CPU_CLASS(oc);
@@ -7427,6 +7432,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->write_elf32_note = x86_cpu_write_elf32_note;
cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
cc->vmsd = &vmstate_x86_cpu;
+ cc->sysemu_ops = &i386_sysemu_ops;
#endif /* !CONFIG_USER_ONLY */
cc->gdb_arch_name = x86_gdb_arch_name;
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index c23d72874c0..15935ae7ceb 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -210,6 +210,11 @@ static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model)
return oc;
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps lm32_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps lm32_tcg_ops = {
@@ -242,6 +247,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_lm32_cpu;
+ cc->sysemu_ops = &lm32_sysemu_ops;
#endif
cc->gdb_num_core_regs = 32 + 7;
cc->gdb_stop_before_watchpoint = true;
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index c98fb1e33be..caa606303f7 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -502,6 +502,11 @@ static const VMStateDescription vmstate_m68k_cpu = {
};
#endif
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps m68k_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps m68k_tcg_ops = {
@@ -534,6 +539,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
#if defined(CONFIG_SOFTMMU)
cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_m68k_cpu;
+ cc->sysemu_ops = &m68k_sysemu_ops;
#endif
cc->disas_set_info = m68k_cpu_disas_set_info;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 335dfdc734e..99c3def0ce6 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -352,6 +352,11 @@ static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
return object_class_by_name(TYPE_MICROBLAZE_CPU);
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps mb_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps mb_tcg_ops = {
@@ -388,6 +393,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug;
cc->vmsd = &vmstate_mb_cpu;
+ cc->sysemu_ops = &mb_sysemu_ops;
#endif
device_class_set_props(dc, mb_properties);
cc->gdb_num_core_regs = 32 + 27;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index bf70c77295f..c8edc1f6ffa 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -680,6 +680,11 @@ static Property mips_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST()
};
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps mips_sysemu_ops = {
+};
+#endif
+
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
/*
@@ -721,6 +726,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_mips_cpu;
+ cc->sysemu_ops = &mips_sysemu_ops;
#endif
cc->disas_set_info = mips_cpu_disas_set_info;
cc->gdb_num_core_regs = 73;
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index 83bec34d36c..2cd631a7304 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -94,6 +94,9 @@ static ObjectClass *moxie_cpu_class_by_name(const char *cpu_model)
return oc;
}
+static const struct SysemuCPUOps moxie_sysemu_ops = {
+};
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps moxie_tcg_ops = {
@@ -125,6 +128,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
cc->vmsd = &vmstate_moxie_cpu;
#endif
cc->disas_set_info = moxie_cpu_disas_set_info;
+ cc->sysemu_ops = &moxie_sysemu_ops;
cc->tcg_ops = &moxie_tcg_ops;
}
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index e9c9fc3a389..296ccc0ed3c 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -207,6 +207,11 @@ static Property nios2_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps nios2_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps nios2_tcg_ops = {
@@ -238,6 +243,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
cc->disas_set_info = nios2_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = nios2_cpu_get_phys_page_debug;
+ cc->sysemu_ops = &nios2_sysemu_ops;
#endif
cc->gdb_read_register = nios2_cpu_gdb_read_register;
cc->gdb_write_register = nios2_cpu_gdb_write_register;
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 79d246d1930..7819413eeb3 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -174,6 +174,11 @@ static void openrisc_any_initfn(Object *obj)
| (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps openrisc_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps openrisc_tcg_ops = {
@@ -205,6 +210,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_openrisc_cpu;
+ cc->sysemu_ops = &openrisc_sysemu_ops;
#endif
cc->gdb_num_core_regs = 32 + 3;
cc->disas_set_info = openrisc_disas_set_info;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 16f1a342388..5e7efcf3feb 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -580,6 +580,11 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
return NULL;
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps riscv_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps riscv_tcg_ops = {
@@ -624,6 +629,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
/* For now, mark unmigratable: */
cc->vmsd = &vmstate_riscv_cpu;
+ cc->sysemu_ops = &riscv_sysemu_ops;
#endif
cc->gdb_arch_name = riscv_gdb_arch_name;
cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 7ac6618b26b..bbee1cb913f 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -173,6 +173,11 @@ static void rx_cpu_init(Object *obj)
qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2);
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps rx_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps rx_tcg_ops = {
@@ -202,6 +207,9 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
cc->dump_state = rx_cpu_dump_state;
cc->set_pc = rx_cpu_set_pc;
+#ifndef CONFIG_USER_ONLY
+ cc->sysemu_ops = &rx_sysemu_ops;
+#endif
cc->gdb_read_register = rx_cpu_gdb_read_register;
cc->gdb_write_register = rx_cpu_gdb_write_register;
cc->get_phys_page_debug = rx_cpu_get_phys_page_debug;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index d35eb39a1bb..36085035d1f 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -477,6 +477,11 @@ static void s390_cpu_reset_full(DeviceState *dev)
return s390_cpu_reset(s, S390_CPU_RESET_CLEAR);
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps s390_sysemu_ops = {
+};
+#endif
+
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
@@ -520,6 +525,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->vmsd = &vmstate_s390_cpu;
cc->get_crash_info = s390_cpu_get_crash_info;
cc->write_elf64_note = s390_cpu_write_elf64_note;
+ cc->sysemu_ops = &s390_sysemu_ops;
#endif
cc->disas_set_info = s390_cpu_disas_set_info;
cc->gdb_num_core_regs = S390_NUM_CORE_REGS;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index bd44de53729..c3cdb08e0b2 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -223,6 +223,11 @@ static const VMStateDescription vmstate_sh_cpu = {
.unmigratable = 1,
};
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps sh4_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps superh_tcg_ops = {
@@ -257,6 +262,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = superh_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
+ cc->sysemu_ops = &sh4_sysemu_ops;
#endif
cc->disas_set_info = superh_cpu_disas_set_info;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index aece2c7dc83..a5dde9f7dd9 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -848,6 +848,11 @@ static Property sparc_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST()
};
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps sparc_sysemu_ops = {
+};
+#endif
+
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
@@ -890,6 +895,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_sparc_cpu;
+ cc->sysemu_ops = &sparc_sysemu_ops;
#endif
cc->disas_set_info = cpu_sparc_disas_set_info;
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 0b1e139bcba..8865fa18fce 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -142,6 +142,9 @@ static void tc27x_initfn(Object *obj)
set_feature(&cpu->env, TRICORE_FEATURE_161);
}
+static const struct SysemuCPUOps tricore_sysemu_ops = {
+};
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps tricore_tcg_ops = {
@@ -171,6 +174,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
cc->dump_state = tricore_cpu_dump_state;
cc->set_pc = tricore_cpu_set_pc;
cc->get_phys_page_debug = tricore_cpu_get_phys_page_debug;
+ cc->sysemu_ops = &tricore_sysemu_ops;
cc->tcg_ops = &tricore_tcg_ops;
}
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index 12894ffac6a..1c89168f172 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -120,6 +120,9 @@ static const VMStateDescription vmstate_uc32_cpu = {
.unmigratable = 1,
};
+static const struct SysemuCPUOps uc32_sysemu_ops = {
+};
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps uc32_tcg_ops = {
@@ -147,6 +150,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = uc32_cpu_set_pc;
cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_uc32_cpu;
+ cc->sysemu_ops = &uc32_sysemu_ops;
cc->tcg_ops = &uc32_tcg_ops;
}
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 6bedd5b97b8..28ad2a44878 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -181,6 +181,11 @@ static const VMStateDescription vmstate_xtensa_cpu = {
.unmigratable = 1,
};
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps xtensa_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps xtensa_tcg_ops = {
@@ -215,6 +220,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = xtensa_cpu_gdb_write_register;
cc->gdb_stop_before_watchpoint = true;
#ifndef CONFIG_USER_ONLY
+ cc->sysemu_ops = &xtensa_sysemu_ops;
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
#endif
cc->disas_set_info = xtensa_cpu_disas_set_info;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index e7324e85cdb..6d50af8c67b 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10843,6 +10843,11 @@ static Property ppc_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps ppc_sysemu_ops = {
+};
+#endif
+
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
@@ -10886,6 +10891,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_ppc_cpu;
+ cc->sysemu_ops = &ppc_sysemu_ops;
#endif
#if defined(CONFIG_SOFTMMU)
cc->write_elf64_note = ppc64_cpu_write_elf64_note;
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v4 08/28] cpu: Move CPUClass::vmsd to SysemuCPUOps
2021-03-03 21:46 ` Philippe Mathieu-Daudé
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Claudio Fontana, qemu-arm, Peter Maydell, Paolo Bonzini,
Richard Henderson, qemu-s390x, Thomas Huth, qemu-ppc,
Laurent Vivier, Cornelia Huck, Alex Bennée,
Philippe Mathieu-Daudé, Eduardo Habkost, Marcel Apfelbaum,
Michael Rolnik, Sarah Harris, Edgar E. Iglesias, Michael Walle,
Aurelien Jarno, Jiaxun Yang, Aleksandar Rikalo, Anthony Green,
Chris Wulff, Marek Vasut, Stafford Horne, David Gibson, Greg Kurz,
Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, Yoshinori Sato, David Hildenbrand,
Mark Cave-Ayland, Artyom Tarasenko, Guan Xuetao, Max Filippov,
open list:RISC-V TCG CPUs
Migration is specific to system emulation.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 2 --
include/hw/core/sysemu-cpu-ops.h | 4 ++++
cpu.c | 18 ++++++++----------
target/alpha/cpu.c | 2 +-
target/arm/cpu.c | 2 +-
target/avr/cpu.c | 2 +-
target/cris/cpu.c | 2 +-
target/hppa/cpu.c | 2 +-
target/i386/cpu.c | 2 +-
target/lm32/cpu.c | 2 +-
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 2 +-
target/moxie/cpu.c | 2 +-
target/nios2/cpu.c | 7 +++++++
target/openrisc/cpu.c | 2 +-
target/riscv/cpu.c | 4 ++--
target/rx/cpu.c | 6 ++++++
target/s390x/cpu.c | 2 +-
target/sh4/cpu.c | 4 ++--
target/sparc/cpu.c | 2 +-
target/tricore/cpu.c | 7 +++++++
target/unicore32/cpu.c | 2 +-
target/xtensa/cpu.c | 4 ++--
target/ppc/translate_init.c.inc | 2 +-
25 files changed, 54 insertions(+), 34 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 3c26471d0fa..471c99d9f04 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -124,7 +124,6 @@ struct AccelCPUClass;
* 32-bit VM coredump.
* @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
* note to a 32-bit VM coredump.
- * @vmsd: State description for migration.
* @gdb_num_core_regs: Number of core registers accessible to GDB.
* @gdb_core_xml_file: File name for core registers GDB XML description.
* @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
@@ -179,7 +178,6 @@ struct CPUClass {
int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
void *opaque);
- const VMStateDescription *vmsd;
const char *gdb_core_xml_file;
gchar * (*gdb_arch_name)(CPUState *cpu);
const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index e54a08ea25e..05f19b22070 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,10 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @vmsd: State description for migration.
+ */
+ const VMStateDescription *vmsd;
} SysemuCPUOps;
#endif /* SYSEMU_CPU_OPS_H */
diff --git a/cpu.c b/cpu.c
index bfbe5a66f95..64e17537e21 100644
--- a/cpu.c
+++ b/cpu.c
@@ -126,7 +126,9 @@ const VMStateDescription vmstate_cpu_common = {
void cpu_exec_realizefn(CPUState *cpu, Error **errp)
{
+#ifndef CONFIG_USER_ONLY
CPUClass *cc = CPU_GET_CLASS(cpu);
+#endif
cpu_list_add(cpu);
@@ -137,27 +139,23 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
}
#endif /* CONFIG_TCG */
-#ifdef CONFIG_USER_ONLY
- assert(cc->vmsd == NULL);
-#else
+#ifndef CONFIG_USER_ONLY
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
}
- if (cc->vmsd != NULL) {
- vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
+ if (cc->sysemu_ops->vmsd != NULL) {
+ vmstate_register(NULL, cpu->cpu_index, cc->sysemu_ops->vmsd, cpu);
}
#endif /* CONFIG_USER_ONLY */
}
void cpu_exec_unrealizefn(CPUState *cpu)
{
+#ifndef CONFIG_USER_ONLY
CPUClass *cc = CPU_GET_CLASS(cpu);
-#ifdef CONFIG_USER_ONLY
- assert(cc->vmsd == NULL);
-#else
- if (cc->vmsd != NULL) {
- vmstate_unregister(NULL, cc->vmsd, cpu);
+ if (cc->sysemu_ops->vmsd != NULL) {
+ vmstate_unregister(NULL, cc->sysemu_ops->vmsd, cpu);
}
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 663b1a4fc4e..de8f9c648fa 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -208,6 +208,7 @@ static void alpha_cpu_initfn(Object *obj)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps alpha_sysemu_ops = {
+ .vmsd = &vmstate_alpha_cpu,
};
#endif
@@ -242,7 +243,6 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = alpha_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_alpha_cpu;
cc->sysemu_ops = &alpha_sysemu_ops;
#endif
cc->disas_set_info = alpha_cpu_disas_set_info;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 1fe3c4ab273..403422c6e76 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2262,6 +2262,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps arm_sysemu_ops = {
+ .vmsd = &vmstate_arm_cpu,
};
#endif
@@ -2304,7 +2305,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->asidx_from_attrs = arm_asidx_from_attrs;
- cc->vmsd = &vmstate_arm_cpu;
cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
cc->write_elf64_note = arm_cpu_write_elf64_note;
cc->write_elf32_note = arm_cpu_write_elf32_note;
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 78ef4473c50..20a48bdfbab 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -185,6 +185,7 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
static const struct SysemuCPUOps avr_sysemu_ops = {
+ .vmsd = &vms_avr_cpu,
};
#include "hw/core/tcg-cpu-ops.h"
@@ -216,7 +217,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = avr_cpu_set_pc;
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
- cc->vmsd = &vms_avr_cpu;
cc->sysemu_ops = &avr_sysemu_ops;
cc->disas_set_info = avr_cpu_disas_set_info;
cc->gdb_read_register = avr_cpu_gdb_read_register;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index 2e447bbf8bc..c05707bad2c 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -195,6 +195,7 @@ static void cris_cpu_initfn(Object *obj)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps cris_sysemu_ops = {
+ .vmsd = &vmstate_cris_cpu,
};
#endif
@@ -298,7 +299,6 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = cris_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_cris_cpu;
cc->sysemu_ops = &cris_sysemu_ops;
#endif
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 4bc4fdbf105..110cc8a6d68 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -133,6 +133,7 @@ static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps hppa_sysemu_ops = {
+ .vmsd = &vmstate_hppa_cpu,
};
#endif
@@ -167,7 +168,6 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = hppa_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_hppa_cpu;
cc->sysemu_ops = &hppa_sysemu_ops;
#endif
cc->disas_set_info = hppa_cpu_disas_set_info;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index d9ed1972eeb..b8f056849a7 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7388,6 +7388,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps i386_sysemu_ops = {
+ .vmsd = &vmstate_x86_cpu,
};
#endif
@@ -7431,7 +7432,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
cc->write_elf32_note = x86_cpu_write_elf32_note;
cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
- cc->vmsd = &vmstate_x86_cpu;
cc->sysemu_ops = &i386_sysemu_ops;
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index 15935ae7ceb..4ff54fd9204 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -212,6 +212,7 @@ static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps lm32_sysemu_ops = {
+ .vmsd = &vmstate_lm32_cpu,
};
#endif
@@ -246,7 +247,6 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = lm32_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_lm32_cpu;
cc->sysemu_ops = &lm32_sysemu_ops;
#endif
cc->gdb_num_core_regs = 32 + 7;
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index caa606303f7..e7ddcf2ee28 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -504,6 +504,7 @@ static const VMStateDescription vmstate_m68k_cpu = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps m68k_sysemu_ops = {
+ .vmsd = &vmstate_m68k_cpu,
};
#endif
@@ -538,7 +539,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_write_register = m68k_cpu_gdb_write_register;
#if defined(CONFIG_SOFTMMU)
cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_m68k_cpu;
cc->sysemu_ops = &m68k_sysemu_ops;
#endif
cc->disas_set_info = m68k_cpu_disas_set_info;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 99c3def0ce6..8b86b99c15b 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -354,6 +354,7 @@ static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps mb_sysemu_ops = {
+ .vmsd = &vmstate_mb_cpu,
};
#endif
@@ -392,7 +393,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug;
- cc->vmsd = &vmstate_mb_cpu;
cc->sysemu_ops = &mb_sysemu_ops;
#endif
device_class_set_props(dc, mb_properties);
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index c8edc1f6ffa..ef997bcd67f 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -682,6 +682,7 @@ static Property mips_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps mips_sysemu_ops = {
+ .vmsd = &vmstate_mips_cpu,
};
#endif
@@ -725,7 +726,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_write_register = mips_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_mips_cpu;
cc->sysemu_ops = &mips_sysemu_ops;
#endif
cc->disas_set_info = mips_cpu_disas_set_info;
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index 2cd631a7304..1e87f07ca73 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -95,6 +95,7 @@ static ObjectClass *moxie_cpu_class_by_name(const char *cpu_model)
}
static const struct SysemuCPUOps moxie_sysemu_ops = {
+ .vmsd = &vmstate_moxie_cpu,
};
#include "hw/core/tcg-cpu-ops.h"
@@ -125,7 +126,6 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = moxie_cpu_set_pc;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = moxie_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_moxie_cpu;
#endif
cc->disas_set_info = moxie_cpu_disas_set_info;
cc->sysemu_ops = &moxie_sysemu_ops;
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 296ccc0ed3c..a785f3ea7b6 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -25,6 +25,7 @@
#include "exec/log.h"
#include "exec/gdbstub.h"
#include "hw/qdev-properties.h"
+#include "migration/vmstate.h"
static void nios2_cpu_set_pc(CPUState *cs, vaddr value)
{
@@ -208,7 +209,13 @@ static Property nios2_properties[] = {
};
#ifndef CONFIG_USER_ONLY
+static const VMStateDescription vmstate_nios2_cpu = {
+ .name = "cpu",
+ .unmigratable = 1,
+};
+
static const struct SysemuCPUOps nios2_sysemu_ops = {
+ .vmsd = &vmstate_nios2_cpu,
};
#endif
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 7819413eeb3..2149e9564fa 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -176,6 +176,7 @@ static void openrisc_any_initfn(Object *obj)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps openrisc_sysemu_ops = {
+ .vmsd = &vmstate_openrisc_cpu,
};
#endif
@@ -209,7 +210,6 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = openrisc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_openrisc_cpu;
cc->sysemu_ops = &openrisc_sysemu_ops;
#endif
cc->gdb_num_core_regs = 32 + 3;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5e7efcf3feb..a6b1ff93299 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -582,6 +582,8 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps riscv_sysemu_ops = {
+ /* For now, mark unmigratable: */
+ .vmsd = &vmstate_riscv_cpu,
};
#endif
@@ -627,8 +629,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
- /* For now, mark unmigratable: */
- cc->vmsd = &vmstate_riscv_cpu;
cc->sysemu_ops = &riscv_sysemu_ops;
#endif
cc->gdb_arch_name = riscv_gdb_arch_name;
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index bbee1cb913f..f293f3630d0 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -174,7 +174,13 @@ static void rx_cpu_init(Object *obj)
}
#ifndef CONFIG_USER_ONLY
+static const VMStateDescription vmstate_rx_cpu = {
+ .name = "cpu",
+ .unmigratable = 1,
+};
+
static const struct SysemuCPUOps rx_sysemu_ops = {
+ .vmsd = &vmstate_rx_cpu,
};
#endif
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 36085035d1f..fe908d9bc40 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -479,6 +479,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps s390_sysemu_ops = {
+ .vmsd = &vmstate_s390_cpu,
};
#endif
@@ -522,7 +523,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = s390_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_s390_cpu;
cc->get_crash_info = s390_cpu_get_crash_info;
cc->write_elf64_note = s390_cpu_write_elf64_note;
cc->sysemu_ops = &s390_sysemu_ops;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index c3cdb08e0b2..8c1d0ba53b1 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -218,13 +218,14 @@ static void superh_cpu_initfn(Object *obj)
env->movcal_backup_tail = &(env->movcal_backup);
}
+#ifndef CONFIG_USER_ONLY
static const VMStateDescription vmstate_sh_cpu = {
.name = "cpu",
.unmigratable = 1,
};
-#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps sh4_sysemu_ops = {
+ .vmsd = &vmstate_sh_cpu,
};
#endif
@@ -268,7 +269,6 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_num_core_regs = 59;
- cc->vmsd = &vmstate_sh_cpu;
cc->tcg_ops = &superh_tcg_ops;
}
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index a5dde9f7dd9..f5862e74baf 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -850,6 +850,7 @@ static Property sparc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps sparc_sysemu_ops = {
+ .vmsd = &vmstate_sparc_cpu,
};
#endif
@@ -894,7 +895,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = sparc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_sparc_cpu;
cc->sysemu_ops = &sparc_sysemu_ops;
#endif
cc->disas_set_info = cpu_sparc_disas_set_info;
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 8865fa18fce..9374f8440a0 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -22,6 +22,7 @@
#include "cpu.h"
#include "exec/exec-all.h"
#include "qemu/error-report.h"
+#include "migration/vmstate.h"
static inline void set_feature(CPUTriCoreState *env, int feature)
{
@@ -142,7 +143,13 @@ static void tc27x_initfn(Object *obj)
set_feature(&cpu->env, TRICORE_FEATURE_161);
}
+static const VMStateDescription vmstate_tricore_cpu = {
+ .name = "cpu",
+ .unmigratable = 1,
+};
+
static const struct SysemuCPUOps tricore_sysemu_ops = {
+ .vmsd = &vmstate_tricore_cpu,
};
#include "hw/core/tcg-cpu-ops.h"
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index 1c89168f172..345b6e9e417 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -121,6 +121,7 @@ static const VMStateDescription vmstate_uc32_cpu = {
};
static const struct SysemuCPUOps uc32_sysemu_ops = {
+ .vmsd = &vmstate_uc32_cpu,
};
#include "hw/core/tcg-cpu-ops.h"
@@ -149,7 +150,6 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = uc32_cpu_dump_state;
cc->set_pc = uc32_cpu_set_pc;
cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_uc32_cpu;
cc->sysemu_ops = &uc32_sysemu_ops;
cc->tcg_ops = &uc32_tcg_ops;
}
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 28ad2a44878..fd65246015f 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -176,13 +176,14 @@ static void xtensa_cpu_initfn(Object *obj)
#endif
}
+#ifndef CONFIG_USER_ONLY
static const VMStateDescription vmstate_xtensa_cpu = {
.name = "cpu",
.unmigratable = 1,
};
-#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps xtensa_sysemu_ops = {
+ .vmsd = &vmstate_xtensa_cpu,
};
#endif
@@ -224,7 +225,6 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
#endif
cc->disas_set_info = xtensa_cpu_disas_set_info;
- cc->vmsd = &vmstate_xtensa_cpu;
cc->tcg_ops = &xtensa_tcg_ops;
}
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 6d50af8c67b..819b807097d 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10845,6 +10845,7 @@ static Property ppc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps ppc_sysemu_ops = {
+ .vmsd = &vmstate_ppc_cpu,
};
#endif
@@ -10890,7 +10891,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = ppc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_ppc_cpu;
cc->sysemu_ops = &ppc_sysemu_ops;
#endif
#if defined(CONFIG_SOFTMMU)
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread* [PATCH v4 08/28] cpu: Move CPUClass::vmsd to SysemuCPUOps
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Sarah Harris, Chris Wulff, Sagar Karandikar,
David Hildenbrand, Anthony Green, Mark Cave-Ayland,
Aleksandar Rikalo, Philippe Mathieu-Daudé, Max Filippov,
Alistair Francis, Edgar E. Iglesias, Guan Xuetao, Marek Vasut,
Yoshinori Sato, Claudio Fontana, Palmer Dabbelt, Artyom Tarasenko,
Thomas Huth, Eduardo Habkost, Richard Henderson, Greg Kurz,
qemu-s390x, qemu-arm, Michael Rolnik, Stafford Horne,
Alex Bennée, David Gibson, open list:RISC-V TCG CPUs,
Bastian Koppelmann, Cornelia Huck, Laurent Vivier, Michael Walle,
qemu-ppc, Paolo Bonzini, Aurelien Jarno
Migration is specific to system emulation.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 2 --
include/hw/core/sysemu-cpu-ops.h | 4 ++++
cpu.c | 18 ++++++++----------
target/alpha/cpu.c | 2 +-
target/arm/cpu.c | 2 +-
target/avr/cpu.c | 2 +-
target/cris/cpu.c | 2 +-
target/hppa/cpu.c | 2 +-
target/i386/cpu.c | 2 +-
target/lm32/cpu.c | 2 +-
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 2 +-
target/moxie/cpu.c | 2 +-
target/nios2/cpu.c | 7 +++++++
target/openrisc/cpu.c | 2 +-
target/riscv/cpu.c | 4 ++--
target/rx/cpu.c | 6 ++++++
target/s390x/cpu.c | 2 +-
target/sh4/cpu.c | 4 ++--
target/sparc/cpu.c | 2 +-
target/tricore/cpu.c | 7 +++++++
target/unicore32/cpu.c | 2 +-
target/xtensa/cpu.c | 4 ++--
target/ppc/translate_init.c.inc | 2 +-
25 files changed, 54 insertions(+), 34 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 3c26471d0fa..471c99d9f04 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -124,7 +124,6 @@ struct AccelCPUClass;
* 32-bit VM coredump.
* @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
* note to a 32-bit VM coredump.
- * @vmsd: State description for migration.
* @gdb_num_core_regs: Number of core registers accessible to GDB.
* @gdb_core_xml_file: File name for core registers GDB XML description.
* @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
@@ -179,7 +178,6 @@ struct CPUClass {
int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
void *opaque);
- const VMStateDescription *vmsd;
const char *gdb_core_xml_file;
gchar * (*gdb_arch_name)(CPUState *cpu);
const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index e54a08ea25e..05f19b22070 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,10 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @vmsd: State description for migration.
+ */
+ const VMStateDescription *vmsd;
} SysemuCPUOps;
#endif /* SYSEMU_CPU_OPS_H */
diff --git a/cpu.c b/cpu.c
index bfbe5a66f95..64e17537e21 100644
--- a/cpu.c
+++ b/cpu.c
@@ -126,7 +126,9 @@ const VMStateDescription vmstate_cpu_common = {
void cpu_exec_realizefn(CPUState *cpu, Error **errp)
{
+#ifndef CONFIG_USER_ONLY
CPUClass *cc = CPU_GET_CLASS(cpu);
+#endif
cpu_list_add(cpu);
@@ -137,27 +139,23 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
}
#endif /* CONFIG_TCG */
-#ifdef CONFIG_USER_ONLY
- assert(cc->vmsd == NULL);
-#else
+#ifndef CONFIG_USER_ONLY
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
}
- if (cc->vmsd != NULL) {
- vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
+ if (cc->sysemu_ops->vmsd != NULL) {
+ vmstate_register(NULL, cpu->cpu_index, cc->sysemu_ops->vmsd, cpu);
}
#endif /* CONFIG_USER_ONLY */
}
void cpu_exec_unrealizefn(CPUState *cpu)
{
+#ifndef CONFIG_USER_ONLY
CPUClass *cc = CPU_GET_CLASS(cpu);
-#ifdef CONFIG_USER_ONLY
- assert(cc->vmsd == NULL);
-#else
- if (cc->vmsd != NULL) {
- vmstate_unregister(NULL, cc->vmsd, cpu);
+ if (cc->sysemu_ops->vmsd != NULL) {
+ vmstate_unregister(NULL, cc->sysemu_ops->vmsd, cpu);
}
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 663b1a4fc4e..de8f9c648fa 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -208,6 +208,7 @@ static void alpha_cpu_initfn(Object *obj)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps alpha_sysemu_ops = {
+ .vmsd = &vmstate_alpha_cpu,
};
#endif
@@ -242,7 +243,6 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = alpha_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_alpha_cpu;
cc->sysemu_ops = &alpha_sysemu_ops;
#endif
cc->disas_set_info = alpha_cpu_disas_set_info;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 1fe3c4ab273..403422c6e76 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2262,6 +2262,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps arm_sysemu_ops = {
+ .vmsd = &vmstate_arm_cpu,
};
#endif
@@ -2304,7 +2305,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->asidx_from_attrs = arm_asidx_from_attrs;
- cc->vmsd = &vmstate_arm_cpu;
cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
cc->write_elf64_note = arm_cpu_write_elf64_note;
cc->write_elf32_note = arm_cpu_write_elf32_note;
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 78ef4473c50..20a48bdfbab 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -185,6 +185,7 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
static const struct SysemuCPUOps avr_sysemu_ops = {
+ .vmsd = &vms_avr_cpu,
};
#include "hw/core/tcg-cpu-ops.h"
@@ -216,7 +217,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = avr_cpu_set_pc;
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
- cc->vmsd = &vms_avr_cpu;
cc->sysemu_ops = &avr_sysemu_ops;
cc->disas_set_info = avr_cpu_disas_set_info;
cc->gdb_read_register = avr_cpu_gdb_read_register;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index 2e447bbf8bc..c05707bad2c 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -195,6 +195,7 @@ static void cris_cpu_initfn(Object *obj)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps cris_sysemu_ops = {
+ .vmsd = &vmstate_cris_cpu,
};
#endif
@@ -298,7 +299,6 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = cris_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_cris_cpu;
cc->sysemu_ops = &cris_sysemu_ops;
#endif
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 4bc4fdbf105..110cc8a6d68 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -133,6 +133,7 @@ static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps hppa_sysemu_ops = {
+ .vmsd = &vmstate_hppa_cpu,
};
#endif
@@ -167,7 +168,6 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = hppa_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_hppa_cpu;
cc->sysemu_ops = &hppa_sysemu_ops;
#endif
cc->disas_set_info = hppa_cpu_disas_set_info;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index d9ed1972eeb..b8f056849a7 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7388,6 +7388,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps i386_sysemu_ops = {
+ .vmsd = &vmstate_x86_cpu,
};
#endif
@@ -7431,7 +7432,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
cc->write_elf32_note = x86_cpu_write_elf32_note;
cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
- cc->vmsd = &vmstate_x86_cpu;
cc->sysemu_ops = &i386_sysemu_ops;
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index 15935ae7ceb..4ff54fd9204 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -212,6 +212,7 @@ static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps lm32_sysemu_ops = {
+ .vmsd = &vmstate_lm32_cpu,
};
#endif
@@ -246,7 +247,6 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = lm32_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_lm32_cpu;
cc->sysemu_ops = &lm32_sysemu_ops;
#endif
cc->gdb_num_core_regs = 32 + 7;
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index caa606303f7..e7ddcf2ee28 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -504,6 +504,7 @@ static const VMStateDescription vmstate_m68k_cpu = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps m68k_sysemu_ops = {
+ .vmsd = &vmstate_m68k_cpu,
};
#endif
@@ -538,7 +539,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_write_register = m68k_cpu_gdb_write_register;
#if defined(CONFIG_SOFTMMU)
cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_m68k_cpu;
cc->sysemu_ops = &m68k_sysemu_ops;
#endif
cc->disas_set_info = m68k_cpu_disas_set_info;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 99c3def0ce6..8b86b99c15b 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -354,6 +354,7 @@ static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps mb_sysemu_ops = {
+ .vmsd = &vmstate_mb_cpu,
};
#endif
@@ -392,7 +393,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug;
- cc->vmsd = &vmstate_mb_cpu;
cc->sysemu_ops = &mb_sysemu_ops;
#endif
device_class_set_props(dc, mb_properties);
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index c8edc1f6ffa..ef997bcd67f 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -682,6 +682,7 @@ static Property mips_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps mips_sysemu_ops = {
+ .vmsd = &vmstate_mips_cpu,
};
#endif
@@ -725,7 +726,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_write_register = mips_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_mips_cpu;
cc->sysemu_ops = &mips_sysemu_ops;
#endif
cc->disas_set_info = mips_cpu_disas_set_info;
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index 2cd631a7304..1e87f07ca73 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -95,6 +95,7 @@ static ObjectClass *moxie_cpu_class_by_name(const char *cpu_model)
}
static const struct SysemuCPUOps moxie_sysemu_ops = {
+ .vmsd = &vmstate_moxie_cpu,
};
#include "hw/core/tcg-cpu-ops.h"
@@ -125,7 +126,6 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = moxie_cpu_set_pc;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = moxie_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_moxie_cpu;
#endif
cc->disas_set_info = moxie_cpu_disas_set_info;
cc->sysemu_ops = &moxie_sysemu_ops;
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 296ccc0ed3c..a785f3ea7b6 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -25,6 +25,7 @@
#include "exec/log.h"
#include "exec/gdbstub.h"
#include "hw/qdev-properties.h"
+#include "migration/vmstate.h"
static void nios2_cpu_set_pc(CPUState *cs, vaddr value)
{
@@ -208,7 +209,13 @@ static Property nios2_properties[] = {
};
#ifndef CONFIG_USER_ONLY
+static const VMStateDescription vmstate_nios2_cpu = {
+ .name = "cpu",
+ .unmigratable = 1,
+};
+
static const struct SysemuCPUOps nios2_sysemu_ops = {
+ .vmsd = &vmstate_nios2_cpu,
};
#endif
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 7819413eeb3..2149e9564fa 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -176,6 +176,7 @@ static void openrisc_any_initfn(Object *obj)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps openrisc_sysemu_ops = {
+ .vmsd = &vmstate_openrisc_cpu,
};
#endif
@@ -209,7 +210,6 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = openrisc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_openrisc_cpu;
cc->sysemu_ops = &openrisc_sysemu_ops;
#endif
cc->gdb_num_core_regs = 32 + 3;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5e7efcf3feb..a6b1ff93299 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -582,6 +582,8 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps riscv_sysemu_ops = {
+ /* For now, mark unmigratable: */
+ .vmsd = &vmstate_riscv_cpu,
};
#endif
@@ -627,8 +629,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
- /* For now, mark unmigratable: */
- cc->vmsd = &vmstate_riscv_cpu;
cc->sysemu_ops = &riscv_sysemu_ops;
#endif
cc->gdb_arch_name = riscv_gdb_arch_name;
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index bbee1cb913f..f293f3630d0 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -174,7 +174,13 @@ static void rx_cpu_init(Object *obj)
}
#ifndef CONFIG_USER_ONLY
+static const VMStateDescription vmstate_rx_cpu = {
+ .name = "cpu",
+ .unmigratable = 1,
+};
+
static const struct SysemuCPUOps rx_sysemu_ops = {
+ .vmsd = &vmstate_rx_cpu,
};
#endif
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 36085035d1f..fe908d9bc40 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -479,6 +479,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps s390_sysemu_ops = {
+ .vmsd = &vmstate_s390_cpu,
};
#endif
@@ -522,7 +523,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = s390_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_s390_cpu;
cc->get_crash_info = s390_cpu_get_crash_info;
cc->write_elf64_note = s390_cpu_write_elf64_note;
cc->sysemu_ops = &s390_sysemu_ops;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index c3cdb08e0b2..8c1d0ba53b1 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -218,13 +218,14 @@ static void superh_cpu_initfn(Object *obj)
env->movcal_backup_tail = &(env->movcal_backup);
}
+#ifndef CONFIG_USER_ONLY
static const VMStateDescription vmstate_sh_cpu = {
.name = "cpu",
.unmigratable = 1,
};
-#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps sh4_sysemu_ops = {
+ .vmsd = &vmstate_sh_cpu,
};
#endif
@@ -268,7 +269,6 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_num_core_regs = 59;
- cc->vmsd = &vmstate_sh_cpu;
cc->tcg_ops = &superh_tcg_ops;
}
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index a5dde9f7dd9..f5862e74baf 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -850,6 +850,7 @@ static Property sparc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps sparc_sysemu_ops = {
+ .vmsd = &vmstate_sparc_cpu,
};
#endif
@@ -894,7 +895,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = sparc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_sparc_cpu;
cc->sysemu_ops = &sparc_sysemu_ops;
#endif
cc->disas_set_info = cpu_sparc_disas_set_info;
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 8865fa18fce..9374f8440a0 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -22,6 +22,7 @@
#include "cpu.h"
#include "exec/exec-all.h"
#include "qemu/error-report.h"
+#include "migration/vmstate.h"
static inline void set_feature(CPUTriCoreState *env, int feature)
{
@@ -142,7 +143,13 @@ static void tc27x_initfn(Object *obj)
set_feature(&cpu->env, TRICORE_FEATURE_161);
}
+static const VMStateDescription vmstate_tricore_cpu = {
+ .name = "cpu",
+ .unmigratable = 1,
+};
+
static const struct SysemuCPUOps tricore_sysemu_ops = {
+ .vmsd = &vmstate_tricore_cpu,
};
#include "hw/core/tcg-cpu-ops.h"
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index 1c89168f172..345b6e9e417 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -121,6 +121,7 @@ static const VMStateDescription vmstate_uc32_cpu = {
};
static const struct SysemuCPUOps uc32_sysemu_ops = {
+ .vmsd = &vmstate_uc32_cpu,
};
#include "hw/core/tcg-cpu-ops.h"
@@ -149,7 +150,6 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = uc32_cpu_dump_state;
cc->set_pc = uc32_cpu_set_pc;
cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_uc32_cpu;
cc->sysemu_ops = &uc32_sysemu_ops;
cc->tcg_ops = &uc32_tcg_ops;
}
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 28ad2a44878..fd65246015f 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -176,13 +176,14 @@ static void xtensa_cpu_initfn(Object *obj)
#endif
}
+#ifndef CONFIG_USER_ONLY
static const VMStateDescription vmstate_xtensa_cpu = {
.name = "cpu",
.unmigratable = 1,
};
-#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps xtensa_sysemu_ops = {
+ .vmsd = &vmstate_xtensa_cpu,
};
#endif
@@ -224,7 +225,6 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
#endif
cc->disas_set_info = xtensa_cpu_disas_set_info;
- cc->vmsd = &vmstate_xtensa_cpu;
cc->tcg_ops = &xtensa_tcg_ops;
}
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 6d50af8c67b..819b807097d 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10845,6 +10845,7 @@ static Property ppc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps ppc_sysemu_ops = {
+ .vmsd = &vmstate_ppc_cpu,
};
#endif
@@ -10890,7 +10891,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = ppc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_ppc_cpu;
cc->sysemu_ops = &ppc_sysemu_ops;
#endif
#if defined(CONFIG_SOFTMMU)
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v4 09/28] cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps
2021-03-03 21:46 ` Philippe Mathieu-Daudé
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Claudio Fontana, qemu-arm, Peter Maydell, Paolo Bonzini,
Richard Henderson, qemu-s390x, Thomas Huth, qemu-ppc,
Laurent Vivier, Cornelia Huck, Alex Bennée,
Philippe Mathieu-Daudé, Eduardo Habkost, Marcel Apfelbaum,
David Gibson, Greg Kurz
VirtIO devices are only meaningful with system emulation.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 5 -----
include/hw/core/sysemu-cpu-ops.h | 8 ++++++++
hw/core/cpu.c | 4 ++--
target/arm/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 4 +---
5 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 471c99d9f04..dfb50b60128 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -89,10 +89,6 @@ struct AccelCPUClass;
* @parse_features: Callback to parse command line arguments.
* @reset_dump_flags: #CPUDumpFlags to use for reset logging.
* @has_work: Callback for checking if there is work to do.
- * @virtio_is_big_endian: Callback to return %true if a CPU which supports
- * runtime configurable endianness is currently big-endian. Non-configurable
- * CPUs can use the default implementation of this method. This method should
- * not be used by any callers other than the pre-1.0 virtio devices.
* @memory_rw_debug: Callback for GDB memory access.
* @dump_state: Callback for dumping state.
* @dump_statistics: Callback for dumping statistics.
@@ -151,7 +147,6 @@ struct CPUClass {
int reset_dump_flags;
bool (*has_work)(CPUState *cpu);
- bool (*virtio_is_big_endian)(CPUState *cpu);
int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
uint8_t *buf, int len, bool is_write);
void (*dump_state)(CPUState *cpu, FILE *, int flags);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 05f19b22070..9c3ac4f2280 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,14 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @virtio_is_big_endian: Callback to return %true if a CPU which supports
+ * runtime configurable endianness is currently big-endian.
+ * Non-configurable CPUs can use the default implementation of this method.
+ * This method should not be used by any callers other than the pre-1.0
+ * virtio devices.
+ */
+ bool (*virtio_is_big_endian)(CPUState *cpu);
/**
* @vmsd: State description for migration.
*/
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 5abf8bed2e4..09eaa3fa49f 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -204,8 +204,8 @@ bool cpu_virtio_is_big_endian(CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->virtio_is_big_endian) {
- return cc->virtio_is_big_endian(cpu);
+ if (cc->sysemu_ops->virtio_is_big_endian) {
+ return cc->sysemu_ops->virtio_is_big_endian(cpu);
}
return target_words_bigendian();
}
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 403422c6e76..fa0d4bba590 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2262,6 +2262,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps arm_sysemu_ops = {
+ .virtio_is_big_endian = arm_cpu_virtio_is_big_endian,
.vmsd = &vmstate_arm_cpu,
};
#endif
@@ -2305,7 +2306,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->asidx_from_attrs = arm_asidx_from_attrs;
- cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
cc->write_elf64_note = arm_cpu_write_elf64_note;
cc->write_elf32_note = arm_cpu_write_elf32_note;
cc->sysemu_ops = &arm_sysemu_ops;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 819b807097d..789124debe7 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10845,6 +10845,7 @@ static Property ppc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps ppc_sysemu_ops = {
+ .virtio_is_big_endian = ppc_cpu_is_big_endian,
.vmsd = &vmstate_ppc_cpu,
};
#endif
@@ -10913,9 +10914,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_core_xml_file = "power64-core.xml";
#else
cc->gdb_core_xml_file = "power-core.xml";
-#endif
-#ifndef CONFIG_USER_ONLY
- cc->virtio_is_big_endian = ppc_cpu_is_big_endian;
#endif
cc->disas_set_info = ppc_disas_set_info;
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread* [PATCH v4 09/28] cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Thomas Huth, Eduardo Habkost, Cornelia Huck,
Richard Henderson, Laurent Vivier, Philippe Mathieu-Daudé,
qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana, Paolo Bonzini,
Greg Kurz, Alex Bennée, David Gibson
VirtIO devices are only meaningful with system emulation.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 5 -----
include/hw/core/sysemu-cpu-ops.h | 8 ++++++++
hw/core/cpu.c | 4 ++--
target/arm/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 4 +---
5 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 471c99d9f04..dfb50b60128 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -89,10 +89,6 @@ struct AccelCPUClass;
* @parse_features: Callback to parse command line arguments.
* @reset_dump_flags: #CPUDumpFlags to use for reset logging.
* @has_work: Callback for checking if there is work to do.
- * @virtio_is_big_endian: Callback to return %true if a CPU which supports
- * runtime configurable endianness is currently big-endian. Non-configurable
- * CPUs can use the default implementation of this method. This method should
- * not be used by any callers other than the pre-1.0 virtio devices.
* @memory_rw_debug: Callback for GDB memory access.
* @dump_state: Callback for dumping state.
* @dump_statistics: Callback for dumping statistics.
@@ -151,7 +147,6 @@ struct CPUClass {
int reset_dump_flags;
bool (*has_work)(CPUState *cpu);
- bool (*virtio_is_big_endian)(CPUState *cpu);
int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
uint8_t *buf, int len, bool is_write);
void (*dump_state)(CPUState *cpu, FILE *, int flags);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 05f19b22070..9c3ac4f2280 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,14 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @virtio_is_big_endian: Callback to return %true if a CPU which supports
+ * runtime configurable endianness is currently big-endian.
+ * Non-configurable CPUs can use the default implementation of this method.
+ * This method should not be used by any callers other than the pre-1.0
+ * virtio devices.
+ */
+ bool (*virtio_is_big_endian)(CPUState *cpu);
/**
* @vmsd: State description for migration.
*/
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 5abf8bed2e4..09eaa3fa49f 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -204,8 +204,8 @@ bool cpu_virtio_is_big_endian(CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->virtio_is_big_endian) {
- return cc->virtio_is_big_endian(cpu);
+ if (cc->sysemu_ops->virtio_is_big_endian) {
+ return cc->sysemu_ops->virtio_is_big_endian(cpu);
}
return target_words_bigendian();
}
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 403422c6e76..fa0d4bba590 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2262,6 +2262,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps arm_sysemu_ops = {
+ .virtio_is_big_endian = arm_cpu_virtio_is_big_endian,
.vmsd = &vmstate_arm_cpu,
};
#endif
@@ -2305,7 +2306,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->asidx_from_attrs = arm_asidx_from_attrs;
- cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
cc->write_elf64_note = arm_cpu_write_elf64_note;
cc->write_elf32_note = arm_cpu_write_elf32_note;
cc->sysemu_ops = &arm_sysemu_ops;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 819b807097d..789124debe7 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10845,6 +10845,7 @@ static Property ppc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps ppc_sysemu_ops = {
+ .virtio_is_big_endian = ppc_cpu_is_big_endian,
.vmsd = &vmstate_ppc_cpu,
};
#endif
@@ -10913,9 +10914,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_core_xml_file = "power64-core.xml";
#else
cc->gdb_core_xml_file = "power-core.xml";
-#endif
-#ifndef CONFIG_USER_ONLY
- cc->virtio_is_big_endian = ppc_cpu_is_big_endian;
#endif
cc->disas_set_info = ppc_disas_set_info;
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v4 10/28] cpu: Move CPUClass::get_crash_info to SysemuCPUOps
2021-03-03 21:46 ` Philippe Mathieu-Daudé
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Claudio Fontana, qemu-arm, Peter Maydell, Paolo Bonzini,
Richard Henderson, qemu-s390x, Thomas Huth, qemu-ppc,
Laurent Vivier, Cornelia Huck, Alex Bennée,
Philippe Mathieu-Daudé, Eduardo Habkost, Marcel Apfelbaum,
David Hildenbrand
cpu_get_crash_info() is called on GUEST_PANICKED events,
which only occur in system emulation.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 1 -
include/hw/core/sysemu-cpu-ops.h | 5 +++++
hw/core/cpu.c | 4 ++--
target/i386/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
5 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index dfb50b60128..781cd8fc42b 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -150,7 +150,6 @@ struct CPUClass {
int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
uint8_t *buf, int len, bool is_write);
void (*dump_state)(CPUState *cpu, FILE *, int flags);
- GuestPanicInformation* (*get_crash_info)(CPUState *cpu);
void (*dump_statistics)(CPUState *cpu, int flags);
int64_t (*get_arch_id)(CPUState *cpu);
bool (*get_paging_enabled)(const CPUState *cpu);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 9c3ac4f2280..b9ffca07665 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,11 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @get_crash_info: Callback for reporting guest crash information in
+ * GUEST_PANICKED events.
+ */
+ GuestPanicInformation* (*get_crash_info)(CPUState *cpu);
/**
* @virtio_is_big_endian: Callback to return %true if a CPU which supports
* runtime configurable endianness is currently big-endian.
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 09eaa3fa49f..0aebc18c41f 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -220,8 +220,8 @@ GuestPanicInformation *cpu_get_crash_info(CPUState *cpu)
CPUClass *cc = CPU_GET_CLASS(cpu);
GuestPanicInformation *res = NULL;
- if (cc->get_crash_info) {
- res = cc->get_crash_info(cpu);
+ if (cc->sysemu_ops->get_crash_info) {
+ res = cc->sysemu_ops->get_crash_info(cpu);
}
return res;
}
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index b8f056849a7..362ad56ab68 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7388,6 +7388,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps i386_sysemu_ops = {
+ .get_crash_info = x86_cpu_get_crash_info,
.vmsd = &vmstate_x86_cpu,
};
#endif
@@ -7427,7 +7428,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->asidx_from_attrs = x86_asidx_from_attrs;
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
- cc->get_crash_info = x86_cpu_get_crash_info;
cc->write_elf64_note = x86_cpu_write_elf64_note;
cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
cc->write_elf32_note = x86_cpu_write_elf32_note;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index fe908d9bc40..fdc169bb0ac 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -479,6 +479,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps s390_sysemu_ops = {
+ .get_crash_info = s390_cpu_get_crash_info,
.vmsd = &vmstate_s390_cpu,
};
#endif
@@ -523,7 +524,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = s390_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
- cc->get_crash_info = s390_cpu_get_crash_info;
cc->write_elf64_note = s390_cpu_write_elf64_note;
cc->sysemu_ops = &s390_sysemu_ops;
#endif
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread* [PATCH v4 10/28] cpu: Move CPUClass::get_crash_info to SysemuCPUOps
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Thomas Huth, Eduardo Habkost, David Hildenbrand,
Cornelia Huck, Richard Henderson, Laurent Vivier,
Philippe Mathieu-Daudé, qemu-s390x, qemu-arm, qemu-ppc,
Claudio Fontana, Paolo Bonzini, Alex Bennée
cpu_get_crash_info() is called on GUEST_PANICKED events,
which only occur in system emulation.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 1 -
include/hw/core/sysemu-cpu-ops.h | 5 +++++
hw/core/cpu.c | 4 ++--
target/i386/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
5 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index dfb50b60128..781cd8fc42b 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -150,7 +150,6 @@ struct CPUClass {
int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
uint8_t *buf, int len, bool is_write);
void (*dump_state)(CPUState *cpu, FILE *, int flags);
- GuestPanicInformation* (*get_crash_info)(CPUState *cpu);
void (*dump_statistics)(CPUState *cpu, int flags);
int64_t (*get_arch_id)(CPUState *cpu);
bool (*get_paging_enabled)(const CPUState *cpu);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 9c3ac4f2280..b9ffca07665 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,11 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @get_crash_info: Callback for reporting guest crash information in
+ * GUEST_PANICKED events.
+ */
+ GuestPanicInformation* (*get_crash_info)(CPUState *cpu);
/**
* @virtio_is_big_endian: Callback to return %true if a CPU which supports
* runtime configurable endianness is currently big-endian.
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 09eaa3fa49f..0aebc18c41f 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -220,8 +220,8 @@ GuestPanicInformation *cpu_get_crash_info(CPUState *cpu)
CPUClass *cc = CPU_GET_CLASS(cpu);
GuestPanicInformation *res = NULL;
- if (cc->get_crash_info) {
- res = cc->get_crash_info(cpu);
+ if (cc->sysemu_ops->get_crash_info) {
+ res = cc->sysemu_ops->get_crash_info(cpu);
}
return res;
}
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index b8f056849a7..362ad56ab68 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7388,6 +7388,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps i386_sysemu_ops = {
+ .get_crash_info = x86_cpu_get_crash_info,
.vmsd = &vmstate_x86_cpu,
};
#endif
@@ -7427,7 +7428,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->asidx_from_attrs = x86_asidx_from_attrs;
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
- cc->get_crash_info = x86_cpu_get_crash_info;
cc->write_elf64_note = x86_cpu_write_elf64_note;
cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
cc->write_elf32_note = x86_cpu_write_elf32_note;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index fe908d9bc40..fdc169bb0ac 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -479,6 +479,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps s390_sysemu_ops = {
+ .get_crash_info = s390_cpu_get_crash_info,
.vmsd = &vmstate_s390_cpu,
};
#endif
@@ -523,7 +524,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = s390_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
- cc->get_crash_info = s390_cpu_get_crash_info;
cc->write_elf64_note = s390_cpu_write_elf64_note;
cc->sysemu_ops = &s390_sysemu_ops;
#endif
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v4 11/28] cpu: Move CPUClass::write_elf* to SysemuCPUOps
2021-03-03 21:46 ` Philippe Mathieu-Daudé
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Claudio Fontana, qemu-arm, Peter Maydell, Paolo Bonzini,
Richard Henderson, qemu-s390x, Thomas Huth, qemu-ppc,
Laurent Vivier, Cornelia Huck, Alex Bennée,
Philippe Mathieu-Daudé, Eduardo Habkost, Marcel Apfelbaum,
David Gibson, Greg Kurz, David Hildenbrand
The write_elf*() handlers are used to dump vmcore images.
This feature is only meaningful for system emulation.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 17 -----------------
include/hw/core/sysemu-cpu-ops.h | 24 ++++++++++++++++++++++++
hw/core/cpu.c | 16 ++++++++--------
target/arm/cpu.c | 4 ++--
target/i386/cpu.c | 8 ++++----
target/s390x/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 6 ++----
7 files changed, 41 insertions(+), 36 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 781cd8fc42b..0a2c29c3735 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -112,14 +112,6 @@ struct AccelCPUClass;
* a memory access with the specified memory transaction attributes.
* @gdb_read_register: Callback for letting GDB read a register.
* @gdb_write_register: Callback for letting GDB write a register.
- * @write_elf64_note: Callback for writing a CPU-specific ELF note to a
- * 64-bit VM coredump.
- * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
- * note to a 32-bit VM coredump.
- * @write_elf32_note: Callback for writing a CPU-specific ELF note to a
- * 32-bit VM coredump.
- * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
- * note to a 32-bit VM coredump.
* @gdb_num_core_regs: Number of core registers accessible to GDB.
* @gdb_core_xml_file: File name for core registers GDB XML description.
* @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
@@ -163,15 +155,6 @@ struct CPUClass {
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
- int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
- int cpuid, void *opaque);
- int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
- void *opaque);
- int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
- int cpuid, void *opaque);
- int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
- void *opaque);
-
const char *gdb_core_xml_file;
gchar * (*gdb_arch_name)(CPUState *cpu);
const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index b9ffca07665..60c667801ef 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -21,6 +21,30 @@ typedef struct SysemuCPUOps {
* GUEST_PANICKED events.
*/
GuestPanicInformation* (*get_crash_info)(CPUState *cpu);
+ /**
+ * @write_elf32_note: Callback for writing a CPU-specific ELF note to a
+ * 32-bit VM coredump.
+ */
+ int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
+ int cpuid, void *opaque);
+ /**
+ * @write_elf64_note: Callback for writing a CPU-specific ELF note to a
+ * 64-bit VM coredump.
+ */
+ int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
+ int cpuid, void *opaque);
+ /**
+ * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
+ * note to a 32-bit VM coredump.
+ */
+ int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
+ void *opaque);
+ /**
+ * @write_elf64_qemunote: Callback for writing a CPU- and QEMU-specific ELF
+ * note to a 64-bit VM coredump.
+ */
+ int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
+ void *opaque);
/**
* @virtio_is_big_endian: Callback to return %true if a CPU which supports
* runtime configurable endianness is currently big-endian.
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 0aebc18c41f..c74390aafbf 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -151,10 +151,10 @@ int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (!cc->write_elf32_qemunote) {
+ if (!cc->sysemu_ops->write_elf32_qemunote) {
return 0;
}
- return (*cc->write_elf32_qemunote)(f, cpu, opaque);
+ return (*cc->sysemu_ops->write_elf32_qemunote)(f, cpu, opaque);
}
int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
@@ -162,10 +162,10 @@ int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (!cc->write_elf32_note) {
+ if (!cc->sysemu_ops->write_elf32_note) {
return -1;
}
- return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
+ return (*cc->sysemu_ops->write_elf32_note)(f, cpu, cpuid, opaque);
}
int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
@@ -173,10 +173,10 @@ int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (!cc->write_elf64_qemunote) {
+ if (!cc->sysemu_ops->write_elf64_qemunote) {
return 0;
}
- return (*cc->write_elf64_qemunote)(f, cpu, opaque);
+ return (*cc->sysemu_ops->write_elf64_qemunote)(f, cpu, opaque);
}
int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
@@ -184,10 +184,10 @@ int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (!cc->write_elf64_note) {
+ if (!cc->sysemu_ops->write_elf64_note) {
return -1;
}
- return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
+ return (*cc->sysemu_ops->write_elf64_note)(f, cpu, cpuid, opaque);
}
static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index fa0d4bba590..0c06b9b1758 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2262,6 +2262,8 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps arm_sysemu_ops = {
+ .write_elf32_note = arm_cpu_write_elf32_note,
+ .write_elf64_note = arm_cpu_write_elf64_note,
.virtio_is_big_endian = arm_cpu_virtio_is_big_endian,
.vmsd = &vmstate_arm_cpu,
};
@@ -2306,8 +2308,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->asidx_from_attrs = arm_asidx_from_attrs;
- cc->write_elf64_note = arm_cpu_write_elf64_note;
- cc->write_elf32_note = arm_cpu_write_elf32_note;
cc->sysemu_ops = &arm_sysemu_ops;
#endif
cc->gdb_num_core_regs = 26;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 362ad56ab68..403ed65fc61 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7389,6 +7389,10 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps i386_sysemu_ops = {
.get_crash_info = x86_cpu_get_crash_info,
+ .write_elf32_note = x86_cpu_write_elf32_note,
+ .write_elf64_note = x86_cpu_write_elf64_note,
+ .write_elf32_qemunote = x86_cpu_write_elf32_qemunote,
+ .write_elf64_qemunote = x86_cpu_write_elf64_qemunote,
.vmsd = &vmstate_x86_cpu,
};
#endif
@@ -7428,10 +7432,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->asidx_from_attrs = x86_asidx_from_attrs;
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
- cc->write_elf64_note = x86_cpu_write_elf64_note;
- cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
- cc->write_elf32_note = x86_cpu_write_elf32_note;
- cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
cc->sysemu_ops = &i386_sysemu_ops;
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index fdc169bb0ac..2b249f47eb9 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -480,6 +480,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps s390_sysemu_ops = {
.get_crash_info = s390_cpu_get_crash_info,
+ .write_elf64_note = s390_cpu_write_elf64_note,
.vmsd = &vmstate_s390_cpu,
};
#endif
@@ -524,7 +525,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = s390_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
- cc->write_elf64_note = s390_cpu_write_elf64_note;
cc->sysemu_ops = &s390_sysemu_ops;
#endif
cc->disas_set_info = s390_cpu_disas_set_info;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 789124debe7..598304bd636 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10845,6 +10845,8 @@ static Property ppc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps ppc_sysemu_ops = {
+ .write_elf32_note = ppc32_cpu_write_elf32_note,
+ .write_elf64_note = ppc64_cpu_write_elf64_note,
.virtio_is_big_endian = ppc_cpu_is_big_endian,
.vmsd = &vmstate_ppc_cpu,
};
@@ -10894,10 +10896,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
cc->sysemu_ops = &ppc_sysemu_ops;
#endif
-#if defined(CONFIG_SOFTMMU)
- cc->write_elf64_note = ppc64_cpu_write_elf64_note;
- cc->write_elf32_note = ppc32_cpu_write_elf32_note;
-#endif
cc->gdb_num_core_regs = 71;
#ifndef CONFIG_USER_ONLY
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread* [PATCH v4 11/28] cpu: Move CPUClass::write_elf* to SysemuCPUOps
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Thomas Huth, Eduardo Habkost, David Hildenbrand,
Cornelia Huck, Richard Henderson, Laurent Vivier,
Philippe Mathieu-Daudé, qemu-s390x, qemu-arm, qemu-ppc,
Claudio Fontana, Paolo Bonzini, Greg Kurz, Alex Bennée,
David Gibson
The write_elf*() handlers are used to dump vmcore images.
This feature is only meaningful for system emulation.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 17 -----------------
include/hw/core/sysemu-cpu-ops.h | 24 ++++++++++++++++++++++++
hw/core/cpu.c | 16 ++++++++--------
target/arm/cpu.c | 4 ++--
target/i386/cpu.c | 8 ++++----
target/s390x/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 6 ++----
7 files changed, 41 insertions(+), 36 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 781cd8fc42b..0a2c29c3735 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -112,14 +112,6 @@ struct AccelCPUClass;
* a memory access with the specified memory transaction attributes.
* @gdb_read_register: Callback for letting GDB read a register.
* @gdb_write_register: Callback for letting GDB write a register.
- * @write_elf64_note: Callback for writing a CPU-specific ELF note to a
- * 64-bit VM coredump.
- * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
- * note to a 32-bit VM coredump.
- * @write_elf32_note: Callback for writing a CPU-specific ELF note to a
- * 32-bit VM coredump.
- * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
- * note to a 32-bit VM coredump.
* @gdb_num_core_regs: Number of core registers accessible to GDB.
* @gdb_core_xml_file: File name for core registers GDB XML description.
* @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
@@ -163,15 +155,6 @@ struct CPUClass {
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
- int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
- int cpuid, void *opaque);
- int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
- void *opaque);
- int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
- int cpuid, void *opaque);
- int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
- void *opaque);
-
const char *gdb_core_xml_file;
gchar * (*gdb_arch_name)(CPUState *cpu);
const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index b9ffca07665..60c667801ef 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -21,6 +21,30 @@ typedef struct SysemuCPUOps {
* GUEST_PANICKED events.
*/
GuestPanicInformation* (*get_crash_info)(CPUState *cpu);
+ /**
+ * @write_elf32_note: Callback for writing a CPU-specific ELF note to a
+ * 32-bit VM coredump.
+ */
+ int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
+ int cpuid, void *opaque);
+ /**
+ * @write_elf64_note: Callback for writing a CPU-specific ELF note to a
+ * 64-bit VM coredump.
+ */
+ int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
+ int cpuid, void *opaque);
+ /**
+ * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
+ * note to a 32-bit VM coredump.
+ */
+ int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
+ void *opaque);
+ /**
+ * @write_elf64_qemunote: Callback for writing a CPU- and QEMU-specific ELF
+ * note to a 64-bit VM coredump.
+ */
+ int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
+ void *opaque);
/**
* @virtio_is_big_endian: Callback to return %true if a CPU which supports
* runtime configurable endianness is currently big-endian.
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 0aebc18c41f..c74390aafbf 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -151,10 +151,10 @@ int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (!cc->write_elf32_qemunote) {
+ if (!cc->sysemu_ops->write_elf32_qemunote) {
return 0;
}
- return (*cc->write_elf32_qemunote)(f, cpu, opaque);
+ return (*cc->sysemu_ops->write_elf32_qemunote)(f, cpu, opaque);
}
int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
@@ -162,10 +162,10 @@ int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (!cc->write_elf32_note) {
+ if (!cc->sysemu_ops->write_elf32_note) {
return -1;
}
- return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
+ return (*cc->sysemu_ops->write_elf32_note)(f, cpu, cpuid, opaque);
}
int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
@@ -173,10 +173,10 @@ int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (!cc->write_elf64_qemunote) {
+ if (!cc->sysemu_ops->write_elf64_qemunote) {
return 0;
}
- return (*cc->write_elf64_qemunote)(f, cpu, opaque);
+ return (*cc->sysemu_ops->write_elf64_qemunote)(f, cpu, opaque);
}
int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
@@ -184,10 +184,10 @@ int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (!cc->write_elf64_note) {
+ if (!cc->sysemu_ops->write_elf64_note) {
return -1;
}
- return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
+ return (*cc->sysemu_ops->write_elf64_note)(f, cpu, cpuid, opaque);
}
static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index fa0d4bba590..0c06b9b1758 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2262,6 +2262,8 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps arm_sysemu_ops = {
+ .write_elf32_note = arm_cpu_write_elf32_note,
+ .write_elf64_note = arm_cpu_write_elf64_note,
.virtio_is_big_endian = arm_cpu_virtio_is_big_endian,
.vmsd = &vmstate_arm_cpu,
};
@@ -2306,8 +2308,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->asidx_from_attrs = arm_asidx_from_attrs;
- cc->write_elf64_note = arm_cpu_write_elf64_note;
- cc->write_elf32_note = arm_cpu_write_elf32_note;
cc->sysemu_ops = &arm_sysemu_ops;
#endif
cc->gdb_num_core_regs = 26;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 362ad56ab68..403ed65fc61 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7389,6 +7389,10 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps i386_sysemu_ops = {
.get_crash_info = x86_cpu_get_crash_info,
+ .write_elf32_note = x86_cpu_write_elf32_note,
+ .write_elf64_note = x86_cpu_write_elf64_note,
+ .write_elf32_qemunote = x86_cpu_write_elf32_qemunote,
+ .write_elf64_qemunote = x86_cpu_write_elf64_qemunote,
.vmsd = &vmstate_x86_cpu,
};
#endif
@@ -7428,10 +7432,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->asidx_from_attrs = x86_asidx_from_attrs;
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
- cc->write_elf64_note = x86_cpu_write_elf64_note;
- cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
- cc->write_elf32_note = x86_cpu_write_elf32_note;
- cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
cc->sysemu_ops = &i386_sysemu_ops;
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index fdc169bb0ac..2b249f47eb9 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -480,6 +480,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps s390_sysemu_ops = {
.get_crash_info = s390_cpu_get_crash_info,
+ .write_elf64_note = s390_cpu_write_elf64_note,
.vmsd = &vmstate_s390_cpu,
};
#endif
@@ -524,7 +525,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = s390_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
- cc->write_elf64_note = s390_cpu_write_elf64_note;
cc->sysemu_ops = &s390_sysemu_ops;
#endif
cc->disas_set_info = s390_cpu_disas_set_info;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 789124debe7..598304bd636 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10845,6 +10845,8 @@ static Property ppc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps ppc_sysemu_ops = {
+ .write_elf32_note = ppc32_cpu_write_elf32_note,
+ .write_elf64_note = ppc64_cpu_write_elf64_note,
.virtio_is_big_endian = ppc_cpu_is_big_endian,
.vmsd = &vmstate_ppc_cpu,
};
@@ -10894,10 +10896,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
cc->sysemu_ops = &ppc_sysemu_ops;
#endif
-#if defined(CONFIG_SOFTMMU)
- cc->write_elf64_note = ppc64_cpu_write_elf64_note;
- cc->write_elf32_note = ppc32_cpu_write_elf32_note;
-#endif
cc->gdb_num_core_regs = 71;
#ifndef CONFIG_USER_ONLY
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v4 12/28] cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps
2021-03-03 21:46 ` Philippe Mathieu-Daudé
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Claudio Fontana, qemu-arm, Peter Maydell, Paolo Bonzini,
Richard Henderson, qemu-s390x, Thomas Huth, qemu-ppc,
Laurent Vivier, Cornelia Huck, Alex Bennée,
Philippe Mathieu-Daudé, Eduardo Habkost, Marcel Apfelbaum
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 3 ---
include/hw/core/sysemu-cpu-ops.h | 5 +++++
hw/core/cpu.c | 4 ++--
target/arm/cpu.c | 2 +-
target/i386/cpu.c | 2 +-
5 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 0a2c29c3735..6713a615916 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -108,8 +108,6 @@ struct AccelCPUClass;
* associated memory transaction attributes to use for the access.
* CPUs which use memory transaction attributes should implement this
* instead of get_phys_page_debug.
- * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
- * a memory access with the specified memory transaction attributes.
* @gdb_read_register: Callback for letting GDB read a register.
* @gdb_write_register: Callback for letting GDB write a register.
* @gdb_num_core_regs: Number of core registers accessible to GDB.
@@ -151,7 +149,6 @@ struct CPUClass {
hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
MemTxAttrs *attrs);
- int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs);
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 60c667801ef..3c3f211136d 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,11 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
+ * a memory access with the specified memory transaction attributes.
+ */
+ int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs);
/**
* @get_crash_info: Callback for reporting guest crash information in
* GUEST_PANICKED events.
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index c74390aafbf..c44229205ff 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -116,8 +116,8 @@ int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
CPUClass *cc = CPU_GET_CLASS(cpu);
int ret = 0;
- if (cc->asidx_from_attrs) {
- ret = cc->asidx_from_attrs(cpu, attrs);
+ if (cc->sysemu_ops->asidx_from_attrs) {
+ ret = cc->sysemu_ops->asidx_from_attrs(cpu, attrs);
assert(ret < cpu->num_ases && ret >= 0);
}
return ret;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 0c06b9b1758..7edb9f581bc 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2262,6 +2262,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps arm_sysemu_ops = {
+ .asidx_from_attrs = arm_asidx_from_attrs,
.write_elf32_note = arm_cpu_write_elf32_note,
.write_elf64_note = arm_cpu_write_elf64_note,
.virtio_is_big_endian = arm_cpu_virtio_is_big_endian,
@@ -2307,7 +2308,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = arm_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
- cc->asidx_from_attrs = arm_asidx_from_attrs;
cc->sysemu_ops = &arm_sysemu_ops;
#endif
cc->gdb_num_core_regs = 26;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 403ed65fc61..4f64f9c2d68 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7388,6 +7388,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps i386_sysemu_ops = {
+ .asidx_from_attrs = x86_asidx_from_attrs,
.get_crash_info = x86_cpu_get_crash_info,
.write_elf32_note = x86_cpu_write_elf32_note,
.write_elf64_note = x86_cpu_write_elf64_note,
@@ -7429,7 +7430,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->get_paging_enabled = x86_cpu_get_paging_enabled;
#ifndef CONFIG_USER_ONLY
- cc->asidx_from_attrs = x86_asidx_from_attrs;
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
cc->sysemu_ops = &i386_sysemu_ops;
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread* [PATCH v4 12/28] cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Thomas Huth, Eduardo Habkost, Cornelia Huck,
Richard Henderson, Laurent Vivier, Philippe Mathieu-Daudé,
qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana, Paolo Bonzini,
Alex Bennée
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 3 ---
include/hw/core/sysemu-cpu-ops.h | 5 +++++
hw/core/cpu.c | 4 ++--
target/arm/cpu.c | 2 +-
target/i386/cpu.c | 2 +-
5 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 0a2c29c3735..6713a615916 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -108,8 +108,6 @@ struct AccelCPUClass;
* associated memory transaction attributes to use for the access.
* CPUs which use memory transaction attributes should implement this
* instead of get_phys_page_debug.
- * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
- * a memory access with the specified memory transaction attributes.
* @gdb_read_register: Callback for letting GDB read a register.
* @gdb_write_register: Callback for letting GDB write a register.
* @gdb_num_core_regs: Number of core registers accessible to GDB.
@@ -151,7 +149,6 @@ struct CPUClass {
hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
MemTxAttrs *attrs);
- int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs);
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 60c667801ef..3c3f211136d 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,11 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
+ * a memory access with the specified memory transaction attributes.
+ */
+ int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs);
/**
* @get_crash_info: Callback for reporting guest crash information in
* GUEST_PANICKED events.
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index c74390aafbf..c44229205ff 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -116,8 +116,8 @@ int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
CPUClass *cc = CPU_GET_CLASS(cpu);
int ret = 0;
- if (cc->asidx_from_attrs) {
- ret = cc->asidx_from_attrs(cpu, attrs);
+ if (cc->sysemu_ops->asidx_from_attrs) {
+ ret = cc->sysemu_ops->asidx_from_attrs(cpu, attrs);
assert(ret < cpu->num_ases && ret >= 0);
}
return ret;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 0c06b9b1758..7edb9f581bc 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2262,6 +2262,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps arm_sysemu_ops = {
+ .asidx_from_attrs = arm_asidx_from_attrs,
.write_elf32_note = arm_cpu_write_elf32_note,
.write_elf64_note = arm_cpu_write_elf64_note,
.virtio_is_big_endian = arm_cpu_virtio_is_big_endian,
@@ -2307,7 +2308,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = arm_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
- cc->asidx_from_attrs = arm_asidx_from_attrs;
cc->sysemu_ops = &arm_sysemu_ops;
#endif
cc->gdb_num_core_regs = 26;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 403ed65fc61..4f64f9c2d68 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7388,6 +7388,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps i386_sysemu_ops = {
+ .asidx_from_attrs = x86_asidx_from_attrs,
.get_crash_info = x86_cpu_get_crash_info,
.write_elf32_note = x86_cpu_write_elf32_note,
.write_elf64_note = x86_cpu_write_elf64_note,
@@ -7429,7 +7430,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->get_paging_enabled = x86_cpu_get_paging_enabled;
#ifndef CONFIG_USER_ONLY
- cc->asidx_from_attrs = x86_asidx_from_attrs;
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
cc->sysemu_ops = &i386_sysemu_ops;
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v4 13/28] cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps
2021-03-03 21:46 ` Philippe Mathieu-Daudé
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Claudio Fontana, qemu-arm, Peter Maydell, Paolo Bonzini,
Richard Henderson, qemu-s390x, Thomas Huth, qemu-ppc,
Laurent Vivier, Cornelia Huck, Alex Bennée,
Philippe Mathieu-Daudé, Eduardo Habkost, Marcel Apfelbaum,
Michael Rolnik, Sarah Harris, Edgar E. Iglesias, Michael Walle,
Aurelien Jarno, Jiaxun Yang, Aleksandar Rikalo, Anthony Green,
Chris Wulff, Marek Vasut, Stafford Horne, David Gibson, Greg Kurz,
Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, Yoshinori Sato, David Hildenbrand,
Mark Cave-Ayland, Artyom Tarasenko, Guan Xuetao, Max Filippov,
open list:RISC-V TCG CPUs
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 8 --------
include/hw/core/sysemu-cpu-ops.h | 13 +++++++++++++
hw/core/cpu.c | 6 +++---
target/alpha/cpu.c | 2 +-
target/arm/cpu.c | 2 +-
target/avr/cpu.c | 2 +-
target/cris/cpu.c | 2 +-
target/hppa/cpu.c | 2 +-
target/i386/cpu.c | 2 +-
target/lm32/cpu.c | 2 +-
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 2 +-
target/moxie/cpu.c | 4 +---
target/nios2/cpu.c | 2 +-
target/openrisc/cpu.c | 2 +-
target/riscv/cpu.c | 2 +-
target/rx/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/sh4/cpu.c | 2 +-
target/sparc/cpu.c | 2 +-
target/tricore/cpu.c | 2 +-
target/unicore32/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 2 +-
25 files changed, 38 insertions(+), 35 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 6713a615916..9a86c707cf7 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -103,11 +103,6 @@ struct AccelCPUClass;
* If the target behaviour here is anything other than "set
* the PC register to the value passed in" then the target must
* also implement the synchronize_from_tb hook.
- * @get_phys_page_debug: Callback for obtaining a physical address.
- * @get_phys_page_attrs_debug: Callback for obtaining a physical address and the
- * associated memory transaction attributes to use for the access.
- * CPUs which use memory transaction attributes should implement this
- * instead of get_phys_page_debug.
* @gdb_read_register: Callback for letting GDB read a register.
* @gdb_write_register: Callback for letting GDB write a register.
* @gdb_num_core_regs: Number of core registers accessible to GDB.
@@ -146,9 +141,6 @@ struct CPUClass {
void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
Error **errp);
void (*set_pc)(CPUState *cpu, vaddr value);
- hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
- hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
- MemTxAttrs *attrs);
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 3c3f211136d..0c8f616a565 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,19 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @get_phys_page_debug: Callback for obtaining a physical address.
+ */
+ hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
+ /**
+ * @get_phys_page_attrs_debug: Callback for obtaining a physical address
+ * and the associated memory transaction attributes to use for the
+ * access.
+ * CPUs which use memory transaction attributes should implement this
+ * instead of get_phys_page_debug.
+ */
+ hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
+ MemTxAttrs *attrs);
/**
* @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
* a memory access with the specified memory transaction attributes.
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index c44229205ff..6932781425a 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -96,12 +96,12 @@ hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->get_phys_page_attrs_debug) {
- return cc->get_phys_page_attrs_debug(cpu, addr, attrs);
+ if (cc->sysemu_ops->get_phys_page_attrs_debug) {
+ return cc->sysemu_ops->get_phys_page_attrs_debug(cpu, addr, attrs);
}
/* Fallback for CPUs which don't implement the _attrs_ hook */
*attrs = MEMTXATTRS_UNSPECIFIED;
- return cc->get_phys_page_debug(cpu, addr);
+ return cc->sysemu_ops->get_phys_page_debug(cpu, addr);
}
hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index de8f9c648fa..fbef4c0923f 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -208,6 +208,7 @@ static void alpha_cpu_initfn(Object *obj)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps alpha_sysemu_ops = {
+ .get_phys_page_debug = alpha_cpu_get_phys_page_debug,
.vmsd = &vmstate_alpha_cpu,
};
#endif
@@ -242,7 +243,6 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = alpha_cpu_gdb_read_register;
cc->gdb_write_register = alpha_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
cc->sysemu_ops = &alpha_sysemu_ops;
#endif
cc->disas_set_info = alpha_cpu_disas_set_info;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 7edb9f581bc..09566a535e5 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2262,6 +2262,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps arm_sysemu_ops = {
+ .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug,
.asidx_from_attrs = arm_asidx_from_attrs,
.write_elf32_note = arm_cpu_write_elf32_note,
.write_elf64_note = arm_cpu_write_elf64_note,
@@ -2307,7 +2308,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = arm_cpu_gdb_read_register;
cc->gdb_write_register = arm_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->sysemu_ops = &arm_sysemu_ops;
#endif
cc->gdb_num_core_regs = 26;
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 20a48bdfbab..436d001a679 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -185,6 +185,7 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
static const struct SysemuCPUOps avr_sysemu_ops = {
+ .get_phys_page_debug = avr_cpu_get_phys_page_debug,
.vmsd = &vms_avr_cpu,
};
@@ -216,7 +217,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = avr_cpu_dump_state;
cc->set_pc = avr_cpu_set_pc;
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
- cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
cc->sysemu_ops = &avr_sysemu_ops;
cc->disas_set_info = avr_cpu_disas_set_info;
cc->gdb_read_register = avr_cpu_gdb_read_register;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index c05707bad2c..6c1eb8d6172 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -195,6 +195,7 @@ static void cris_cpu_initfn(Object *obj)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps cris_sysemu_ops = {
+ .get_phys_page_debug = cris_cpu_get_phys_page_debug,
.vmsd = &vmstate_cris_cpu,
};
#endif
@@ -298,7 +299,6 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = cris_cpu_gdb_read_register;
cc->gdb_write_register = cris_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
cc->sysemu_ops = &cris_sysemu_ops;
#endif
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 110cc8a6d68..f0eeaea22bb 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -133,6 +133,7 @@ static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps hppa_sysemu_ops = {
+ .get_phys_page_debug = hppa_cpu_get_phys_page_debug,
.vmsd = &vmstate_hppa_cpu,
};
#endif
@@ -167,7 +168,6 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = hppa_cpu_gdb_read_register;
cc->gdb_write_register = hppa_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug;
cc->sysemu_ops = &hppa_sysemu_ops;
#endif
cc->disas_set_info = hppa_cpu_disas_set_info;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 4f64f9c2d68..0de4ee18bee 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7388,6 +7388,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps i386_sysemu_ops = {
+ .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug,
.asidx_from_attrs = x86_asidx_from_attrs,
.get_crash_info = x86_cpu_get_crash_info,
.write_elf32_note = x86_cpu_write_elf32_note,
@@ -7431,7 +7432,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
- cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
cc->sysemu_ops = &i386_sysemu_ops;
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index 4ff54fd9204..d31c33575f6 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -212,6 +212,7 @@ static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps lm32_sysemu_ops = {
+ .get_phys_page_debug = lm32_cpu_get_phys_page_debug,
.vmsd = &vmstate_lm32_cpu,
};
#endif
@@ -246,7 +247,6 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = lm32_cpu_gdb_read_register;
cc->gdb_write_register = lm32_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
cc->sysemu_ops = &lm32_sysemu_ops;
#endif
cc->gdb_num_core_regs = 32 + 7;
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index e7ddcf2ee28..67ea33c8200 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -504,6 +504,7 @@ static const VMStateDescription vmstate_m68k_cpu = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps m68k_sysemu_ops = {
+ .get_phys_page_debug = m68k_cpu_get_phys_page_debug,
.vmsd = &vmstate_m68k_cpu,
};
#endif
@@ -538,7 +539,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_read_register = m68k_cpu_gdb_read_register;
cc->gdb_write_register = m68k_cpu_gdb_write_register;
#if defined(CONFIG_SOFTMMU)
- cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
cc->sysemu_ops = &m68k_sysemu_ops;
#endif
cc->disas_set_info = m68k_cpu_disas_set_info;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 8b86b99c15b..49d6f16ca70 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -354,6 +354,7 @@ static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps mb_sysemu_ops = {
+ .get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug,
.vmsd = &vmstate_mb_cpu,
};
#endif
@@ -392,7 +393,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = mb_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug;
cc->sysemu_ops = &mb_sysemu_ops;
#endif
device_class_set_props(dc, mb_properties);
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index ef997bcd67f..d8f2086c69e 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -682,6 +682,7 @@ static Property mips_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps mips_sysemu_ops = {
+ .get_phys_page_debug = mips_cpu_get_phys_page_debug,
.vmsd = &vmstate_mips_cpu,
};
#endif
@@ -725,7 +726,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_read_register = mips_cpu_gdb_read_register;
cc->gdb_write_register = mips_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
cc->sysemu_ops = &mips_sysemu_ops;
#endif
cc->disas_set_info = mips_cpu_disas_set_info;
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index 1e87f07ca73..c488bbc894a 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -95,6 +95,7 @@ static ObjectClass *moxie_cpu_class_by_name(const char *cpu_model)
}
static const struct SysemuCPUOps moxie_sysemu_ops = {
+ .get_phys_page_debug = moxie_cpu_get_phys_page_debug,
.vmsd = &vmstate_moxie_cpu,
};
@@ -124,9 +125,6 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
cc->has_work = moxie_cpu_has_work;
cc->dump_state = moxie_cpu_dump_state;
cc->set_pc = moxie_cpu_set_pc;
-#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = moxie_cpu_get_phys_page_debug;
-#endif
cc->disas_set_info = moxie_cpu_disas_set_info;
cc->sysemu_ops = &moxie_sysemu_ops;
cc->tcg_ops = &moxie_tcg_ops;
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index a785f3ea7b6..6fc73ed8693 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -215,6 +215,7 @@ static const VMStateDescription vmstate_nios2_cpu = {
};
static const struct SysemuCPUOps nios2_sysemu_ops = {
+ .get_phys_page_debug = nios2_cpu_get_phys_page_debug,
.vmsd = &vmstate_nios2_cpu,
};
#endif
@@ -249,7 +250,6 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = nios2_cpu_set_pc;
cc->disas_set_info = nios2_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = nios2_cpu_get_phys_page_debug;
cc->sysemu_ops = &nios2_sysemu_ops;
#endif
cc->gdb_read_register = nios2_cpu_gdb_read_register;
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 2149e9564fa..1b05f4e3567 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -176,6 +176,7 @@ static void openrisc_any_initfn(Object *obj)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps openrisc_sysemu_ops = {
+ .get_phys_page_debug = openrisc_cpu_get_phys_page_debug,
.vmsd = &vmstate_openrisc_cpu,
};
#endif
@@ -209,7 +210,6 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = openrisc_cpu_gdb_read_register;
cc->gdb_write_register = openrisc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
cc->sysemu_ops = &openrisc_sysemu_ops;
#endif
cc->gdb_num_core_regs = 32 + 3;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a6b1ff93299..14dc8583615 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -582,6 +582,7 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps riscv_sysemu_ops = {
+ .get_phys_page_debug = riscv_cpu_get_phys_page_debug,
/* For now, mark unmigratable: */
.vmsd = &vmstate_riscv_cpu,
};
@@ -628,7 +629,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
cc->sysemu_ops = &riscv_sysemu_ops;
#endif
cc->gdb_arch_name = riscv_gdb_arch_name;
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index f293f3630d0..5f8226ed31c 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -180,6 +180,7 @@ static const VMStateDescription vmstate_rx_cpu = {
};
static const struct SysemuCPUOps rx_sysemu_ops = {
+ .get_phys_page_debug = rx_cpu_get_phys_page_debug,
.vmsd = &vmstate_rx_cpu,
};
#endif
@@ -218,7 +219,6 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
#endif
cc->gdb_read_register = rx_cpu_gdb_read_register;
cc->gdb_write_register = rx_cpu_gdb_write_register;
- cc->get_phys_page_debug = rx_cpu_get_phys_page_debug;
cc->disas_set_info = rx_cpu_disas_set_info;
cc->gdb_num_core_regs = 26;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 2b249f47eb9..96e8342fb96 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -479,6 +479,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps s390_sysemu_ops = {
+ .get_phys_page_debug = s390_cpu_get_phys_page_debug,
.get_crash_info = s390_cpu_get_crash_info,
.write_elf64_note = s390_cpu_write_elf64_note,
.vmsd = &vmstate_s390_cpu,
@@ -524,7 +525,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = s390_cpu_gdb_read_register;
cc->gdb_write_register = s390_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
cc->sysemu_ops = &s390_sysemu_ops;
#endif
cc->disas_set_info = s390_cpu_disas_set_info;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 8c1d0ba53b1..2f7b43a0353 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -225,6 +225,7 @@ static const VMStateDescription vmstate_sh_cpu = {
};
static const struct SysemuCPUOps sh4_sysemu_ops = {
+ .get_phys_page_debug = superh_cpu_get_phys_page_debug,
.vmsd = &vmstate_sh_cpu,
};
#endif
@@ -262,7 +263,6 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = superh_cpu_gdb_read_register;
cc->gdb_write_register = superh_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
cc->sysemu_ops = &sh4_sysemu_ops;
#endif
cc->disas_set_info = superh_cpu_disas_set_info;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index f5862e74baf..b13d586f79d 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -850,6 +850,7 @@ static Property sparc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps sparc_sysemu_ops = {
+ .get_phys_page_debug = sparc_cpu_get_phys_page_debug,
.vmsd = &vmstate_sparc_cpu,
};
#endif
@@ -894,7 +895,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = sparc_cpu_gdb_read_register;
cc->gdb_write_register = sparc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
cc->sysemu_ops = &sparc_sysemu_ops;
#endif
cc->disas_set_info = cpu_sparc_disas_set_info;
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 9374f8440a0..b1776c10205 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -149,6 +149,7 @@ static const VMStateDescription vmstate_tricore_cpu = {
};
static const struct SysemuCPUOps tricore_sysemu_ops = {
+ .get_phys_page_debug = tricore_cpu_get_phys_page_debug,
.vmsd = &vmstate_tricore_cpu,
};
@@ -180,7 +181,6 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
cc->dump_state = tricore_cpu_dump_state;
cc->set_pc = tricore_cpu_set_pc;
- cc->get_phys_page_debug = tricore_cpu_get_phys_page_debug;
cc->sysemu_ops = &tricore_sysemu_ops;
cc->tcg_ops = &tricore_tcg_ops;
}
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index 345b6e9e417..1b2bb25f508 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -121,6 +121,7 @@ static const VMStateDescription vmstate_uc32_cpu = {
};
static const struct SysemuCPUOps uc32_sysemu_ops = {
+ .get_phys_page_debug = uc32_cpu_get_phys_page_debug,
.vmsd = &vmstate_uc32_cpu,
};
@@ -149,7 +150,6 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->has_work = uc32_cpu_has_work;
cc->dump_state = uc32_cpu_dump_state;
cc->set_pc = uc32_cpu_set_pc;
- cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
cc->sysemu_ops = &uc32_sysemu_ops;
cc->tcg_ops = &uc32_tcg_ops;
}
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index fd65246015f..8b1d827e747 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -183,6 +183,7 @@ static const VMStateDescription vmstate_xtensa_cpu = {
};
static const struct SysemuCPUOps xtensa_sysemu_ops = {
+ .get_phys_page_debug = xtensa_cpu_get_phys_page_debug,
.vmsd = &vmstate_xtensa_cpu,
};
#endif
@@ -222,7 +223,6 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_stop_before_watchpoint = true;
#ifndef CONFIG_USER_ONLY
cc->sysemu_ops = &xtensa_sysemu_ops;
- cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
#endif
cc->disas_set_info = xtensa_cpu_disas_set_info;
cc->tcg_ops = &xtensa_tcg_ops;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 598304bd636..cd22a1ce3f0 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10845,6 +10845,7 @@ static Property ppc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps ppc_sysemu_ops = {
+ .get_phys_page_debug = ppc_cpu_get_phys_page_debug,
.write_elf32_note = ppc32_cpu_write_elf32_note,
.write_elf64_note = ppc64_cpu_write_elf64_note,
.virtio_is_big_endian = ppc_cpu_is_big_endian,
@@ -10893,7 +10894,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = ppc_cpu_gdb_read_register;
cc->gdb_write_register = ppc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
cc->sysemu_ops = &ppc_sysemu_ops;
#endif
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread* [PATCH v4 13/28] cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Sarah Harris, Chris Wulff, Sagar Karandikar,
David Hildenbrand, Anthony Green, Mark Cave-Ayland,
Aleksandar Rikalo, Philippe Mathieu-Daudé, Max Filippov,
Alistair Francis, Edgar E. Iglesias, Guan Xuetao, Marek Vasut,
Yoshinori Sato, Claudio Fontana, Palmer Dabbelt, Artyom Tarasenko,
Thomas Huth, Eduardo Habkost, Richard Henderson, Greg Kurz,
qemu-s390x, qemu-arm, Michael Rolnik, Stafford Horne,
Alex Bennée, David Gibson, open list:RISC-V TCG CPUs,
Bastian Koppelmann, Cornelia Huck, Laurent Vivier, Michael Walle,
qemu-ppc, Paolo Bonzini, Aurelien Jarno
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 8 --------
include/hw/core/sysemu-cpu-ops.h | 13 +++++++++++++
hw/core/cpu.c | 6 +++---
target/alpha/cpu.c | 2 +-
target/arm/cpu.c | 2 +-
target/avr/cpu.c | 2 +-
target/cris/cpu.c | 2 +-
target/hppa/cpu.c | 2 +-
target/i386/cpu.c | 2 +-
target/lm32/cpu.c | 2 +-
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 2 +-
target/moxie/cpu.c | 4 +---
target/nios2/cpu.c | 2 +-
target/openrisc/cpu.c | 2 +-
target/riscv/cpu.c | 2 +-
target/rx/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/sh4/cpu.c | 2 +-
target/sparc/cpu.c | 2 +-
target/tricore/cpu.c | 2 +-
target/unicore32/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 2 +-
25 files changed, 38 insertions(+), 35 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 6713a615916..9a86c707cf7 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -103,11 +103,6 @@ struct AccelCPUClass;
* If the target behaviour here is anything other than "set
* the PC register to the value passed in" then the target must
* also implement the synchronize_from_tb hook.
- * @get_phys_page_debug: Callback for obtaining a physical address.
- * @get_phys_page_attrs_debug: Callback for obtaining a physical address and the
- * associated memory transaction attributes to use for the access.
- * CPUs which use memory transaction attributes should implement this
- * instead of get_phys_page_debug.
* @gdb_read_register: Callback for letting GDB read a register.
* @gdb_write_register: Callback for letting GDB write a register.
* @gdb_num_core_regs: Number of core registers accessible to GDB.
@@ -146,9 +141,6 @@ struct CPUClass {
void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
Error **errp);
void (*set_pc)(CPUState *cpu, vaddr value);
- hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
- hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
- MemTxAttrs *attrs);
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 3c3f211136d..0c8f616a565 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,19 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @get_phys_page_debug: Callback for obtaining a physical address.
+ */
+ hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
+ /**
+ * @get_phys_page_attrs_debug: Callback for obtaining a physical address
+ * and the associated memory transaction attributes to use for the
+ * access.
+ * CPUs which use memory transaction attributes should implement this
+ * instead of get_phys_page_debug.
+ */
+ hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
+ MemTxAttrs *attrs);
/**
* @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
* a memory access with the specified memory transaction attributes.
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index c44229205ff..6932781425a 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -96,12 +96,12 @@ hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->get_phys_page_attrs_debug) {
- return cc->get_phys_page_attrs_debug(cpu, addr, attrs);
+ if (cc->sysemu_ops->get_phys_page_attrs_debug) {
+ return cc->sysemu_ops->get_phys_page_attrs_debug(cpu, addr, attrs);
}
/* Fallback for CPUs which don't implement the _attrs_ hook */
*attrs = MEMTXATTRS_UNSPECIFIED;
- return cc->get_phys_page_debug(cpu, addr);
+ return cc->sysemu_ops->get_phys_page_debug(cpu, addr);
}
hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index de8f9c648fa..fbef4c0923f 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -208,6 +208,7 @@ static void alpha_cpu_initfn(Object *obj)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps alpha_sysemu_ops = {
+ .get_phys_page_debug = alpha_cpu_get_phys_page_debug,
.vmsd = &vmstate_alpha_cpu,
};
#endif
@@ -242,7 +243,6 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = alpha_cpu_gdb_read_register;
cc->gdb_write_register = alpha_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
cc->sysemu_ops = &alpha_sysemu_ops;
#endif
cc->disas_set_info = alpha_cpu_disas_set_info;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 7edb9f581bc..09566a535e5 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2262,6 +2262,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps arm_sysemu_ops = {
+ .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug,
.asidx_from_attrs = arm_asidx_from_attrs,
.write_elf32_note = arm_cpu_write_elf32_note,
.write_elf64_note = arm_cpu_write_elf64_note,
@@ -2307,7 +2308,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = arm_cpu_gdb_read_register;
cc->gdb_write_register = arm_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->sysemu_ops = &arm_sysemu_ops;
#endif
cc->gdb_num_core_regs = 26;
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 20a48bdfbab..436d001a679 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -185,6 +185,7 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
static const struct SysemuCPUOps avr_sysemu_ops = {
+ .get_phys_page_debug = avr_cpu_get_phys_page_debug,
.vmsd = &vms_avr_cpu,
};
@@ -216,7 +217,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = avr_cpu_dump_state;
cc->set_pc = avr_cpu_set_pc;
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
- cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
cc->sysemu_ops = &avr_sysemu_ops;
cc->disas_set_info = avr_cpu_disas_set_info;
cc->gdb_read_register = avr_cpu_gdb_read_register;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index c05707bad2c..6c1eb8d6172 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -195,6 +195,7 @@ static void cris_cpu_initfn(Object *obj)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps cris_sysemu_ops = {
+ .get_phys_page_debug = cris_cpu_get_phys_page_debug,
.vmsd = &vmstate_cris_cpu,
};
#endif
@@ -298,7 +299,6 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = cris_cpu_gdb_read_register;
cc->gdb_write_register = cris_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
cc->sysemu_ops = &cris_sysemu_ops;
#endif
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 110cc8a6d68..f0eeaea22bb 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -133,6 +133,7 @@ static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps hppa_sysemu_ops = {
+ .get_phys_page_debug = hppa_cpu_get_phys_page_debug,
.vmsd = &vmstate_hppa_cpu,
};
#endif
@@ -167,7 +168,6 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = hppa_cpu_gdb_read_register;
cc->gdb_write_register = hppa_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug;
cc->sysemu_ops = &hppa_sysemu_ops;
#endif
cc->disas_set_info = hppa_cpu_disas_set_info;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 4f64f9c2d68..0de4ee18bee 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7388,6 +7388,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps i386_sysemu_ops = {
+ .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug,
.asidx_from_attrs = x86_asidx_from_attrs,
.get_crash_info = x86_cpu_get_crash_info,
.write_elf32_note = x86_cpu_write_elf32_note,
@@ -7431,7 +7432,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
- cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
cc->sysemu_ops = &i386_sysemu_ops;
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index 4ff54fd9204..d31c33575f6 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -212,6 +212,7 @@ static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps lm32_sysemu_ops = {
+ .get_phys_page_debug = lm32_cpu_get_phys_page_debug,
.vmsd = &vmstate_lm32_cpu,
};
#endif
@@ -246,7 +247,6 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = lm32_cpu_gdb_read_register;
cc->gdb_write_register = lm32_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
cc->sysemu_ops = &lm32_sysemu_ops;
#endif
cc->gdb_num_core_regs = 32 + 7;
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index e7ddcf2ee28..67ea33c8200 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -504,6 +504,7 @@ static const VMStateDescription vmstate_m68k_cpu = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps m68k_sysemu_ops = {
+ .get_phys_page_debug = m68k_cpu_get_phys_page_debug,
.vmsd = &vmstate_m68k_cpu,
};
#endif
@@ -538,7 +539,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_read_register = m68k_cpu_gdb_read_register;
cc->gdb_write_register = m68k_cpu_gdb_write_register;
#if defined(CONFIG_SOFTMMU)
- cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
cc->sysemu_ops = &m68k_sysemu_ops;
#endif
cc->disas_set_info = m68k_cpu_disas_set_info;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 8b86b99c15b..49d6f16ca70 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -354,6 +354,7 @@ static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps mb_sysemu_ops = {
+ .get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug,
.vmsd = &vmstate_mb_cpu,
};
#endif
@@ -392,7 +393,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = mb_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug;
cc->sysemu_ops = &mb_sysemu_ops;
#endif
device_class_set_props(dc, mb_properties);
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index ef997bcd67f..d8f2086c69e 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -682,6 +682,7 @@ static Property mips_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps mips_sysemu_ops = {
+ .get_phys_page_debug = mips_cpu_get_phys_page_debug,
.vmsd = &vmstate_mips_cpu,
};
#endif
@@ -725,7 +726,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_read_register = mips_cpu_gdb_read_register;
cc->gdb_write_register = mips_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
cc->sysemu_ops = &mips_sysemu_ops;
#endif
cc->disas_set_info = mips_cpu_disas_set_info;
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index 1e87f07ca73..c488bbc894a 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -95,6 +95,7 @@ static ObjectClass *moxie_cpu_class_by_name(const char *cpu_model)
}
static const struct SysemuCPUOps moxie_sysemu_ops = {
+ .get_phys_page_debug = moxie_cpu_get_phys_page_debug,
.vmsd = &vmstate_moxie_cpu,
};
@@ -124,9 +125,6 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
cc->has_work = moxie_cpu_has_work;
cc->dump_state = moxie_cpu_dump_state;
cc->set_pc = moxie_cpu_set_pc;
-#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = moxie_cpu_get_phys_page_debug;
-#endif
cc->disas_set_info = moxie_cpu_disas_set_info;
cc->sysemu_ops = &moxie_sysemu_ops;
cc->tcg_ops = &moxie_tcg_ops;
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index a785f3ea7b6..6fc73ed8693 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -215,6 +215,7 @@ static const VMStateDescription vmstate_nios2_cpu = {
};
static const struct SysemuCPUOps nios2_sysemu_ops = {
+ .get_phys_page_debug = nios2_cpu_get_phys_page_debug,
.vmsd = &vmstate_nios2_cpu,
};
#endif
@@ -249,7 +250,6 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = nios2_cpu_set_pc;
cc->disas_set_info = nios2_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = nios2_cpu_get_phys_page_debug;
cc->sysemu_ops = &nios2_sysemu_ops;
#endif
cc->gdb_read_register = nios2_cpu_gdb_read_register;
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 2149e9564fa..1b05f4e3567 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -176,6 +176,7 @@ static void openrisc_any_initfn(Object *obj)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps openrisc_sysemu_ops = {
+ .get_phys_page_debug = openrisc_cpu_get_phys_page_debug,
.vmsd = &vmstate_openrisc_cpu,
};
#endif
@@ -209,7 +210,6 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = openrisc_cpu_gdb_read_register;
cc->gdb_write_register = openrisc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
cc->sysemu_ops = &openrisc_sysemu_ops;
#endif
cc->gdb_num_core_regs = 32 + 3;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a6b1ff93299..14dc8583615 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -582,6 +582,7 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps riscv_sysemu_ops = {
+ .get_phys_page_debug = riscv_cpu_get_phys_page_debug,
/* For now, mark unmigratable: */
.vmsd = &vmstate_riscv_cpu,
};
@@ -628,7 +629,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
cc->sysemu_ops = &riscv_sysemu_ops;
#endif
cc->gdb_arch_name = riscv_gdb_arch_name;
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index f293f3630d0..5f8226ed31c 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -180,6 +180,7 @@ static const VMStateDescription vmstate_rx_cpu = {
};
static const struct SysemuCPUOps rx_sysemu_ops = {
+ .get_phys_page_debug = rx_cpu_get_phys_page_debug,
.vmsd = &vmstate_rx_cpu,
};
#endif
@@ -218,7 +219,6 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
#endif
cc->gdb_read_register = rx_cpu_gdb_read_register;
cc->gdb_write_register = rx_cpu_gdb_write_register;
- cc->get_phys_page_debug = rx_cpu_get_phys_page_debug;
cc->disas_set_info = rx_cpu_disas_set_info;
cc->gdb_num_core_regs = 26;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 2b249f47eb9..96e8342fb96 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -479,6 +479,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps s390_sysemu_ops = {
+ .get_phys_page_debug = s390_cpu_get_phys_page_debug,
.get_crash_info = s390_cpu_get_crash_info,
.write_elf64_note = s390_cpu_write_elf64_note,
.vmsd = &vmstate_s390_cpu,
@@ -524,7 +525,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = s390_cpu_gdb_read_register;
cc->gdb_write_register = s390_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
cc->sysemu_ops = &s390_sysemu_ops;
#endif
cc->disas_set_info = s390_cpu_disas_set_info;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 8c1d0ba53b1..2f7b43a0353 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -225,6 +225,7 @@ static const VMStateDescription vmstate_sh_cpu = {
};
static const struct SysemuCPUOps sh4_sysemu_ops = {
+ .get_phys_page_debug = superh_cpu_get_phys_page_debug,
.vmsd = &vmstate_sh_cpu,
};
#endif
@@ -262,7 +263,6 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = superh_cpu_gdb_read_register;
cc->gdb_write_register = superh_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
cc->sysemu_ops = &sh4_sysemu_ops;
#endif
cc->disas_set_info = superh_cpu_disas_set_info;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index f5862e74baf..b13d586f79d 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -850,6 +850,7 @@ static Property sparc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps sparc_sysemu_ops = {
+ .get_phys_page_debug = sparc_cpu_get_phys_page_debug,
.vmsd = &vmstate_sparc_cpu,
};
#endif
@@ -894,7 +895,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = sparc_cpu_gdb_read_register;
cc->gdb_write_register = sparc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
cc->sysemu_ops = &sparc_sysemu_ops;
#endif
cc->disas_set_info = cpu_sparc_disas_set_info;
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 9374f8440a0..b1776c10205 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -149,6 +149,7 @@ static const VMStateDescription vmstate_tricore_cpu = {
};
static const struct SysemuCPUOps tricore_sysemu_ops = {
+ .get_phys_page_debug = tricore_cpu_get_phys_page_debug,
.vmsd = &vmstate_tricore_cpu,
};
@@ -180,7 +181,6 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
cc->dump_state = tricore_cpu_dump_state;
cc->set_pc = tricore_cpu_set_pc;
- cc->get_phys_page_debug = tricore_cpu_get_phys_page_debug;
cc->sysemu_ops = &tricore_sysemu_ops;
cc->tcg_ops = &tricore_tcg_ops;
}
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index 345b6e9e417..1b2bb25f508 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -121,6 +121,7 @@ static const VMStateDescription vmstate_uc32_cpu = {
};
static const struct SysemuCPUOps uc32_sysemu_ops = {
+ .get_phys_page_debug = uc32_cpu_get_phys_page_debug,
.vmsd = &vmstate_uc32_cpu,
};
@@ -149,7 +150,6 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->has_work = uc32_cpu_has_work;
cc->dump_state = uc32_cpu_dump_state;
cc->set_pc = uc32_cpu_set_pc;
- cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
cc->sysemu_ops = &uc32_sysemu_ops;
cc->tcg_ops = &uc32_tcg_ops;
}
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index fd65246015f..8b1d827e747 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -183,6 +183,7 @@ static const VMStateDescription vmstate_xtensa_cpu = {
};
static const struct SysemuCPUOps xtensa_sysemu_ops = {
+ .get_phys_page_debug = xtensa_cpu_get_phys_page_debug,
.vmsd = &vmstate_xtensa_cpu,
};
#endif
@@ -222,7 +223,6 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_stop_before_watchpoint = true;
#ifndef CONFIG_USER_ONLY
cc->sysemu_ops = &xtensa_sysemu_ops;
- cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
#endif
cc->disas_set_info = xtensa_cpu_disas_set_info;
cc->tcg_ops = &xtensa_tcg_ops;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 598304bd636..cd22a1ce3f0 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10845,6 +10845,7 @@ static Property ppc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps ppc_sysemu_ops = {
+ .get_phys_page_debug = ppc_cpu_get_phys_page_debug,
.write_elf32_note = ppc32_cpu_write_elf32_note,
.write_elf64_note = ppc64_cpu_write_elf64_note,
.virtio_is_big_endian = ppc_cpu_is_big_endian,
@@ -10893,7 +10894,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = ppc_cpu_gdb_read_register;
cc->gdb_write_register = ppc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
cc->sysemu_ops = &ppc_sysemu_ops;
#endif
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v4 14/28] cpu: Move CPUClass::get_memory_mapping to SysemuCPUOps
2021-03-03 21:46 ` Philippe Mathieu-Daudé
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Claudio Fontana, qemu-arm, Peter Maydell, Paolo Bonzini,
Richard Henderson, qemu-s390x, Thomas Huth, qemu-ppc,
Laurent Vivier, Cornelia Huck, Alex Bennée,
Philippe Mathieu-Daudé, Eduardo Habkost, Marcel Apfelbaum
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 3 ---
include/hw/core/sysemu-cpu-ops.h | 5 +++++
hw/core/cpu.c | 4 ++--
target/i386/cpu.c | 2 +-
4 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 9a86c707cf7..8af78cdde23 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -94,7 +94,6 @@ struct AccelCPUClass;
* @dump_statistics: Callback for dumping statistics.
* @get_arch_id: Callback for getting architecture-dependent CPU ID.
* @get_paging_enabled: Callback for inquiring whether paging is enabled.
- * @get_memory_mapping: Callback for obtaining the memory mappings.
* @set_pc: Callback for setting the Program Counter register. This
* should have the semantics used by the target architecture when
* setting the PC from a source such as an ELF file entry point;
@@ -138,8 +137,6 @@ struct CPUClass {
void (*dump_statistics)(CPUState *cpu, int flags);
int64_t (*get_arch_id)(CPUState *cpu);
bool (*get_paging_enabled)(const CPUState *cpu);
- void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
- Error **errp);
void (*set_pc)(CPUState *cpu, vaddr value);
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 0c8f616a565..460e7d63b0c 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,11 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @get_memory_mapping: Callback for obtaining the memory mappings.
+ */
+ void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
+ Error **errp);
/**
* @get_phys_page_debug: Callback for obtaining a physical address.
*/
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 6932781425a..339bdfadd7a 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -83,8 +83,8 @@ void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->get_memory_mapping) {
- cc->get_memory_mapping(cpu, list, errp);
+ if (cc->sysemu_ops->get_memory_mapping) {
+ cc->sysemu_ops->get_memory_mapping(cpu, list, errp);
return;
}
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 0de4ee18bee..b2d3debd1f2 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7388,6 +7388,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps i386_sysemu_ops = {
+ .get_memory_mapping = x86_cpu_get_memory_mapping,
.get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug,
.asidx_from_attrs = x86_asidx_from_attrs,
.get_crash_info = x86_cpu_get_crash_info,
@@ -7431,7 +7432,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->get_paging_enabled = x86_cpu_get_paging_enabled;
#ifndef CONFIG_USER_ONLY
- cc->get_memory_mapping = x86_cpu_get_memory_mapping;
cc->sysemu_ops = &i386_sysemu_ops;
#endif /* !CONFIG_USER_ONLY */
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread* [PATCH v4 14/28] cpu: Move CPUClass::get_memory_mapping to SysemuCPUOps
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Thomas Huth, Eduardo Habkost, Cornelia Huck,
Richard Henderson, Laurent Vivier, Philippe Mathieu-Daudé,
qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana, Paolo Bonzini,
Alex Bennée
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 3 ---
include/hw/core/sysemu-cpu-ops.h | 5 +++++
hw/core/cpu.c | 4 ++--
target/i386/cpu.c | 2 +-
4 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 9a86c707cf7..8af78cdde23 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -94,7 +94,6 @@ struct AccelCPUClass;
* @dump_statistics: Callback for dumping statistics.
* @get_arch_id: Callback for getting architecture-dependent CPU ID.
* @get_paging_enabled: Callback for inquiring whether paging is enabled.
- * @get_memory_mapping: Callback for obtaining the memory mappings.
* @set_pc: Callback for setting the Program Counter register. This
* should have the semantics used by the target architecture when
* setting the PC from a source such as an ELF file entry point;
@@ -138,8 +137,6 @@ struct CPUClass {
void (*dump_statistics)(CPUState *cpu, int flags);
int64_t (*get_arch_id)(CPUState *cpu);
bool (*get_paging_enabled)(const CPUState *cpu);
- void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
- Error **errp);
void (*set_pc)(CPUState *cpu, vaddr value);
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 0c8f616a565..460e7d63b0c 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,11 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @get_memory_mapping: Callback for obtaining the memory mappings.
+ */
+ void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
+ Error **errp);
/**
* @get_phys_page_debug: Callback for obtaining a physical address.
*/
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 6932781425a..339bdfadd7a 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -83,8 +83,8 @@ void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->get_memory_mapping) {
- cc->get_memory_mapping(cpu, list, errp);
+ if (cc->sysemu_ops->get_memory_mapping) {
+ cc->sysemu_ops->get_memory_mapping(cpu, list, errp);
return;
}
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 0de4ee18bee..b2d3debd1f2 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7388,6 +7388,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps i386_sysemu_ops = {
+ .get_memory_mapping = x86_cpu_get_memory_mapping,
.get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug,
.asidx_from_attrs = x86_asidx_from_attrs,
.get_crash_info = x86_cpu_get_crash_info,
@@ -7431,7 +7432,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->get_paging_enabled = x86_cpu_get_paging_enabled;
#ifndef CONFIG_USER_ONLY
- cc->get_memory_mapping = x86_cpu_get_memory_mapping;
cc->sysemu_ops = &i386_sysemu_ops;
#endif /* !CONFIG_USER_ONLY */
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v4 15/28] cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps
2021-03-03 21:46 ` Philippe Mathieu-Daudé
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Claudio Fontana, qemu-arm, Peter Maydell, Paolo Bonzini,
Richard Henderson, qemu-s390x, Thomas Huth, qemu-ppc,
Laurent Vivier, Cornelia Huck, Alex Bennée,
Philippe Mathieu-Daudé, Eduardo Habkost, Marcel Apfelbaum
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 2 --
include/hw/core/sysemu-cpu-ops.h | 4 ++++
hw/core/cpu.c | 4 ++--
target/i386/cpu.c | 4 +++-
4 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 8af78cdde23..960846d2b64 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -93,7 +93,6 @@ struct AccelCPUClass;
* @dump_state: Callback for dumping state.
* @dump_statistics: Callback for dumping statistics.
* @get_arch_id: Callback for getting architecture-dependent CPU ID.
- * @get_paging_enabled: Callback for inquiring whether paging is enabled.
* @set_pc: Callback for setting the Program Counter register. This
* should have the semantics used by the target architecture when
* setting the PC from a source such as an ELF file entry point;
@@ -136,7 +135,6 @@ struct CPUClass {
void (*dump_state)(CPUState *cpu, FILE *, int flags);
void (*dump_statistics)(CPUState *cpu, int flags);
int64_t (*get_arch_id)(CPUState *cpu);
- bool (*get_paging_enabled)(const CPUState *cpu);
void (*set_pc)(CPUState *cpu, vaddr value);
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 460e7d63b0c..3f9a5199dd1 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -21,6 +21,10 @@ typedef struct SysemuCPUOps {
*/
void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
Error **errp);
+ /**
+ * @get_paging_enabled: Callback for inquiring whether paging is enabled.
+ */
+ bool (*get_paging_enabled)(const CPUState *cpu);
/**
* @get_phys_page_debug: Callback for obtaining a physical address.
*/
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 339bdfadd7a..7a8487d468f 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -71,8 +71,8 @@ bool cpu_paging_enabled(const CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->get_paging_enabled) {
- return cc->get_paging_enabled(cpu);
+ if (cc->sysemu_ops->get_paging_enabled) {
+ return cc->sysemu_ops->get_paging_enabled(cpu);
}
return false;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index b2d3debd1f2..994d58aa754 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7157,12 +7157,14 @@ static int64_t x86_cpu_get_arch_id(CPUState *cs)
return cpu->apic_id;
}
+#if !defined(CONFIG_USER_ONLY)
static bool x86_cpu_get_paging_enabled(const CPUState *cs)
{
X86CPU *cpu = X86_CPU(cs);
return cpu->env.cr[0] & CR0_PG_MASK;
}
+#endif /* !CONFIG_USER_ONLY */
static void x86_cpu_set_pc(CPUState *cs, vaddr value)
{
@@ -7389,6 +7391,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps i386_sysemu_ops = {
.get_memory_mapping = x86_cpu_get_memory_mapping,
+ .get_paging_enabled = x86_cpu_get_paging_enabled,
.get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug,
.asidx_from_attrs = x86_asidx_from_attrs,
.get_crash_info = x86_cpu_get_crash_info,
@@ -7429,7 +7432,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = x86_cpu_gdb_read_register;
cc->gdb_write_register = x86_cpu_gdb_write_register;
cc->get_arch_id = x86_cpu_get_arch_id;
- cc->get_paging_enabled = x86_cpu_get_paging_enabled;
#ifndef CONFIG_USER_ONLY
cc->sysemu_ops = &i386_sysemu_ops;
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread* [PATCH v4 15/28] cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Thomas Huth, Eduardo Habkost, Cornelia Huck,
Richard Henderson, Laurent Vivier, Philippe Mathieu-Daudé,
qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana, Paolo Bonzini,
Alex Bennée
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 2 --
include/hw/core/sysemu-cpu-ops.h | 4 ++++
hw/core/cpu.c | 4 ++--
target/i386/cpu.c | 4 +++-
4 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 8af78cdde23..960846d2b64 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -93,7 +93,6 @@ struct AccelCPUClass;
* @dump_state: Callback for dumping state.
* @dump_statistics: Callback for dumping statistics.
* @get_arch_id: Callback for getting architecture-dependent CPU ID.
- * @get_paging_enabled: Callback for inquiring whether paging is enabled.
* @set_pc: Callback for setting the Program Counter register. This
* should have the semantics used by the target architecture when
* setting the PC from a source such as an ELF file entry point;
@@ -136,7 +135,6 @@ struct CPUClass {
void (*dump_state)(CPUState *cpu, FILE *, int flags);
void (*dump_statistics)(CPUState *cpu, int flags);
int64_t (*get_arch_id)(CPUState *cpu);
- bool (*get_paging_enabled)(const CPUState *cpu);
void (*set_pc)(CPUState *cpu, vaddr value);
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 460e7d63b0c..3f9a5199dd1 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -21,6 +21,10 @@ typedef struct SysemuCPUOps {
*/
void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
Error **errp);
+ /**
+ * @get_paging_enabled: Callback for inquiring whether paging is enabled.
+ */
+ bool (*get_paging_enabled)(const CPUState *cpu);
/**
* @get_phys_page_debug: Callback for obtaining a physical address.
*/
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 339bdfadd7a..7a8487d468f 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -71,8 +71,8 @@ bool cpu_paging_enabled(const CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->get_paging_enabled) {
- return cc->get_paging_enabled(cpu);
+ if (cc->sysemu_ops->get_paging_enabled) {
+ return cc->sysemu_ops->get_paging_enabled(cpu);
}
return false;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index b2d3debd1f2..994d58aa754 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7157,12 +7157,14 @@ static int64_t x86_cpu_get_arch_id(CPUState *cs)
return cpu->apic_id;
}
+#if !defined(CONFIG_USER_ONLY)
static bool x86_cpu_get_paging_enabled(const CPUState *cs)
{
X86CPU *cpu = X86_CPU(cs);
return cpu->env.cr[0] & CR0_PG_MASK;
}
+#endif /* !CONFIG_USER_ONLY */
static void x86_cpu_set_pc(CPUState *cs, vaddr value)
{
@@ -7389,6 +7391,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps i386_sysemu_ops = {
.get_memory_mapping = x86_cpu_get_memory_mapping,
+ .get_paging_enabled = x86_cpu_get_paging_enabled,
.get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug,
.asidx_from_attrs = x86_asidx_from_attrs,
.get_crash_info = x86_cpu_get_crash_info,
@@ -7429,7 +7432,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = x86_cpu_gdb_read_register;
cc->gdb_write_register = x86_cpu_gdb_write_register;
cc->get_arch_id = x86_cpu_get_arch_id;
- cc->get_paging_enabled = x86_cpu_get_paging_enabled;
#ifndef CONFIG_USER_ONLY
cc->sysemu_ops = &i386_sysemu_ops;
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v4 16/28] cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c
2021-03-03 21:46 ` Philippe Mathieu-Daudé
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Claudio Fontana, qemu-arm, Peter Maydell, Paolo Bonzini,
Richard Henderson, qemu-s390x, Thomas Huth, qemu-ppc,
Laurent Vivier, Cornelia Huck, Alex Bennée,
Philippe Mathieu-Daudé, Eduardo Habkost, Marcel Apfelbaum,
Michael Rolnik, Sarah Harris, Edgar E. Iglesias, Taylor Simpson,
Michael Walle, Aurelien Jarno, Jiaxun Yang, Aleksandar Rikalo,
Anthony Green, Chris Wulff, Marek Vasut, Stafford Horne,
David Gibson, Greg Kurz, Palmer Dabbelt, Alistair Francis,
Sagar Karandikar, Bastian Koppelmann, Yoshinori Sato,
David Hildenbrand, Mark Cave-Ayland, Artyom Tarasenko,
Guan Xuetao, Max Filippov, open list:RISC-V TCG CPUs
Somehow similar to commit 78271684719 ("cpu: tcg_ops: move to
tcg-cpu-ops.h, keep a pointer in CPUClass"):
We cannot in principle make the SysEmu Operations field definitions
conditional on CONFIG_SOFTMMU in code that is included by both
common_ss and specific_ss modules.
Therefore, what we can do safely to restrict the SysEmu fields to
system emulation builds, is to move all sysemu operations into a
separate header file, which is only included by system-specific code.
This leaves just a NULL pointer in the cpu.h for the user-mode builds.
Inspired-by: Claudio Fontana <cfontana@suse.de>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 3 ++-
target/alpha/cpu.h | 3 +++
target/arm/cpu.h | 3 +++
target/avr/cpu.h | 1 +
target/cris/cpu.h | 3 +++
target/hexagon/cpu.h | 3 +++
target/hppa/cpu.h | 3 +++
target/i386/cpu.h | 3 +++
target/lm32/cpu.h | 3 +++
target/m68k/cpu.h | 3 +++
target/microblaze/cpu.h | 1 +
target/mips/cpu.h | 3 +++
target/moxie/cpu.h | 3 +++
target/nios2/cpu.h | 1 +
target/openrisc/cpu.h | 3 +++
target/ppc/cpu.h | 3 +++
target/riscv/cpu.h | 3 +++
target/rx/cpu.h | 1 +
target/s390x/cpu.h | 3 +++
target/sh4/cpu.h | 3 +++
target/sparc/cpu.h | 3 +++
target/tilegx/cpu.h | 3 +++
target/tricore/cpu.h | 3 +++
target/unicore32/cpu.h | 3 +++
target/xtensa/cpu.h | 3 +++
cpu.c | 1 +
hw/core/cpu.c | 1 +
27 files changed, 68 insertions(+), 1 deletion(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 960846d2b64..fe4206b540f 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -80,7 +80,8 @@ struct TCGCPUOps;
/* see accel-cpu.h */
struct AccelCPUClass;
-#include "hw/core/sysemu-cpu-ops.h"
+/* see sysemu-cpu-ops.h */
+struct SysemuCPUOps;
/**
* CPUClass:
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index 82df108967b..f1218a27706 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -22,6 +22,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* Alpha processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index efa1618c4d5..265d00d55dd 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -25,6 +25,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "qapi/qapi-types-common.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* ARM processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index d148e8c75a4..e0419649fa7 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -23,6 +23,7 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#include "hw/core/sysemu-cpu-ops.h"
#ifdef CONFIG_USER_ONLY
#error "AVR 8-bit does not support user mode"
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index d3b64929096..4450f2268ea 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -23,6 +23,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define EXCP_NMI 1
#define EXCP_GURU 2
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index e04eac591c8..2a878e77f08 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -26,6 +26,9 @@ typedef struct CPUHexagonState CPUHexagonState;
#include "qemu-common.h"
#include "exec/cpu-defs.h"
#include "hex_regs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define NUM_PREGS 4
#define TOTAL_PER_THREAD_REGS 64
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 61178fa6a2a..94d2d4701c4 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -23,6 +23,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "exec/memory.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* PA-RISC 1.x processors have a strong memory model. */
/* ??? While we do not yet implement PA-RISC 2.0, those processors have
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index b4b136cd0d1..06965f11100 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -25,6 +25,9 @@
#include "kvm/hyperv-proto.h"
#include "exec/cpu-defs.h"
#include "qapi/qapi-types-common.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* The x86 has a strong memory model with some store-after-load re-ordering */
#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h
index ea7c01ca8b0..034183dad30 100644
--- a/target/lm32/cpu.h
+++ b/target/lm32/cpu.h
@@ -22,6 +22,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
typedef struct CPULM32State CPULM32State;
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 7c3feeaf8a6..4b0a19bdf44 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -23,6 +23,9 @@
#include "exec/cpu-defs.h"
#include "cpu-qom.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define OS_BYTE 0
#define OS_WORD 1
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index e4bba8a7551..3f5c2e048e5 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -26,6 +26,7 @@
typedef struct CPUMBState CPUMBState;
#if !defined(CONFIG_USER_ONLY)
+#include "hw/core/sysemu-cpu-ops.h"
#include "mmu.h"
#endif
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 075c24abdad..923ab71f8d7 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -6,6 +6,9 @@
#include "fpu/softfloat-types.h"
#include "hw/clock.h"
#include "mips-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define TCG_GUEST_DEFAULT_MO (0)
diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h
index bd6ab66084d..7a0a5e95d01 100644
--- a/target/moxie/cpu.h
+++ b/target/moxie/cpu.h
@@ -22,6 +22,9 @@
#include "exec/cpu-defs.h"
#include "qom/object.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define MOXIE_EX_DIV0 0
#define MOXIE_EX_BAD 1
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 2ab82fdc713..1b88b027063 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -27,6 +27,7 @@
typedef struct CPUNios2State CPUNios2State;
#if !defined(CONFIG_USER_ONLY)
+#include "hw/core/sysemu-cpu-ops.h"
#include "mmu.h"
#endif
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 82cbaeb4f84..2a6f9f48547 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -23,6 +23,9 @@
#include "exec/cpu-defs.h"
#include "hw/core/cpu.h"
#include "qom/object.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */
struct OpenRISCCPU;
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index e73416da68d..f889c28e548 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -24,6 +24,9 @@
#include "exec/cpu-defs.h"
#include "cpu-qom.h"
#include "qom/object.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define TCG_GUEST_DEFAULT_MO 0
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 02758ae0eb4..254eefaf824 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -25,6 +25,9 @@
#include "exec/cpu-defs.h"
#include "fpu/softfloat-types.h"
#include "qom/object.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define TCG_GUEST_DEFAULT_MO 0
diff --git a/target/rx/cpu.h b/target/rx/cpu.h
index 0b4b998c7be..d9b7b63716a 100644
--- a/target/rx/cpu.h
+++ b/target/rx/cpu.h
@@ -25,6 +25,7 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#include "hw/core/sysemu-cpu-ops.h"
/* PSW define */
REG32(PSW, 0)
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 60d434d5edd..2ca6a4f559f 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -28,6 +28,9 @@
#include "cpu-qom.h"
#include "cpu_models.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define ELF_MACHINE_UNAME "S390X"
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 714e3b56413..07ed2f3e206 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -22,6 +22,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* CPU Subtypes */
#define SH_CPU_SH7750 (1 << 0)
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 4b2290650be..237ffc4fe66 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -4,6 +4,9 @@
#include "qemu/bswap.h"
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#if !defined(TARGET_SPARC64)
#define TARGET_DPREGS 16
diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h
index 7d8e44d12e4..54bdbf0ca1e 100644
--- a/target/tilegx/cpu.h
+++ b/target/tilegx/cpu.h
@@ -22,6 +22,9 @@
#include "exec/cpu-defs.h"
#include "qom/object.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* TILE-Gx common register alias */
#define TILEGX_R_RE 0 /* 0 register, for function/syscall return value */
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index b82349d1b10..cb0b989953e 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -23,6 +23,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "tricore-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
struct tricore_boot_info;
diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h
index 7a32e086ed3..de475d0fc2e 100644
--- a/target/unicore32/cpu.h
+++ b/target/unicore32/cpu.h
@@ -14,6 +14,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
typedef struct CPUUniCore32State {
/* Regs for current mode. */
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 3bd4f691c1a..ea4ee5338f3 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -31,6 +31,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "xtensa-isa.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* Xtensa processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
diff --git a/cpu.c b/cpu.c
index 64e17537e21..29dafee581f 100644
--- a/cpu.c
+++ b/cpu.c
@@ -29,6 +29,7 @@
#ifdef CONFIG_USER_ONLY
#include "qemu.h"
#else
+#include "hw/core/sysemu-cpu-ops.h"
#include "exec/address-spaces.h"
#endif
#include "sysemu/tcg.h"
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 7a8487d468f..da7543be514 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -35,6 +35,7 @@
#include "trace/trace-root.h"
#include "qemu/plugin.h"
#include "sysemu/hw_accel.h"
+#include "hw/core/sysemu-cpu-ops.h"
CPUState *cpu_by_arch_id(int64_t id)
{
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread* [PATCH v4 16/28] cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Sarah Harris, Chris Wulff, Sagar Karandikar,
David Hildenbrand, Anthony Green, Mark Cave-Ayland,
Aleksandar Rikalo, Philippe Mathieu-Daudé, Max Filippov,
Taylor Simpson, Alistair Francis, Edgar E. Iglesias, Guan Xuetao,
Marek Vasut, Yoshinori Sato, Claudio Fontana, Palmer Dabbelt,
Artyom Tarasenko, Thomas Huth, Eduardo Habkost, Richard Henderson,
Greg Kurz, qemu-s390x, qemu-arm, Michael Rolnik, Stafford Horne,
Alex Bennée, David Gibson, open list:RISC-V TCG CPUs,
Bastian Koppelmann, Cornelia Huck, Laurent Vivier, Michael Walle,
qemu-ppc, Paolo Bonzini, Aurelien Jarno
Somehow similar to commit 78271684719 ("cpu: tcg_ops: move to
tcg-cpu-ops.h, keep a pointer in CPUClass"):
We cannot in principle make the SysEmu Operations field definitions
conditional on CONFIG_SOFTMMU in code that is included by both
common_ss and specific_ss modules.
Therefore, what we can do safely to restrict the SysEmu fields to
system emulation builds, is to move all sysemu operations into a
separate header file, which is only included by system-specific code.
This leaves just a NULL pointer in the cpu.h for the user-mode builds.
Inspired-by: Claudio Fontana <cfontana@suse.de>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 3 ++-
target/alpha/cpu.h | 3 +++
target/arm/cpu.h | 3 +++
target/avr/cpu.h | 1 +
target/cris/cpu.h | 3 +++
target/hexagon/cpu.h | 3 +++
target/hppa/cpu.h | 3 +++
target/i386/cpu.h | 3 +++
target/lm32/cpu.h | 3 +++
target/m68k/cpu.h | 3 +++
target/microblaze/cpu.h | 1 +
target/mips/cpu.h | 3 +++
target/moxie/cpu.h | 3 +++
target/nios2/cpu.h | 1 +
target/openrisc/cpu.h | 3 +++
target/ppc/cpu.h | 3 +++
target/riscv/cpu.h | 3 +++
target/rx/cpu.h | 1 +
target/s390x/cpu.h | 3 +++
target/sh4/cpu.h | 3 +++
target/sparc/cpu.h | 3 +++
target/tilegx/cpu.h | 3 +++
target/tricore/cpu.h | 3 +++
target/unicore32/cpu.h | 3 +++
target/xtensa/cpu.h | 3 +++
cpu.c | 1 +
hw/core/cpu.c | 1 +
27 files changed, 68 insertions(+), 1 deletion(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 960846d2b64..fe4206b540f 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -80,7 +80,8 @@ struct TCGCPUOps;
/* see accel-cpu.h */
struct AccelCPUClass;
-#include "hw/core/sysemu-cpu-ops.h"
+/* see sysemu-cpu-ops.h */
+struct SysemuCPUOps;
/**
* CPUClass:
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index 82df108967b..f1218a27706 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -22,6 +22,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* Alpha processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index efa1618c4d5..265d00d55dd 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -25,6 +25,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "qapi/qapi-types-common.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* ARM processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index d148e8c75a4..e0419649fa7 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -23,6 +23,7 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#include "hw/core/sysemu-cpu-ops.h"
#ifdef CONFIG_USER_ONLY
#error "AVR 8-bit does not support user mode"
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index d3b64929096..4450f2268ea 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -23,6 +23,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define EXCP_NMI 1
#define EXCP_GURU 2
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index e04eac591c8..2a878e77f08 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -26,6 +26,9 @@ typedef struct CPUHexagonState CPUHexagonState;
#include "qemu-common.h"
#include "exec/cpu-defs.h"
#include "hex_regs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define NUM_PREGS 4
#define TOTAL_PER_THREAD_REGS 64
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 61178fa6a2a..94d2d4701c4 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -23,6 +23,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "exec/memory.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* PA-RISC 1.x processors have a strong memory model. */
/* ??? While we do not yet implement PA-RISC 2.0, those processors have
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index b4b136cd0d1..06965f11100 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -25,6 +25,9 @@
#include "kvm/hyperv-proto.h"
#include "exec/cpu-defs.h"
#include "qapi/qapi-types-common.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* The x86 has a strong memory model with some store-after-load re-ordering */
#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h
index ea7c01ca8b0..034183dad30 100644
--- a/target/lm32/cpu.h
+++ b/target/lm32/cpu.h
@@ -22,6 +22,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
typedef struct CPULM32State CPULM32State;
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 7c3feeaf8a6..4b0a19bdf44 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -23,6 +23,9 @@
#include "exec/cpu-defs.h"
#include "cpu-qom.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define OS_BYTE 0
#define OS_WORD 1
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index e4bba8a7551..3f5c2e048e5 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -26,6 +26,7 @@
typedef struct CPUMBState CPUMBState;
#if !defined(CONFIG_USER_ONLY)
+#include "hw/core/sysemu-cpu-ops.h"
#include "mmu.h"
#endif
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 075c24abdad..923ab71f8d7 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -6,6 +6,9 @@
#include "fpu/softfloat-types.h"
#include "hw/clock.h"
#include "mips-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define TCG_GUEST_DEFAULT_MO (0)
diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h
index bd6ab66084d..7a0a5e95d01 100644
--- a/target/moxie/cpu.h
+++ b/target/moxie/cpu.h
@@ -22,6 +22,9 @@
#include "exec/cpu-defs.h"
#include "qom/object.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define MOXIE_EX_DIV0 0
#define MOXIE_EX_BAD 1
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 2ab82fdc713..1b88b027063 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -27,6 +27,7 @@
typedef struct CPUNios2State CPUNios2State;
#if !defined(CONFIG_USER_ONLY)
+#include "hw/core/sysemu-cpu-ops.h"
#include "mmu.h"
#endif
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 82cbaeb4f84..2a6f9f48547 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -23,6 +23,9 @@
#include "exec/cpu-defs.h"
#include "hw/core/cpu.h"
#include "qom/object.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */
struct OpenRISCCPU;
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index e73416da68d..f889c28e548 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -24,6 +24,9 @@
#include "exec/cpu-defs.h"
#include "cpu-qom.h"
#include "qom/object.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define TCG_GUEST_DEFAULT_MO 0
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 02758ae0eb4..254eefaf824 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -25,6 +25,9 @@
#include "exec/cpu-defs.h"
#include "fpu/softfloat-types.h"
#include "qom/object.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define TCG_GUEST_DEFAULT_MO 0
diff --git a/target/rx/cpu.h b/target/rx/cpu.h
index 0b4b998c7be..d9b7b63716a 100644
--- a/target/rx/cpu.h
+++ b/target/rx/cpu.h
@@ -25,6 +25,7 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#include "hw/core/sysemu-cpu-ops.h"
/* PSW define */
REG32(PSW, 0)
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 60d434d5edd..2ca6a4f559f 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -28,6 +28,9 @@
#include "cpu-qom.h"
#include "cpu_models.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define ELF_MACHINE_UNAME "S390X"
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 714e3b56413..07ed2f3e206 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -22,6 +22,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* CPU Subtypes */
#define SH_CPU_SH7750 (1 << 0)
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 4b2290650be..237ffc4fe66 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -4,6 +4,9 @@
#include "qemu/bswap.h"
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#if !defined(TARGET_SPARC64)
#define TARGET_DPREGS 16
diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h
index 7d8e44d12e4..54bdbf0ca1e 100644
--- a/target/tilegx/cpu.h
+++ b/target/tilegx/cpu.h
@@ -22,6 +22,9 @@
#include "exec/cpu-defs.h"
#include "qom/object.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* TILE-Gx common register alias */
#define TILEGX_R_RE 0 /* 0 register, for function/syscall return value */
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index b82349d1b10..cb0b989953e 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -23,6 +23,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "tricore-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
struct tricore_boot_info;
diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h
index 7a32e086ed3..de475d0fc2e 100644
--- a/target/unicore32/cpu.h
+++ b/target/unicore32/cpu.h
@@ -14,6 +14,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
typedef struct CPUUniCore32State {
/* Regs for current mode. */
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 3bd4f691c1a..ea4ee5338f3 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -31,6 +31,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "xtensa-isa.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* Xtensa processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
diff --git a/cpu.c b/cpu.c
index 64e17537e21..29dafee581f 100644
--- a/cpu.c
+++ b/cpu.c
@@ -29,6 +29,7 @@
#ifdef CONFIG_USER_ONLY
#include "qemu.h"
#else
+#include "hw/core/sysemu-cpu-ops.h"
#include "exec/address-spaces.h"
#endif
#include "sysemu/tcg.h"
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 7a8487d468f..da7543be514 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -35,6 +35,7 @@
#include "trace/trace-root.h"
#include "qemu/plugin.h"
#include "sysemu/hw_accel.h"
+#include "hw/core/sysemu-cpu-ops.h"
CPUState *cpu_by_arch_id(int64_t id)
{
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread* RE: [PATCH v4 16/28] cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c
2021-03-03 21:46 ` Philippe Mathieu-Daudé
@ 2021-03-03 22:27 ` Taylor Simpson
-1 siblings, 0 replies; 79+ messages in thread
From: Taylor Simpson @ 2021-03-03 22:27 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel@nongnu.org
Cc: Claudio Fontana, qemu-arm@nongnu.org, Peter Maydell,
Paolo Bonzini, Richard Henderson, qemu-s390x@nongnu.org,
Thomas Huth, qemu-ppc@nongnu.org, Laurent Vivier, Cornelia Huck,
Alex Bennée, Eduardo Habkost, Marcel Apfelbaum,
Michael Rolnik, Sarah Harris, Edgar E. Iglesias, Michael Walle,
Aurelien Jarno, Jiaxun Yang, Aleksandar Rikalo, Anthony Green,
Chris Wulff, Marek Vasut, Stafford Horne, David Gibson, Greg Kurz,
Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, Yoshinori Sato, David Hildenbrand,
Mark Cave-Ayland, Artyom Tarasenko, Guan Xuetao, Max Filippov,
open list:RISC-V TCG CPUs
> -----Original Message-----
> From: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> On
> Behalf Of Philippe Mathieu-Daudé
> Sent: Wednesday, March 3, 2021 3:47 PM
> To: qemu-devel@nongnu.org
> Cc: Claudio Fontana <cfontana@suse.de>; qemu-arm@nongnu.org; Peter
> Maydell <peter.maydell@linaro.org>; Paolo Bonzini
> <pbonzini@redhat.com>; Richard Henderson
> <richard.henderson@linaro.org>; qemu-s390x@nongnu.org; Thomas Huth
> <thuth@redhat.com>; qemu-ppc@nongnu.org; Laurent Vivier
> <laurent@vivier.eu>; Cornelia Huck <cohuck@redhat.com>; Alex Bennée
> <alex.bennee@linaro.org>; Philippe Mathieu-Daudé <f4bug@amsat.org>;
> Eduardo Habkost <ehabkost@redhat.com>; Marcel Apfelbaum
> <marcel.apfelbaum@gmail.com>; Michael Rolnik <mrolnik@gmail.com>;
> Sarah Harris <S.E.Harris@kent.ac.uk>; Edgar E. Iglesias
> <edgar.iglesias@gmail.com>; Taylor Simpson <tsimpson@quicinc.com>;
> Michael Walle <michael@walle.cc>; Aurelien Jarno <aurelien@aurel32.net>;
> Jiaxun Yang <jiaxun.yang@flygoat.com>; Aleksandar Rikalo
> <aleksandar.rikalo@syrmia.com>; Anthony Green
> <green@moxielogic.com>; Chris Wulff <crwulff@gmail.com>; Marek Vasut
> <marex@denx.de>; Stafford Horne <shorne@gmail.com>; David Gibson
> <david@gibson.dropbear.id.au>; Greg Kurz <groug@kaod.org>; Palmer
> Dabbelt <palmer@dabbelt.com>; Alistair Francis
> <Alistair.Francis@wdc.com>; Sagar Karandikar <sagark@eecs.berkeley.edu>;
> Bastian Koppelmann <kbastian@mail.uni-paderborn.de>; Yoshinori Sato
> <ysato@users.sourceforge.jp>; David Hildenbrand <david@redhat.com>;
> Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>; Artyom Tarasenko
> <atar4qemu@gmail.com>; Guan Xuetao <gxt@mprc.pku.edu.cn>; Max
> Filippov <jcmvbkbc@gmail.com>; open list:RISC-V TCG CPUs <qemu-
> riscv@nongnu.org>
> Subject: [PATCH v4 16/28] cpu: Restrict "hw/core/sysemu-cpu-ops.h" to
> target/cpu.c
>
> Somehow similar to commit 78271684719 ("cpu: tcg_ops: move to
> tcg-cpu-ops.h, keep a pointer in CPUClass"):
>
> We cannot in principle make the SysEmu Operations field definitions
> conditional on CONFIG_SOFTMMU in code that is included by both
> common_ss and specific_ss modules.
>
> Therefore, what we can do safely to restrict the SysEmu fields to
> system emulation builds, is to move all sysemu operations into a
> separate header file, which is only included by system-specific code.
>
> This leaves just a NULL pointer in the cpu.h for the user-mode builds.
>
> Inspired-by: Claudio Fontana <cfontana@suse.de>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
> index e04eac591c8..2a878e77f08 100644
> --- a/target/hexagon/cpu.h
> +++ b/target/hexagon/cpu.h
> @@ -26,6 +26,9 @@ typedef struct CPUHexagonState CPUHexagonState;
> #include "qemu-common.h"
> #include "exec/cpu-defs.h"
> #include "hex_regs.h"
> +#ifndef CONFIG_USER_ONLY
> +#include "hw/core/sysemu-cpu-ops.h"
> +#endif
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
^ permalink raw reply [flat|nested] 79+ messages in thread* RE: [PATCH v4 16/28] cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c
@ 2021-03-03 22:27 ` Taylor Simpson
0 siblings, 0 replies; 79+ messages in thread
From: Taylor Simpson @ 2021-03-03 22:27 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel@nongnu.org
Cc: Peter Maydell, Sarah Harris, Chris Wulff, Sagar Karandikar,
David Hildenbrand, Anthony Green, Mark Cave-Ayland,
Aleksandar Rikalo, Max Filippov, Alistair Francis,
Edgar E. Iglesias, Guan Xuetao, Marek Vasut, Yoshinori Sato,
Claudio Fontana, Palmer Dabbelt, Artyom Tarasenko, Thomas Huth,
Eduardo Habkost, Richard Henderson, Greg Kurz,
qemu-s390x@nongnu.org, qemu-arm@nongnu.org, Michael Rolnik,
Stafford Horne, Alex Bennée, David Gibson,
open list:RISC-V TCG CPUs, Bastian Koppelmann, Cornelia Huck,
Laurent Vivier, Michael Walle, qemu-ppc@nongnu.org, Paolo Bonzini,
Aurelien Jarno
> -----Original Message-----
> From: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> On
> Behalf Of Philippe Mathieu-Daudé
> Sent: Wednesday, March 3, 2021 3:47 PM
> To: qemu-devel@nongnu.org
> Cc: Claudio Fontana <cfontana@suse.de>; qemu-arm@nongnu.org; Peter
> Maydell <peter.maydell@linaro.org>; Paolo Bonzini
> <pbonzini@redhat.com>; Richard Henderson
> <richard.henderson@linaro.org>; qemu-s390x@nongnu.org; Thomas Huth
> <thuth@redhat.com>; qemu-ppc@nongnu.org; Laurent Vivier
> <laurent@vivier.eu>; Cornelia Huck <cohuck@redhat.com>; Alex Bennée
> <alex.bennee@linaro.org>; Philippe Mathieu-Daudé <f4bug@amsat.org>;
> Eduardo Habkost <ehabkost@redhat.com>; Marcel Apfelbaum
> <marcel.apfelbaum@gmail.com>; Michael Rolnik <mrolnik@gmail.com>;
> Sarah Harris <S.E.Harris@kent.ac.uk>; Edgar E. Iglesias
> <edgar.iglesias@gmail.com>; Taylor Simpson <tsimpson@quicinc.com>;
> Michael Walle <michael@walle.cc>; Aurelien Jarno <aurelien@aurel32.net>;
> Jiaxun Yang <jiaxun.yang@flygoat.com>; Aleksandar Rikalo
> <aleksandar.rikalo@syrmia.com>; Anthony Green
> <green@moxielogic.com>; Chris Wulff <crwulff@gmail.com>; Marek Vasut
> <marex@denx.de>; Stafford Horne <shorne@gmail.com>; David Gibson
> <david@gibson.dropbear.id.au>; Greg Kurz <groug@kaod.org>; Palmer
> Dabbelt <palmer@dabbelt.com>; Alistair Francis
> <Alistair.Francis@wdc.com>; Sagar Karandikar <sagark@eecs.berkeley.edu>;
> Bastian Koppelmann <kbastian@mail.uni-paderborn.de>; Yoshinori Sato
> <ysato@users.sourceforge.jp>; David Hildenbrand <david@redhat.com>;
> Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>; Artyom Tarasenko
> <atar4qemu@gmail.com>; Guan Xuetao <gxt@mprc.pku.edu.cn>; Max
> Filippov <jcmvbkbc@gmail.com>; open list:RISC-V TCG CPUs <qemu-
> riscv@nongnu.org>
> Subject: [PATCH v4 16/28] cpu: Restrict "hw/core/sysemu-cpu-ops.h" to
> target/cpu.c
>
> Somehow similar to commit 78271684719 ("cpu: tcg_ops: move to
> tcg-cpu-ops.h, keep a pointer in CPUClass"):
>
> We cannot in principle make the SysEmu Operations field definitions
> conditional on CONFIG_SOFTMMU in code that is included by both
> common_ss and specific_ss modules.
>
> Therefore, what we can do safely to restrict the SysEmu fields to
> system emulation builds, is to move all sysemu operations into a
> separate header file, which is only included by system-specific code.
>
> This leaves just a NULL pointer in the cpu.h for the user-mode builds.
>
> Inspired-by: Claudio Fontana <cfontana@suse.de>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
> index e04eac591c8..2a878e77f08 100644
> --- a/target/hexagon/cpu.h
> +++ b/target/hexagon/cpu.h
> @@ -26,6 +26,9 @@ typedef struct CPUHexagonState CPUHexagonState;
> #include "qemu-common.h"
> #include "exec/cpu-defs.h"
> #include "hex_regs.h"
> +#ifndef CONFIG_USER_ONLY
> +#include "hw/core/sysemu-cpu-ops.h"
> +#endif
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
^ permalink raw reply [flat|nested] 79+ messages in thread
* [PATCH v4 17/28] linux-user: Remove dead code
2021-03-03 21:46 ` Philippe Mathieu-Daudé
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Claudio Fontana, qemu-arm, Peter Maydell, Paolo Bonzini,
Richard Henderson, qemu-s390x, Thomas Huth, qemu-ppc,
Laurent Vivier, Cornelia Huck, Alex Bennée,
Philippe Mathieu-Daudé
We can not use watchpoints in user-mode emulation because we
need the softmmu slow path to detect accesses to watchpointed
memory. This code is expanded as empty stub in "hw/core/cpu.h"
anyway, so we can drop it.
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
linux-user/main.c | 5 -----
1 file changed, 5 deletions(-)
diff --git a/linux-user/main.c b/linux-user/main.c
index 81f48ff54ed..d7af3ffbc22 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -200,7 +200,6 @@ CPUArchState *cpu_copy(CPUArchState *env)
CPUState *new_cpu = cpu_create(cpu_type);
CPUArchState *new_env = new_cpu->env_ptr;
CPUBreakpoint *bp;
- CPUWatchpoint *wp;
/* Reset non arch specific state */
cpu_reset(new_cpu);
@@ -211,13 +210,9 @@ CPUArchState *cpu_copy(CPUArchState *env)
Note: Once we support ptrace with hw-debug register access, make sure
BP_CPU break/watchpoints are handled correctly on clone. */
QTAILQ_INIT(&new_cpu->breakpoints);
- QTAILQ_INIT(&new_cpu->watchpoints);
QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
}
- QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
- cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL);
- }
return new_env;
}
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread* [PATCH v4 17/28] linux-user: Remove dead code
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Thomas Huth, Cornelia Huck, Richard Henderson,
Laurent Vivier, Philippe Mathieu-Daudé, qemu-s390x, qemu-arm,
qemu-ppc, Claudio Fontana, Paolo Bonzini, Alex Bennée
We can not use watchpoints in user-mode emulation because we
need the softmmu slow path to detect accesses to watchpointed
memory. This code is expanded as empty stub in "hw/core/cpu.h"
anyway, so we can drop it.
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
linux-user/main.c | 5 -----
1 file changed, 5 deletions(-)
diff --git a/linux-user/main.c b/linux-user/main.c
index 81f48ff54ed..d7af3ffbc22 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -200,7 +200,6 @@ CPUArchState *cpu_copy(CPUArchState *env)
CPUState *new_cpu = cpu_create(cpu_type);
CPUArchState *new_env = new_cpu->env_ptr;
CPUBreakpoint *bp;
- CPUWatchpoint *wp;
/* Reset non arch specific state */
cpu_reset(new_cpu);
@@ -211,13 +210,9 @@ CPUArchState *cpu_copy(CPUArchState *env)
Note: Once we support ptrace with hw-debug register access, make sure
BP_CPU break/watchpoints are handled correctly on clone. */
QTAILQ_INIT(&new_cpu->breakpoints);
- QTAILQ_INIT(&new_cpu->watchpoints);
QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
}
- QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
- cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL);
- }
return new_env;
}
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread* Re: [PATCH v4 17/28] linux-user: Remove dead code
2021-03-03 21:46 ` Philippe Mathieu-Daudé
@ 2021-05-15 19:25 ` Laurent Vivier
-1 siblings, 0 replies; 79+ messages in thread
From: Laurent Vivier @ 2021-05-15 19:25 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Claudio Fontana, qemu-arm, Peter Maydell, Paolo Bonzini,
Richard Henderson, qemu-s390x, Thomas Huth, qemu-ppc,
Cornelia Huck, Alex Bennée
Le 03/03/2021 à 22:46, Philippe Mathieu-Daudé a écrit :
> We can not use watchpoints in user-mode emulation because we
> need the softmmu slow path to detect accesses to watchpointed
> memory. This code is expanded as empty stub in "hw/core/cpu.h"
> anyway, so we can drop it.
>
> Reviewed-by: Laurent Vivier <laurent@vivier.eu>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> linux-user/main.c | 5 -----
> 1 file changed, 5 deletions(-)
>
> diff --git a/linux-user/main.c b/linux-user/main.c
> index 81f48ff54ed..d7af3ffbc22 100644
> --- a/linux-user/main.c
> +++ b/linux-user/main.c
> @@ -200,7 +200,6 @@ CPUArchState *cpu_copy(CPUArchState *env)
> CPUState *new_cpu = cpu_create(cpu_type);
> CPUArchState *new_env = new_cpu->env_ptr;
> CPUBreakpoint *bp;
> - CPUWatchpoint *wp;
>
> /* Reset non arch specific state */
> cpu_reset(new_cpu);
> @@ -211,13 +210,9 @@ CPUArchState *cpu_copy(CPUArchState *env)
> Note: Once we support ptrace with hw-debug register access, make sure
> BP_CPU break/watchpoints are handled correctly on clone. */
> QTAILQ_INIT(&new_cpu->breakpoints);
> - QTAILQ_INIT(&new_cpu->watchpoints);
> QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
> cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
> }
> - QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
> - cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL);
> - }
>
> return new_env;
> }
>
Applied to my linux-user-for-6.1 branch.
Thanks,
Laurent
^ permalink raw reply [flat|nested] 79+ messages in thread* Re: [PATCH v4 17/28] linux-user: Remove dead code
@ 2021-05-15 19:25 ` Laurent Vivier
0 siblings, 0 replies; 79+ messages in thread
From: Laurent Vivier @ 2021-05-15 19:25 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Peter Maydell, Thomas Huth, Cornelia Huck, Richard Henderson,
qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana, Paolo Bonzini,
Alex Bennée
Le 03/03/2021 à 22:46, Philippe Mathieu-Daudé a écrit :
> We can not use watchpoints in user-mode emulation because we
> need the softmmu slow path to detect accesses to watchpointed
> memory. This code is expanded as empty stub in "hw/core/cpu.h"
> anyway, so we can drop it.
>
> Reviewed-by: Laurent Vivier <laurent@vivier.eu>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> linux-user/main.c | 5 -----
> 1 file changed, 5 deletions(-)
>
> diff --git a/linux-user/main.c b/linux-user/main.c
> index 81f48ff54ed..d7af3ffbc22 100644
> --- a/linux-user/main.c
> +++ b/linux-user/main.c
> @@ -200,7 +200,6 @@ CPUArchState *cpu_copy(CPUArchState *env)
> CPUState *new_cpu = cpu_create(cpu_type);
> CPUArchState *new_env = new_cpu->env_ptr;
> CPUBreakpoint *bp;
> - CPUWatchpoint *wp;
>
> /* Reset non arch specific state */
> cpu_reset(new_cpu);
> @@ -211,13 +210,9 @@ CPUArchState *cpu_copy(CPUArchState *env)
> Note: Once we support ptrace with hw-debug register access, make sure
> BP_CPU break/watchpoints are handled correctly on clone. */
> QTAILQ_INIT(&new_cpu->breakpoints);
> - QTAILQ_INIT(&new_cpu->watchpoints);
> QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
> cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
> }
> - QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
> - cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL);
> - }
>
> return new_env;
> }
>
Applied to my linux-user-for-6.1 branch.
Thanks,
Laurent
^ permalink raw reply [flat|nested] 79+ messages in thread
* [PATCH v4 18/28] gdbstub: Remove watchpoint dead code in gdbserver_fork()
2021-03-03 21:46 ` Philippe Mathieu-Daudé
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Claudio Fontana, qemu-arm, Peter Maydell, Paolo Bonzini,
Richard Henderson, qemu-s390x, Thomas Huth, qemu-ppc,
Laurent Vivier, Cornelia Huck, Alex Bennée,
Philippe Mathieu-Daudé, Philippe Mathieu-Daudé
gdbserver_fork() is only used in user emulation where we can not
use watchpoints because we need the softmmu slow path to detect
accesses to watchpointed memory. This code doesn't do anything as
declared as stubs in "hw/core/cpu.h". Drop it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
gdbstub.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/gdbstub.c b/gdbstub.c
index 3ee40479b69..f3614ebcc7a 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -3349,7 +3349,6 @@ void gdbserver_fork(CPUState *cpu)
close(gdbserver_state.fd);
gdbserver_state.fd = -1;
cpu_breakpoint_remove_all(cpu, BP_GDB);
- cpu_watchpoint_remove_all(cpu, BP_GDB);
}
#else
static int gdb_chr_can_receive(void *opaque)
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread* [PATCH v4 18/28] gdbstub: Remove watchpoint dead code in gdbserver_fork()
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Thomas Huth, Philippe Mathieu-Daudé,
Cornelia Huck, Richard Henderson, Laurent Vivier,
Philippe Mathieu-Daudé, qemu-s390x, qemu-arm, qemu-ppc,
Claudio Fontana, Paolo Bonzini, Alex Bennée
gdbserver_fork() is only used in user emulation where we can not
use watchpoints because we need the softmmu slow path to detect
accesses to watchpointed memory. This code doesn't do anything as
declared as stubs in "hw/core/cpu.h". Drop it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
gdbstub.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/gdbstub.c b/gdbstub.c
index 3ee40479b69..f3614ebcc7a 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -3349,7 +3349,6 @@ void gdbserver_fork(CPUState *cpu)
close(gdbserver_state.fd);
gdbserver_state.fd = -1;
cpu_breakpoint_remove_all(cpu, BP_GDB);
- cpu_watchpoint_remove_all(cpu, BP_GDB);
}
#else
static int gdb_chr_can_receive(void *opaque)
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v4 19/28] target/arm/internals: Fix code style for checkpatch.pl
2021-03-03 21:46 ` Philippe Mathieu-Daudé
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Claudio Fontana, qemu-arm, Peter Maydell, Paolo Bonzini,
Richard Henderson, qemu-s390x, Thomas Huth, qemu-ppc,
Laurent Vivier, Cornelia Huck, Alex Bennée,
Philippe Mathieu-Daudé
We are going to move this code, fix its style first.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/arm/internals.h | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 05cebc8597c..d6ace004855 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -251,7 +251,8 @@ static inline unsigned int arm_pamax(ARMCPU *cpu)
return pamax_map[parange];
}
-/* Return true if extended addresses are enabled.
+/*
+ * Return true if extended addresses are enabled.
* This is always the case if our translation regime is 64 bit,
* but depends on TTBCR.EAE for 32 bit.
*/
@@ -262,20 +263,24 @@ static inline bool extended_addresses_enabled(CPUARMState *env)
(arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE));
}
-/* Update a QEMU watchpoint based on the information the guest has set in the
+/*
+ * Update a QEMU watchpoint based on the information the guest has set in the
* DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers.
*/
void hw_watchpoint_update(ARMCPU *cpu, int n);
-/* Update the QEMU watchpoints for every guest watchpoint. This does a
+/*
+ * Update the QEMU watchpoints for every guest watchpoint. This does a
* complete delete-and-reinstate of the QEMU watchpoint list and so is
* suitable for use after migration or on reset.
*/
void hw_watchpoint_update_all(ARMCPU *cpu);
-/* Update a QEMU breakpoint based on the information the guest has set in the
+/*
+ * Update a QEMU breakpoint based on the information the guest has set in the
* DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers.
*/
void hw_breakpoint_update(ARMCPU *cpu, int n);
-/* Update the QEMU breakpoints for every guest breakpoint. This does a
+/*
+ * Update the QEMU breakpoints for every guest breakpoint. This does a
* complete delete-and-reinstate of the QEMU breakpoint list and so is
* suitable for use after migration or on reset.
*/
@@ -284,7 +289,8 @@ void hw_breakpoint_update_all(ARMCPU *cpu);
/* Callback function for checking if a watchpoint should trigger. */
bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
-/* Adjust addresses (in BE32 mode) before testing against watchpoint
+/*
+ * Adjust addresses (in BE32 mode) before testing against watchpoint
* addresses.
*/
vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len);
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread* [PATCH v4 19/28] target/arm/internals: Fix code style for checkpatch.pl
@ 2021-03-03 21:46 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:46 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Thomas Huth, Cornelia Huck, Richard Henderson,
Laurent Vivier, Philippe Mathieu-Daudé, qemu-s390x, qemu-arm,
qemu-ppc, Claudio Fontana, Paolo Bonzini, Alex Bennée
We are going to move this code, fix its style first.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/arm/internals.h | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 05cebc8597c..d6ace004855 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -251,7 +251,8 @@ static inline unsigned int arm_pamax(ARMCPU *cpu)
return pamax_map[parange];
}
-/* Return true if extended addresses are enabled.
+/*
+ * Return true if extended addresses are enabled.
* This is always the case if our translation regime is 64 bit,
* but depends on TTBCR.EAE for 32 bit.
*/
@@ -262,20 +263,24 @@ static inline bool extended_addresses_enabled(CPUARMState *env)
(arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE));
}
-/* Update a QEMU watchpoint based on the information the guest has set in the
+/*
+ * Update a QEMU watchpoint based on the information the guest has set in the
* DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers.
*/
void hw_watchpoint_update(ARMCPU *cpu, int n);
-/* Update the QEMU watchpoints for every guest watchpoint. This does a
+/*
+ * Update the QEMU watchpoints for every guest watchpoint. This does a
* complete delete-and-reinstate of the QEMU watchpoint list and so is
* suitable for use after migration or on reset.
*/
void hw_watchpoint_update_all(ARMCPU *cpu);
-/* Update a QEMU breakpoint based on the information the guest has set in the
+/*
+ * Update a QEMU breakpoint based on the information the guest has set in the
* DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers.
*/
void hw_breakpoint_update(ARMCPU *cpu, int n);
-/* Update the QEMU breakpoints for every guest breakpoint. This does a
+/*
+ * Update the QEMU breakpoints for every guest breakpoint. This does a
* complete delete-and-reinstate of the QEMU breakpoint list and so is
* suitable for use after migration or on reset.
*/
@@ -284,7 +289,8 @@ void hw_breakpoint_update_all(ARMCPU *cpu);
/* Callback function for checking if a watchpoint should trigger. */
bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
-/* Adjust addresses (in BE32 mode) before testing against watchpoint
+/*
+ * Adjust addresses (in BE32 mode) before testing against watchpoint
* addresses.
*/
vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len);
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v4 20/28] target/arm: Move code blocks around
2021-03-03 21:46 ` Philippe Mathieu-Daudé
@ 2021-03-03 21:47 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:47 UTC (permalink / raw)
To: qemu-devel
Cc: Claudio Fontana, qemu-arm, Peter Maydell, Paolo Bonzini,
Richard Henderson, qemu-s390x, Thomas Huth, qemu-ppc,
Laurent Vivier, Cornelia Huck, Alex Bennée,
Philippe Mathieu-Daudé
To simplify later #ifdef'ry, move some code around.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/arm/internals.h | 16 ++++++++--------
target/arm/debug_helper.c | 22 +++++++++++-----------
2 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index d6ace004855..3fb295431ae 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -278,14 +278,6 @@ void hw_watchpoint_update_all(ARMCPU *cpu);
* Update a QEMU breakpoint based on the information the guest has set in the
* DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers.
*/
-void hw_breakpoint_update(ARMCPU *cpu, int n);
-/*
- * Update the QEMU breakpoints for every guest breakpoint. This does a
- * complete delete-and-reinstate of the QEMU breakpoint list and so is
- * suitable for use after migration or on reset.
- */
-void hw_breakpoint_update_all(ARMCPU *cpu);
-
/* Callback function for checking if a watchpoint should trigger. */
bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
@@ -295,6 +287,14 @@ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
*/
vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len);
+void hw_breakpoint_update(ARMCPU *cpu, int n);
+/*
+ * Update the QEMU breakpoints for every guest breakpoint. This does a
+ * complete delete-and-reinstate of the QEMU breakpoint list and so is
+ * suitable for use after migration or on reset.
+ */
+void hw_breakpoint_update_all(ARMCPU *cpu);
+
/* Callback function for when a watchpoint or breakpoint triggers. */
void arm_debug_excp_handler(CPUState *cs);
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index 2ff72d47d19..c01d8524443 100644
--- a/target/arm/debug_helper.c
+++ b/target/arm/debug_helper.c
@@ -216,6 +216,17 @@ static bool check_watchpoints(ARMCPU *cpu)
return false;
}
+bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
+{
+ /*
+ * Called by core code when a CPU watchpoint fires; need to check if this
+ * is also an architectural watchpoint match.
+ */
+ ARMCPU *cpu = ARM_CPU(cs);
+
+ return check_watchpoints(cpu);
+}
+
static bool check_breakpoints(ARMCPU *cpu)
{
CPUARMState *env = &cpu->env;
@@ -247,17 +258,6 @@ void HELPER(check_breakpoints)(CPUARMState *env)
}
}
-bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
-{
- /*
- * Called by core code when a CPU watchpoint fires; need to check if this
- * is also an architectural watchpoint match.
- */
- ARMCPU *cpu = ARM_CPU(cs);
-
- return check_watchpoints(cpu);
-}
-
void arm_debug_excp_handler(CPUState *cs)
{
/*
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread* [PATCH v4 20/28] target/arm: Move code blocks around
@ 2021-03-03 21:47 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:47 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Thomas Huth, Cornelia Huck, Richard Henderson,
Laurent Vivier, Philippe Mathieu-Daudé, qemu-s390x, qemu-arm,
qemu-ppc, Claudio Fontana, Paolo Bonzini, Alex Bennée
To simplify later #ifdef'ry, move some code around.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/arm/internals.h | 16 ++++++++--------
target/arm/debug_helper.c | 22 +++++++++++-----------
2 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index d6ace004855..3fb295431ae 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -278,14 +278,6 @@ void hw_watchpoint_update_all(ARMCPU *cpu);
* Update a QEMU breakpoint based on the information the guest has set in the
* DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers.
*/
-void hw_breakpoint_update(ARMCPU *cpu, int n);
-/*
- * Update the QEMU breakpoints for every guest breakpoint. This does a
- * complete delete-and-reinstate of the QEMU breakpoint list and so is
- * suitable for use after migration or on reset.
- */
-void hw_breakpoint_update_all(ARMCPU *cpu);
-
/* Callback function for checking if a watchpoint should trigger. */
bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
@@ -295,6 +287,14 @@ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
*/
vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len);
+void hw_breakpoint_update(ARMCPU *cpu, int n);
+/*
+ * Update the QEMU breakpoints for every guest breakpoint. This does a
+ * complete delete-and-reinstate of the QEMU breakpoint list and so is
+ * suitable for use after migration or on reset.
+ */
+void hw_breakpoint_update_all(ARMCPU *cpu);
+
/* Callback function for when a watchpoint or breakpoint triggers. */
void arm_debug_excp_handler(CPUState *cs);
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index 2ff72d47d19..c01d8524443 100644
--- a/target/arm/debug_helper.c
+++ b/target/arm/debug_helper.c
@@ -216,6 +216,17 @@ static bool check_watchpoints(ARMCPU *cpu)
return false;
}
+bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
+{
+ /*
+ * Called by core code when a CPU watchpoint fires; need to check if this
+ * is also an architectural watchpoint match.
+ */
+ ARMCPU *cpu = ARM_CPU(cs);
+
+ return check_watchpoints(cpu);
+}
+
static bool check_breakpoints(ARMCPU *cpu)
{
CPUARMState *env = &cpu->env;
@@ -247,17 +258,6 @@ void HELPER(check_breakpoints)(CPUARMState *env)
}
}
-bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
-{
- /*
- * Called by core code when a CPU watchpoint fires; need to check if this
- * is also an architectural watchpoint match.
- */
- ARMCPU *cpu = ARM_CPU(cs);
-
- return check_watchpoints(cpu);
-}
-
void arm_debug_excp_handler(CPUState *cs)
{
/*
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v4 21/28] target/arm: Refactor some function bodies
2021-03-03 21:46 ` Philippe Mathieu-Daudé
@ 2021-03-03 21:47 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:47 UTC (permalink / raw)
To: qemu-devel
Cc: Claudio Fontana, qemu-arm, Peter Maydell, Paolo Bonzini,
Richard Henderson, qemu-s390x, Thomas Huth, qemu-ppc,
Laurent Vivier, Cornelia Huck, Alex Bennée,
Philippe Mathieu-Daudé
Refactor few fonctions body to ease #ifdef'ry review
in the next commit. No logical change intented.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
Patch easier to review using:
'git-diff --color-moved-ws=allow-indentation-change'
---
target/arm/debug_helper.c | 72 +++++++++++++++++++--------------------
target/arm/helper.c | 5 ++-
2 files changed, 38 insertions(+), 39 deletions(-)
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index c01d8524443..980110e1328 100644
--- a/target/arm/debug_helper.c
+++ b/target/arm/debug_helper.c
@@ -230,7 +230,6 @@ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
static bool check_breakpoints(ARMCPU *cpu)
{
CPUARMState *env = &cpu->env;
- int n;
/*
* If breakpoints are disabled globally or we can't take debug
@@ -241,7 +240,7 @@ static bool check_breakpoints(ARMCPU *cpu)
return false;
}
- for (n = 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) {
+ for (int n = 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) {
if (bp_wp_matches(cpu, n, false)) {
return true;
}
@@ -266,47 +265,48 @@ void arm_debug_excp_handler(CPUState *cs)
*/
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
+ uint64_t pc;
+ bool same_el;
CPUWatchpoint *wp_hit = cs->watchpoint_hit;
- if (wp_hit) {
- if (wp_hit->flags & BP_CPU) {
- bool wnr = (wp_hit->flags & BP_WATCHPOINT_HIT_WRITE) != 0;
- bool same_el = arm_debug_target_el(env) == arm_current_el(env);
+ if (wp_hit && (wp_hit->flags & BP_CPU)) {
+ bool wnr = (wp_hit->flags & BP_WATCHPOINT_HIT_WRITE) != 0;
+ bool same_el = arm_debug_target_el(env) == arm_current_el(env);
- cs->watchpoint_hit = NULL;
-
- env->exception.fsr = arm_debug_exception_fsr(env);
- env->exception.vaddress = wp_hit->hitaddr;
- raise_exception(env, EXCP_DATA_ABORT,
- syn_watchpoint(same_el, 0, wnr),
- arm_debug_target_el(env));
- }
- } else {
- uint64_t pc = is_a64(env) ? env->pc : env->regs[15];
- bool same_el = (arm_debug_target_el(env) == arm_current_el(env));
-
- /*
- * (1) GDB breakpoints should be handled first.
- * (2) Do not raise a CPU exception if no CPU breakpoint has fired,
- * since singlestep is also done by generating a debug internal
- * exception.
- */
- if (cpu_breakpoint_test(cs, pc, BP_GDB)
- || !cpu_breakpoint_test(cs, pc, BP_CPU)) {
- return;
- }
+ cs->watchpoint_hit = NULL;
env->exception.fsr = arm_debug_exception_fsr(env);
- /*
- * FAR is UNKNOWN: clear vaddress to avoid potentially exposing
- * values to the guest that it shouldn't be able to see at its
- * exception/security level.
- */
- env->exception.vaddress = 0;
- raise_exception(env, EXCP_PREFETCH_ABORT,
- syn_breakpoint(same_el),
+ env->exception.vaddress = wp_hit->hitaddr;
+ raise_exception(env, EXCP_DATA_ABORT,
+ syn_watchpoint(same_el, 0, wnr),
arm_debug_target_el(env));
+ return;
}
+
+ pc = is_a64(env) ? env->pc : env->regs[15];
+ same_el = (arm_debug_target_el(env) == arm_current_el(env));
+
+ /*
+ * (1) GDB breakpoints should be handled first.
+ * (2) Do not raise a CPU exception if no CPU breakpoint has fired,
+ * since singlestep is also done by generating a debug internal
+ * exception.
+ */
+ if (cpu_breakpoint_test(cs, pc, BP_GDB)
+ || !cpu_breakpoint_test(cs, pc, BP_CPU)) {
+ return;
+ }
+
+ env->exception.fsr = arm_debug_exception_fsr(env);
+ /*
+ * FAR is UNKNOWN: clear vaddress to avoid potentially exposing
+ * values to the guest that it shouldn't be able to see at its
+ * exception/security level.
+ */
+ env->exception.vaddress = 0;
+ raise_exception(env, EXCP_PREFETCH_ABORT,
+ syn_breakpoint(same_el),
+ arm_debug_target_el(env));
}
#if !defined(CONFIG_USER_ONLY)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 0e1a3b94211..54648c7fbb6 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6595,7 +6595,7 @@ static void define_debug_regs(ARMCPU *cpu)
* These are just dummy implementations for now.
*/
int i;
- int wrps, brps, ctx_cmps;
+ int brps, ctx_cmps;
/*
* The Arm ARM says DBGDIDR is optional and deprecated if EL1 cannot
@@ -6614,7 +6614,6 @@ static void define_debug_regs(ARMCPU *cpu)
/* Note that all these register fields hold "number of Xs minus 1". */
brps = arm_num_brps(cpu);
- wrps = arm_num_wrps(cpu);
ctx_cmps = arm_num_ctx_cmps(cpu);
assert(ctx_cmps <= brps);
@@ -6644,7 +6643,7 @@ static void define_debug_regs(ARMCPU *cpu)
define_arm_cp_regs(cpu, dbgregs);
}
- for (i = 0; i < wrps; i++) {
+ for (i = 0; i < arm_num_wrps(cpu); i++) {
ARMCPRegInfo dbgregs[] = {
{ .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread* [PATCH v4 21/28] target/arm: Refactor some function bodies
@ 2021-03-03 21:47 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:47 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Thomas Huth, Cornelia Huck, Richard Henderson,
Laurent Vivier, Philippe Mathieu-Daudé, qemu-s390x, qemu-arm,
qemu-ppc, Claudio Fontana, Paolo Bonzini, Alex Bennée
Refactor few fonctions body to ease #ifdef'ry review
in the next commit. No logical change intented.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
Patch easier to review using:
'git-diff --color-moved-ws=allow-indentation-change'
---
target/arm/debug_helper.c | 72 +++++++++++++++++++--------------------
target/arm/helper.c | 5 ++-
2 files changed, 38 insertions(+), 39 deletions(-)
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index c01d8524443..980110e1328 100644
--- a/target/arm/debug_helper.c
+++ b/target/arm/debug_helper.c
@@ -230,7 +230,6 @@ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
static bool check_breakpoints(ARMCPU *cpu)
{
CPUARMState *env = &cpu->env;
- int n;
/*
* If breakpoints are disabled globally or we can't take debug
@@ -241,7 +240,7 @@ static bool check_breakpoints(ARMCPU *cpu)
return false;
}
- for (n = 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) {
+ for (int n = 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) {
if (bp_wp_matches(cpu, n, false)) {
return true;
}
@@ -266,47 +265,48 @@ void arm_debug_excp_handler(CPUState *cs)
*/
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
+ uint64_t pc;
+ bool same_el;
CPUWatchpoint *wp_hit = cs->watchpoint_hit;
- if (wp_hit) {
- if (wp_hit->flags & BP_CPU) {
- bool wnr = (wp_hit->flags & BP_WATCHPOINT_HIT_WRITE) != 0;
- bool same_el = arm_debug_target_el(env) == arm_current_el(env);
+ if (wp_hit && (wp_hit->flags & BP_CPU)) {
+ bool wnr = (wp_hit->flags & BP_WATCHPOINT_HIT_WRITE) != 0;
+ bool same_el = arm_debug_target_el(env) == arm_current_el(env);
- cs->watchpoint_hit = NULL;
-
- env->exception.fsr = arm_debug_exception_fsr(env);
- env->exception.vaddress = wp_hit->hitaddr;
- raise_exception(env, EXCP_DATA_ABORT,
- syn_watchpoint(same_el, 0, wnr),
- arm_debug_target_el(env));
- }
- } else {
- uint64_t pc = is_a64(env) ? env->pc : env->regs[15];
- bool same_el = (arm_debug_target_el(env) == arm_current_el(env));
-
- /*
- * (1) GDB breakpoints should be handled first.
- * (2) Do not raise a CPU exception if no CPU breakpoint has fired,
- * since singlestep is also done by generating a debug internal
- * exception.
- */
- if (cpu_breakpoint_test(cs, pc, BP_GDB)
- || !cpu_breakpoint_test(cs, pc, BP_CPU)) {
- return;
- }
+ cs->watchpoint_hit = NULL;
env->exception.fsr = arm_debug_exception_fsr(env);
- /*
- * FAR is UNKNOWN: clear vaddress to avoid potentially exposing
- * values to the guest that it shouldn't be able to see at its
- * exception/security level.
- */
- env->exception.vaddress = 0;
- raise_exception(env, EXCP_PREFETCH_ABORT,
- syn_breakpoint(same_el),
+ env->exception.vaddress = wp_hit->hitaddr;
+ raise_exception(env, EXCP_DATA_ABORT,
+ syn_watchpoint(same_el, 0, wnr),
arm_debug_target_el(env));
+ return;
}
+
+ pc = is_a64(env) ? env->pc : env->regs[15];
+ same_el = (arm_debug_target_el(env) == arm_current_el(env));
+
+ /*
+ * (1) GDB breakpoints should be handled first.
+ * (2) Do not raise a CPU exception if no CPU breakpoint has fired,
+ * since singlestep is also done by generating a debug internal
+ * exception.
+ */
+ if (cpu_breakpoint_test(cs, pc, BP_GDB)
+ || !cpu_breakpoint_test(cs, pc, BP_CPU)) {
+ return;
+ }
+
+ env->exception.fsr = arm_debug_exception_fsr(env);
+ /*
+ * FAR is UNKNOWN: clear vaddress to avoid potentially exposing
+ * values to the guest that it shouldn't be able to see at its
+ * exception/security level.
+ */
+ env->exception.vaddress = 0;
+ raise_exception(env, EXCP_PREFETCH_ABORT,
+ syn_breakpoint(same_el),
+ arm_debug_target_el(env));
}
#if !defined(CONFIG_USER_ONLY)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 0e1a3b94211..54648c7fbb6 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6595,7 +6595,7 @@ static void define_debug_regs(ARMCPU *cpu)
* These are just dummy implementations for now.
*/
int i;
- int wrps, brps, ctx_cmps;
+ int brps, ctx_cmps;
/*
* The Arm ARM says DBGDIDR is optional and deprecated if EL1 cannot
@@ -6614,7 +6614,6 @@ static void define_debug_regs(ARMCPU *cpu)
/* Note that all these register fields hold "number of Xs minus 1". */
brps = arm_num_brps(cpu);
- wrps = arm_num_wrps(cpu);
ctx_cmps = arm_num_ctx_cmps(cpu);
assert(ctx_cmps <= brps);
@@ -6644,7 +6643,7 @@ static void define_debug_regs(ARMCPU *cpu)
define_arm_cp_regs(cpu, dbgregs);
}
- for (i = 0; i < wrps; i++) {
+ for (i = 0; i < arm_num_wrps(cpu); i++) {
ARMCPRegInfo dbgregs[] = {
{ .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v4 22/28] target/arm: Restrict watchpoint code to system emulation
2021-03-03 21:46 ` Philippe Mathieu-Daudé
@ 2021-03-03 21:47 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:47 UTC (permalink / raw)
To: qemu-devel
Cc: Claudio Fontana, qemu-arm, Peter Maydell, Paolo Bonzini,
Richard Henderson, qemu-s390x, Thomas Huth, qemu-ppc,
Laurent Vivier, Cornelia Huck, Alex Bennée,
Philippe Mathieu-Daudé
We can not use watchpoints in user-mode emulation because we
need the softmmu slow path to detect accesses to watchpointed
memory. Add #ifdef'ry around it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/arm/internals.h | 2 ++
target/arm/cpu.c | 4 ++--
target/arm/debug_helper.c | 8 ++++++++
target/arm/helper.c | 4 ++++
target/arm/sve_helper.c | 12 ++++++++++++
5 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 3fb295431ae..8fa0a244d59 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -263,6 +263,7 @@ static inline bool extended_addresses_enabled(CPUARMState *env)
(arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE));
}
+#ifndef CONFIG_USER_ONLY
/*
* Update a QEMU watchpoint based on the information the guest has set in the
* DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers.
@@ -286,6 +287,7 @@ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
* addresses.
*/
vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len);
+#endif /* !CONFIG_USER_ONLY */
void hw_breakpoint_update(ARMCPU *cpu, int n);
/*
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 09566a535e5..efc338b24eb 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -432,10 +432,10 @@ static void arm_cpu_reset(DeviceState *dev)
if (kvm_enabled()) {
kvm_arm_reset_vcpu(cpu);
}
-#endif
- hw_breakpoint_update_all(cpu);
hw_watchpoint_update_all(cpu);
+#endif
+ hw_breakpoint_update_all(cpu);
arm_rebuild_hflags(env);
}
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index 980110e1328..b8b7d81762d 100644
--- a/target/arm/debug_helper.c
+++ b/target/arm/debug_helper.c
@@ -11,6 +11,8 @@
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
+#ifndef CONFIG_USER_ONLY
+
/* Return true if the linked breakpoint entry lbn passes its checks */
static bool linked_bp_matches(ARMCPU *cpu, int lbn)
{
@@ -227,6 +229,8 @@ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
return check_watchpoints(cpu);
}
+#endif /* !CONFIG_USER_ONLY */
+
static bool check_breakpoints(ARMCPU *cpu)
{
CPUARMState *env = &cpu->env;
@@ -240,11 +244,13 @@ static bool check_breakpoints(ARMCPU *cpu)
return false;
}
+#ifndef CONFIG_USER_ONLY
for (int n = 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) {
if (bp_wp_matches(cpu, n, false)) {
return true;
}
}
+#endif /* !CONFIG_USER_ONLY */
return false;
}
@@ -267,6 +273,7 @@ void arm_debug_excp_handler(CPUState *cs)
CPUARMState *env = &cpu->env;
uint64_t pc;
bool same_el;
+#ifndef CONFIG_USER_ONLY
CPUWatchpoint *wp_hit = cs->watchpoint_hit;
if (wp_hit && (wp_hit->flags & BP_CPU)) {
@@ -282,6 +289,7 @@ void arm_debug_excp_handler(CPUState *cs)
arm_debug_target_el(env));
return;
}
+#endif /* !CONFIG_USER_ONLY */
pc = is_a64(env) ? env->pc : env->regs[15];
same_el = (arm_debug_target_el(env) == arm_current_el(env));
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 54648c7fbb6..2e7a6356ae3 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6345,6 +6345,7 @@ static const ARMCPRegInfo zcr_el3_reginfo = {
.writefn = zcr_write, .raw_writefn = raw_write
};
+#ifndef CONFIG_USER_ONLY
void hw_watchpoint_update(ARMCPU *cpu, int n)
{
CPUARMState *env = &cpu->env;
@@ -6470,6 +6471,7 @@ static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
raw_write(env, ri, value);
hw_watchpoint_update(cpu, i);
}
+#endif /* !CONFIG_USER_ONLY */
void hw_breakpoint_update(ARMCPU *cpu, int n)
{
@@ -6643,6 +6645,7 @@ static void define_debug_regs(ARMCPU *cpu)
define_arm_cp_regs(cpu, dbgregs);
}
+#ifndef CONFIG_USER_ONLY
for (i = 0; i < arm_num_wrps(cpu); i++) {
ARMCPRegInfo dbgregs[] = {
{ .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
@@ -6661,6 +6664,7 @@ static void define_debug_regs(ARMCPU *cpu)
};
define_arm_cp_regs(cpu, dbgregs);
}
+#endif /* !CONFIG_USER_ONLY */
}
static void define_pmu_regs(ARMCPU *cpu)
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 844db08bd57..ed3f22d78a5 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -4849,6 +4849,7 @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const target_ulong addr,
/* Some page is MMIO, see below. */
goto do_fault;
}
+#ifndef CONFIG_USER_ONLY
if (unlikely(flags & TLB_WATCHPOINT) &&
(cpu_watchpoint_address_matches
(env_cpu(env), addr + mem_off, 1 << msz)
@@ -4856,6 +4857,7 @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const target_ulong addr,
/* Watchpoint hit, see below. */
goto do_fault;
}
+#endif
if (mtedesc && !mte_probe1(env, mtedesc, addr + mem_off)) {
goto do_fault;
}
@@ -4900,12 +4902,14 @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const target_ulong addr,
uint64_t pg = *(uint64_t *)(vg + (reg_off >> 3));
do {
if ((pg >> (reg_off & 63)) & 1) {
+#ifndef CONFIG_USER_ONLY
if (unlikely(flags & TLB_WATCHPOINT) &&
(cpu_watchpoint_address_matches
(env_cpu(env), addr + mem_off, 1 << msz)
& BP_MEM_READ)) {
goto do_fault;
}
+#endif
if (mtedesc && !mte_probe1(env, mtedesc, addr + mem_off)) {
goto do_fault;
}
@@ -5355,10 +5359,12 @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
mmu_idx, retaddr);
if (likely(in_page >= msize)) {
+#ifndef CONFIG_USER_ONLY
if (unlikely(info.flags & TLB_WATCHPOINT)) {
cpu_check_watchpoint(env_cpu(env), addr, msize,
info.attrs, BP_MEM_READ, retaddr);
}
+#endif
if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) {
mte_check1(env, mtedesc, addr, retaddr);
}
@@ -5367,11 +5373,13 @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
/* Element crosses the page boundary. */
sve_probe_page(&info2, false, env, addr + in_page, 0,
MMU_DATA_LOAD, mmu_idx, retaddr);
+#ifndef CONFIG_USER_ONLY
if (unlikely((info.flags | info2.flags) & TLB_WATCHPOINT)) {
cpu_check_watchpoint(env_cpu(env), addr,
msize, info.attrs,
BP_MEM_READ, retaddr);
}
+#endif
if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) {
mte_check1(env, mtedesc, addr, retaddr);
}
@@ -5568,11 +5576,13 @@ void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
if (unlikely(info.flags & (TLB_INVALID_MASK | TLB_MMIO))) {
goto fault;
}
+#ifndef CONFIG_USER_ONLY
if (unlikely(info.flags & TLB_WATCHPOINT) &&
(cpu_watchpoint_address_matches
(env_cpu(env), addr, msize) & BP_MEM_READ)) {
goto fault;
}
+#endif
if (mtedesc &&
arm_tlb_mte_tagged(&info.attrs) &&
!mte_probe1(env, mtedesc, addr)) {
@@ -5754,10 +5764,12 @@ void sve_st1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
info.flags |= info2.flags;
}
+#ifndef CONFIG_USER_ONLY
if (unlikely(info.flags & TLB_WATCHPOINT)) {
cpu_check_watchpoint(env_cpu(env), addr, msize,
info.attrs, BP_MEM_WRITE, retaddr);
}
+#endif
if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) {
mte_check1(env, mtedesc, addr, retaddr);
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread* [PATCH v4 22/28] target/arm: Restrict watchpoint code to system emulation
@ 2021-03-03 21:47 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:47 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Thomas Huth, Cornelia Huck, Richard Henderson,
Laurent Vivier, Philippe Mathieu-Daudé, qemu-s390x, qemu-arm,
qemu-ppc, Claudio Fontana, Paolo Bonzini, Alex Bennée
We can not use watchpoints in user-mode emulation because we
need the softmmu slow path to detect accesses to watchpointed
memory. Add #ifdef'ry around it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/arm/internals.h | 2 ++
target/arm/cpu.c | 4 ++--
target/arm/debug_helper.c | 8 ++++++++
target/arm/helper.c | 4 ++++
target/arm/sve_helper.c | 12 ++++++++++++
5 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 3fb295431ae..8fa0a244d59 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -263,6 +263,7 @@ static inline bool extended_addresses_enabled(CPUARMState *env)
(arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE));
}
+#ifndef CONFIG_USER_ONLY
/*
* Update a QEMU watchpoint based on the information the guest has set in the
* DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers.
@@ -286,6 +287,7 @@ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
* addresses.
*/
vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len);
+#endif /* !CONFIG_USER_ONLY */
void hw_breakpoint_update(ARMCPU *cpu, int n);
/*
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 09566a535e5..efc338b24eb 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -432,10 +432,10 @@ static void arm_cpu_reset(DeviceState *dev)
if (kvm_enabled()) {
kvm_arm_reset_vcpu(cpu);
}
-#endif
- hw_breakpoint_update_all(cpu);
hw_watchpoint_update_all(cpu);
+#endif
+ hw_breakpoint_update_all(cpu);
arm_rebuild_hflags(env);
}
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index 980110e1328..b8b7d81762d 100644
--- a/target/arm/debug_helper.c
+++ b/target/arm/debug_helper.c
@@ -11,6 +11,8 @@
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
+#ifndef CONFIG_USER_ONLY
+
/* Return true if the linked breakpoint entry lbn passes its checks */
static bool linked_bp_matches(ARMCPU *cpu, int lbn)
{
@@ -227,6 +229,8 @@ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
return check_watchpoints(cpu);
}
+#endif /* !CONFIG_USER_ONLY */
+
static bool check_breakpoints(ARMCPU *cpu)
{
CPUARMState *env = &cpu->env;
@@ -240,11 +244,13 @@ static bool check_breakpoints(ARMCPU *cpu)
return false;
}
+#ifndef CONFIG_USER_ONLY
for (int n = 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) {
if (bp_wp_matches(cpu, n, false)) {
return true;
}
}
+#endif /* !CONFIG_USER_ONLY */
return false;
}
@@ -267,6 +273,7 @@ void arm_debug_excp_handler(CPUState *cs)
CPUARMState *env = &cpu->env;
uint64_t pc;
bool same_el;
+#ifndef CONFIG_USER_ONLY
CPUWatchpoint *wp_hit = cs->watchpoint_hit;
if (wp_hit && (wp_hit->flags & BP_CPU)) {
@@ -282,6 +289,7 @@ void arm_debug_excp_handler(CPUState *cs)
arm_debug_target_el(env));
return;
}
+#endif /* !CONFIG_USER_ONLY */
pc = is_a64(env) ? env->pc : env->regs[15];
same_el = (arm_debug_target_el(env) == arm_current_el(env));
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 54648c7fbb6..2e7a6356ae3 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6345,6 +6345,7 @@ static const ARMCPRegInfo zcr_el3_reginfo = {
.writefn = zcr_write, .raw_writefn = raw_write
};
+#ifndef CONFIG_USER_ONLY
void hw_watchpoint_update(ARMCPU *cpu, int n)
{
CPUARMState *env = &cpu->env;
@@ -6470,6 +6471,7 @@ static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
raw_write(env, ri, value);
hw_watchpoint_update(cpu, i);
}
+#endif /* !CONFIG_USER_ONLY */
void hw_breakpoint_update(ARMCPU *cpu, int n)
{
@@ -6643,6 +6645,7 @@ static void define_debug_regs(ARMCPU *cpu)
define_arm_cp_regs(cpu, dbgregs);
}
+#ifndef CONFIG_USER_ONLY
for (i = 0; i < arm_num_wrps(cpu); i++) {
ARMCPRegInfo dbgregs[] = {
{ .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
@@ -6661,6 +6664,7 @@ static void define_debug_regs(ARMCPU *cpu)
};
define_arm_cp_regs(cpu, dbgregs);
}
+#endif /* !CONFIG_USER_ONLY */
}
static void define_pmu_regs(ARMCPU *cpu)
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 844db08bd57..ed3f22d78a5 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -4849,6 +4849,7 @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const target_ulong addr,
/* Some page is MMIO, see below. */
goto do_fault;
}
+#ifndef CONFIG_USER_ONLY
if (unlikely(flags & TLB_WATCHPOINT) &&
(cpu_watchpoint_address_matches
(env_cpu(env), addr + mem_off, 1 << msz)
@@ -4856,6 +4857,7 @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const target_ulong addr,
/* Watchpoint hit, see below. */
goto do_fault;
}
+#endif
if (mtedesc && !mte_probe1(env, mtedesc, addr + mem_off)) {
goto do_fault;
}
@@ -4900,12 +4902,14 @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const target_ulong addr,
uint64_t pg = *(uint64_t *)(vg + (reg_off >> 3));
do {
if ((pg >> (reg_off & 63)) & 1) {
+#ifndef CONFIG_USER_ONLY
if (unlikely(flags & TLB_WATCHPOINT) &&
(cpu_watchpoint_address_matches
(env_cpu(env), addr + mem_off, 1 << msz)
& BP_MEM_READ)) {
goto do_fault;
}
+#endif
if (mtedesc && !mte_probe1(env, mtedesc, addr + mem_off)) {
goto do_fault;
}
@@ -5355,10 +5359,12 @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
mmu_idx, retaddr);
if (likely(in_page >= msize)) {
+#ifndef CONFIG_USER_ONLY
if (unlikely(info.flags & TLB_WATCHPOINT)) {
cpu_check_watchpoint(env_cpu(env), addr, msize,
info.attrs, BP_MEM_READ, retaddr);
}
+#endif
if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) {
mte_check1(env, mtedesc, addr, retaddr);
}
@@ -5367,11 +5373,13 @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
/* Element crosses the page boundary. */
sve_probe_page(&info2, false, env, addr + in_page, 0,
MMU_DATA_LOAD, mmu_idx, retaddr);
+#ifndef CONFIG_USER_ONLY
if (unlikely((info.flags | info2.flags) & TLB_WATCHPOINT)) {
cpu_check_watchpoint(env_cpu(env), addr,
msize, info.attrs,
BP_MEM_READ, retaddr);
}
+#endif
if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) {
mte_check1(env, mtedesc, addr, retaddr);
}
@@ -5568,11 +5576,13 @@ void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
if (unlikely(info.flags & (TLB_INVALID_MASK | TLB_MMIO))) {
goto fault;
}
+#ifndef CONFIG_USER_ONLY
if (unlikely(info.flags & TLB_WATCHPOINT) &&
(cpu_watchpoint_address_matches
(env_cpu(env), addr, msize) & BP_MEM_READ)) {
goto fault;
}
+#endif
if (mtedesc &&
arm_tlb_mte_tagged(&info.attrs) &&
!mte_probe1(env, mtedesc, addr)) {
@@ -5754,10 +5764,12 @@ void sve_st1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
info.flags |= info2.flags;
}
+#ifndef CONFIG_USER_ONLY
if (unlikely(info.flags & TLB_WATCHPOINT)) {
cpu_check_watchpoint(env_cpu(env), addr, msize,
info.attrs, BP_MEM_WRITE, retaddr);
}
+#endif
if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) {
mte_check1(env, mtedesc, addr, retaddr);
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread* Re: [PATCH v4 22/28] target/arm: Restrict watchpoint code to system emulation
2021-03-03 21:47 ` Philippe Mathieu-Daudé
@ 2021-03-03 22:40 ` Richard Henderson
-1 siblings, 0 replies; 79+ messages in thread
From: Richard Henderson @ 2021-03-03 22:40 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Claudio Fontana, qemu-arm, Peter Maydell, Paolo Bonzini,
qemu-s390x, Thomas Huth, qemu-ppc, Laurent Vivier, Cornelia Huck,
Alex Bennée
On 3/3/21 1:47 PM, Philippe Mathieu-Daudé wrote:
> diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
> index 844db08bd57..ed3f22d78a5 100644
> --- a/target/arm/sve_helper.c
> +++ b/target/arm/sve_helper.c
> @@ -4849,6 +4849,7 @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const target_ulong addr,
> /* Some page is MMIO, see below. */
> goto do_fault;
> }
> +#ifndef CONFIG_USER_ONLY
> if (unlikely(flags & TLB_WATCHPOINT) &&
> (cpu_watchpoint_address_matches
> (env_cpu(env), addr + mem_off, 1 << msz)
> @@ -4856,6 +4857,7 @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const target_ulong addr,
> /* Watchpoint hit, see below. */
> goto do_fault;
> }
> +#endif
>
Nack. These are eliminated via TLB_WATCHPOINT 0 in exec/cpu-all.h, and an
empty inline function in hw/core/cpu.h.
r~
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v4 22/28] target/arm: Restrict watchpoint code to system emulation
@ 2021-03-03 22:40 ` Richard Henderson
0 siblings, 0 replies; 79+ messages in thread
From: Richard Henderson @ 2021-03-03 22:40 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Peter Maydell, Thomas Huth, Cornelia Huck, Laurent Vivier,
qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana, Paolo Bonzini,
Alex Bennée
On 3/3/21 1:47 PM, Philippe Mathieu-Daudé wrote:
> diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
> index 844db08bd57..ed3f22d78a5 100644
> --- a/target/arm/sve_helper.c
> +++ b/target/arm/sve_helper.c
> @@ -4849,6 +4849,7 @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const target_ulong addr,
> /* Some page is MMIO, see below. */
> goto do_fault;
> }
> +#ifndef CONFIG_USER_ONLY
> if (unlikely(flags & TLB_WATCHPOINT) &&
> (cpu_watchpoint_address_matches
> (env_cpu(env), addr + mem_off, 1 << msz)
> @@ -4856,6 +4857,7 @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const target_ulong addr,
> /* Watchpoint hit, see below. */
> goto do_fault;
> }
> +#endif
>
Nack. These are eliminated via TLB_WATCHPOINT 0 in exec/cpu-all.h, and an
empty inline function in hw/core/cpu.h.
r~
^ permalink raw reply [flat|nested] 79+ messages in thread
* [PATCH v4 23/28] target/i386: Restrict watchpoint code to system emulation
2021-03-03 21:46 ` Philippe Mathieu-Daudé
@ 2021-03-03 21:47 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:47 UTC (permalink / raw)
To: qemu-devel
Cc: Claudio Fontana, qemu-arm, Peter Maydell, Paolo Bonzini,
Richard Henderson, qemu-s390x, Thomas Huth, qemu-ppc,
Laurent Vivier, Cornelia Huck, Alex Bennée,
Philippe Mathieu-Daudé, Eduardo Habkost
We can not use watchpoints in user-mode emulation because we
need the softmmu slow path to detect accesses to watchpointed
memory. Add #ifdef'ry around it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/i386/cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 994d58aa754..4b8f06f6193 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6182,7 +6182,6 @@ static void x86_cpu_reset(DeviceState *dev)
env->dr[6] = DR6_FIXED_1;
env->dr[7] = DR7_FIXED_1;
cpu_breakpoint_remove_all(s, BP_CPU);
- cpu_watchpoint_remove_all(s, BP_CPU);
cr4 = 0;
xcr0 = XSTATE_FP_MASK;
@@ -6205,6 +6204,8 @@ static void x86_cpu_reset(DeviceState *dev)
if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
cr4 |= CR4_FSGSBASE_MASK;
}
+#else
+ cpu_watchpoint_remove_all(s, BP_CPU);
#endif
env->xcr0 = xcr0;
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread* [PATCH v4 23/28] target/i386: Restrict watchpoint code to system emulation
@ 2021-03-03 21:47 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:47 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Thomas Huth, Eduardo Habkost, Cornelia Huck,
Richard Henderson, Laurent Vivier, Philippe Mathieu-Daudé,
qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana, Paolo Bonzini,
Alex Bennée
We can not use watchpoints in user-mode emulation because we
need the softmmu slow path to detect accesses to watchpointed
memory. Add #ifdef'ry around it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/i386/cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 994d58aa754..4b8f06f6193 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6182,7 +6182,6 @@ static void x86_cpu_reset(DeviceState *dev)
env->dr[6] = DR6_FIXED_1;
env->dr[7] = DR7_FIXED_1;
cpu_breakpoint_remove_all(s, BP_CPU);
- cpu_watchpoint_remove_all(s, BP_CPU);
cr4 = 0;
xcr0 = XSTATE_FP_MASK;
@@ -6205,6 +6204,8 @@ static void x86_cpu_reset(DeviceState *dev)
if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
cr4 |= CR4_FSGSBASE_MASK;
}
+#else
+ cpu_watchpoint_remove_all(s, BP_CPU);
#endif
env->xcr0 = xcr0;
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v4 24/28] target/xtensa: Restrict watchpoint code to system emulation
2021-03-03 21:46 ` Philippe Mathieu-Daudé
@ 2021-03-03 21:47 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:47 UTC (permalink / raw)
To: qemu-devel
Cc: Claudio Fontana, qemu-arm, Peter Maydell, Paolo Bonzini,
Richard Henderson, qemu-s390x, Thomas Huth, qemu-ppc,
Laurent Vivier, Cornelia Huck, Alex Bennée,
Philippe Mathieu-Daudé, Max Filippov
We can not use watchpoints in user-mode emulation because we
need the softmmu slow path to detect accesses to watchpointed
memory. Add #ifdef'ry around it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/xtensa/helper.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c
index eeffee297d1..85e466b37d2 100644
--- a/target/xtensa/helper.c
+++ b/target/xtensa/helper.c
@@ -201,6 +201,7 @@ void xtensa_register_core(XtensaConfigList *node)
g_free((gpointer)type.name);
}
+#ifndef CONFIG_USER_ONLY
static uint32_t check_hw_breakpoints(CPUXtensaState *env)
{
unsigned i;
@@ -213,9 +214,11 @@ static uint32_t check_hw_breakpoints(CPUXtensaState *env)
}
return 0;
}
+#endif
void xtensa_breakpoint_handler(CPUState *cs)
{
+#ifndef CONFIG_USER_ONLY
XtensaCPU *cpu = XTENSA_CPU(cs);
CPUXtensaState *env = &cpu->env;
@@ -231,6 +234,7 @@ void xtensa_breakpoint_handler(CPUState *cs)
cpu_loop_exit_noexc(cs);
}
}
+#endif
}
void xtensa_cpu_list(void)
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread* [PATCH v4 24/28] target/xtensa: Restrict watchpoint code to system emulation
@ 2021-03-03 21:47 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:47 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Thomas Huth, Cornelia Huck, Richard Henderson,
Laurent Vivier, Philippe Mathieu-Daudé, Max Filippov,
qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana, Paolo Bonzini,
Alex Bennée
We can not use watchpoints in user-mode emulation because we
need the softmmu slow path to detect accesses to watchpointed
memory. Add #ifdef'ry around it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/xtensa/helper.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c
index eeffee297d1..85e466b37d2 100644
--- a/target/xtensa/helper.c
+++ b/target/xtensa/helper.c
@@ -201,6 +201,7 @@ void xtensa_register_core(XtensaConfigList *node)
g_free((gpointer)type.name);
}
+#ifndef CONFIG_USER_ONLY
static uint32_t check_hw_breakpoints(CPUXtensaState *env)
{
unsigned i;
@@ -213,9 +214,11 @@ static uint32_t check_hw_breakpoints(CPUXtensaState *env)
}
return 0;
}
+#endif
void xtensa_breakpoint_handler(CPUState *cs)
{
+#ifndef CONFIG_USER_ONLY
XtensaCPU *cpu = XTENSA_CPU(cs);
CPUXtensaState *env = &cpu->env;
@@ -231,6 +234,7 @@ void xtensa_breakpoint_handler(CPUState *cs)
cpu_loop_exit_noexc(cs);
}
}
+#endif
}
void xtensa_cpu_list(void)
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v4 25/28] accel/tcg/cpu-exec: Restrict watchpoint code to system emulation
2021-03-03 21:46 ` Philippe Mathieu-Daudé
@ 2021-03-03 21:47 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:47 UTC (permalink / raw)
To: qemu-devel
Cc: Claudio Fontana, qemu-arm, Peter Maydell, Paolo Bonzini,
Richard Henderson, qemu-s390x, Thomas Huth, qemu-ppc,
Laurent Vivier, Cornelia Huck, Alex Bennée,
Philippe Mathieu-Daudé
We can not use watchpoints in user-mode emulation because we
need the softmmu slow path to detect accesses to watchpointed
memory. Add #ifdef'ry around it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
accel/tcg/cpu-exec.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 16e4fe3ccd8..3a6436013ea 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -471,13 +471,16 @@ static inline bool cpu_handle_halt(CPUState *cpu)
static inline void cpu_handle_debug_exception(CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- CPUWatchpoint *wp;
+#ifndef CONFIG_USER_ONLY
if (!cpu->watchpoint_hit) {
+ CPUWatchpoint *wp;
+
QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
wp->flags &= ~BP_WATCHPOINT_HIT;
}
}
+#endif
if (cc->tcg_ops->debug_excp_handler) {
cc->tcg_ops->debug_excp_handler(cpu);
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread* [PATCH v4 25/28] accel/tcg/cpu-exec: Restrict watchpoint code to system emulation
@ 2021-03-03 21:47 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:47 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Thomas Huth, Cornelia Huck, Richard Henderson,
Laurent Vivier, Philippe Mathieu-Daudé, qemu-s390x, qemu-arm,
qemu-ppc, Claudio Fontana, Paolo Bonzini, Alex Bennée
We can not use watchpoints in user-mode emulation because we
need the softmmu slow path to detect accesses to watchpointed
memory. Add #ifdef'ry around it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
accel/tcg/cpu-exec.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 16e4fe3ccd8..3a6436013ea 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -471,13 +471,16 @@ static inline bool cpu_handle_halt(CPUState *cpu)
static inline void cpu_handle_debug_exception(CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- CPUWatchpoint *wp;
+#ifndef CONFIG_USER_ONLY
if (!cpu->watchpoint_hit) {
+ CPUWatchpoint *wp;
+
QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
wp->flags &= ~BP_WATCHPOINT_HIT;
}
}
+#endif
if (cc->tcg_ops->debug_excp_handler) {
cc->tcg_ops->debug_excp_handler(cpu);
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v4 26/28] cpu: Remove watchpoint stubs for user emulation
2021-03-03 21:46 ` Philippe Mathieu-Daudé
@ 2021-03-03 21:47 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:47 UTC (permalink / raw)
To: qemu-devel
Cc: Claudio Fontana, qemu-arm, Peter Maydell, Paolo Bonzini,
Richard Henderson, qemu-s390x, Thomas Huth, qemu-ppc,
Laurent Vivier, Cornelia Huck, Alex Bennée,
Philippe Mathieu-Daudé, Eduardo Habkost, Marcel Apfelbaum
Since we remove all access to the watchpoint methods from user-mode
code, we can now remove them, as they are not used anymore.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 34 +---------------------------------
1 file changed, 1 insertion(+), 33 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index fe4206b540f..b708f365a7a 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -916,39 +916,7 @@ static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask)
return false;
}
-#ifdef CONFIG_USER_ONLY
-static inline int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
- int flags, CPUWatchpoint **watchpoint)
-{
- return -ENOSYS;
-}
-
-static inline int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
- vaddr len, int flags)
-{
- return -ENOSYS;
-}
-
-static inline void cpu_watchpoint_remove_by_ref(CPUState *cpu,
- CPUWatchpoint *wp)
-{
-}
-
-static inline void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
-{
-}
-
-static inline void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
- MemTxAttrs atr, int fl, uintptr_t ra)
-{
-}
-
-static inline int cpu_watchpoint_address_matches(CPUState *cpu,
- vaddr addr, vaddr len)
-{
- return 0;
-}
-#else
+#ifndef CONFIG_USER_ONLY
int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
int flags, CPUWatchpoint **watchpoint);
int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread* [PATCH v4 26/28] cpu: Remove watchpoint stubs for user emulation
@ 2021-03-03 21:47 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:47 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Thomas Huth, Eduardo Habkost, Cornelia Huck,
Richard Henderson, Laurent Vivier, Philippe Mathieu-Daudé,
qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana, Paolo Bonzini,
Alex Bennée
Since we remove all access to the watchpoint methods from user-mode
code, we can now remove them, as they are not used anymore.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 34 +---------------------------------
1 file changed, 1 insertion(+), 33 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index fe4206b540f..b708f365a7a 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -916,39 +916,7 @@ static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask)
return false;
}
-#ifdef CONFIG_USER_ONLY
-static inline int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
- int flags, CPUWatchpoint **watchpoint)
-{
- return -ENOSYS;
-}
-
-static inline int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
- vaddr len, int flags)
-{
- return -ENOSYS;
-}
-
-static inline void cpu_watchpoint_remove_by_ref(CPUState *cpu,
- CPUWatchpoint *wp)
-{
-}
-
-static inline void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
-{
-}
-
-static inline void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
- MemTxAttrs atr, int fl, uintptr_t ra)
-{
-}
-
-static inline int cpu_watchpoint_address_matches(CPUState *cpu,
- vaddr addr, vaddr len)
-{
- return 0;
-}
-#else
+#ifndef CONFIG_USER_ONLY
int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
int flags, CPUWatchpoint **watchpoint);
int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread* Re: [PATCH v4 26/28] cpu: Remove watchpoint stubs for user emulation
2021-03-03 21:47 ` Philippe Mathieu-Daudé
@ 2021-03-03 23:28 ` Richard Henderson
-1 siblings, 0 replies; 79+ messages in thread
From: Richard Henderson @ 2021-03-03 23:28 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Claudio Fontana, qemu-arm, Peter Maydell, Paolo Bonzini,
qemu-s390x, Thomas Huth, qemu-ppc, Laurent Vivier, Cornelia Huck,
Alex Bennée, Eduardo Habkost, Marcel Apfelbaum
On 3/3/21 1:47 PM, Philippe Mathieu-Daudé wrote:
> Since we remove all access to the watchpoint methods from user-mode
> code, we can now remove them, as they are not used anymore.
>
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
> include/hw/core/cpu.h | 34 +---------------------------------
> 1 file changed, 1 insertion(+), 33 deletions(-)
I do not think this is a good tradeoff, removing one central ifdef and
substituting lots of others, scattered throughout target/.
r~
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v4 26/28] cpu: Remove watchpoint stubs for user emulation
@ 2021-03-03 23:28 ` Richard Henderson
0 siblings, 0 replies; 79+ messages in thread
From: Richard Henderson @ 2021-03-03 23:28 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Peter Maydell, Thomas Huth, Eduardo Habkost, Cornelia Huck,
Laurent Vivier, qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana,
Paolo Bonzini, Alex Bennée
On 3/3/21 1:47 PM, Philippe Mathieu-Daudé wrote:
> Since we remove all access to the watchpoint methods from user-mode
> code, we can now remove them, as they are not used anymore.
>
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
> include/hw/core/cpu.h | 34 +---------------------------------
> 1 file changed, 1 insertion(+), 33 deletions(-)
I do not think this is a good tradeoff, removing one central ifdef and
substituting lots of others, scattered throughout target/.
r~
^ permalink raw reply [flat|nested] 79+ messages in thread
* [PATCH v4 27/28] cpu: Fix code style for checkpatch.pl
2021-03-03 21:46 ` Philippe Mathieu-Daudé
@ 2021-03-03 21:47 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:47 UTC (permalink / raw)
To: qemu-devel
Cc: Claudio Fontana, qemu-arm, Peter Maydell, Paolo Bonzini,
Richard Henderson, qemu-s390x, Thomas Huth, qemu-ppc,
Laurent Vivier, Cornelia Huck, Alex Bennée,
Philippe Mathieu-Daudé, Eduardo Habkost, Marcel Apfelbaum
We are going to move this code, fix its style first.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index b708f365a7a..79dcc9a4e42 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -558,7 +558,8 @@ hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
*/
hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
-/** cpu_asidx_from_attrs:
+/**
+ * cpu_asidx_from_attrs:
* @cpu: CPU
* @attrs: memory transaction attributes
*
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v4 27/28] cpu: Fix code style for checkpatch.pl
@ 2021-03-03 21:47 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:47 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Thomas Huth, Eduardo Habkost, Cornelia Huck,
Richard Henderson, Laurent Vivier, Philippe Mathieu-Daudé,
qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana, Paolo Bonzini,
Alex Bennée
We are going to move this code, fix its style first.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index b708f365a7a..79dcc9a4e42 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -558,7 +558,8 @@ hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
*/
hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
-/** cpu_asidx_from_attrs:
+/**
+ * cpu_asidx_from_attrs:
* @cpu: CPU
* @attrs: memory transaction attributes
*
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v4 28/28] cpu: Move sysemu specific declarations to 'sysemu-cpu-ops.h'
2021-03-03 21:46 ` Philippe Mathieu-Daudé
@ 2021-03-03 21:47 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:47 UTC (permalink / raw)
To: qemu-devel
Cc: Claudio Fontana, qemu-arm, Peter Maydell, Paolo Bonzini,
Richard Henderson, qemu-s390x, Thomas Huth, qemu-ppc,
Laurent Vivier, Cornelia Huck, Alex Bennée,
Philippe Mathieu-Daudé, Philippe Mathieu-Daudé,
Eduardo Habkost, Marcel Apfelbaum
All these prototypes and declarations don't need to be exposed
on user-mode emulation. Move them to "sysemu-cpu-ops.h".
Suggested-by: Claudio Fontana <cfontana@suse.de>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 164 -------------------------------
include/hw/core/sysemu-cpu-ops.h | 155 +++++++++++++++++++++++++++++
gdbstub.c | 1 +
softmmu/physmem.c | 1 +
4 files changed, 157 insertions(+), 164 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 79dcc9a4e42..53598c02187 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -185,15 +185,6 @@ typedef struct CPUBreakpoint {
QTAILQ_ENTRY(CPUBreakpoint) entry;
} CPUBreakpoint;
-struct CPUWatchpoint {
- vaddr vaddr;
- vaddr len;
- vaddr hitaddr;
- MemTxAttrs hitattrs;
- int flags; /* BP_* */
- QTAILQ_ENTRY(CPUWatchpoint) entry;
-};
-
#ifdef CONFIG_PLUGIN
/*
* For plugins we sometime need to save the resolved iotlb data before
@@ -428,76 +419,6 @@ static inline void cpu_tb_jmp_cache_clear(CPUState *cpu)
extern bool mttcg_enabled;
#define qemu_tcg_mttcg_enabled() (mttcg_enabled)
-/**
- * cpu_paging_enabled:
- * @cpu: The CPU whose state is to be inspected.
- *
- * Returns: %true if paging is enabled, %false otherwise.
- */
-bool cpu_paging_enabled(const CPUState *cpu);
-
-/**
- * cpu_get_memory_mapping:
- * @cpu: The CPU whose memory mappings are to be obtained.
- * @list: Where to write the memory mappings to.
- * @errp: Pointer for reporting an #Error.
- */
-void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
- Error **errp);
-
-#if !defined(CONFIG_USER_ONLY)
-
-/**
- * cpu_write_elf64_note:
- * @f: pointer to a function that writes memory to a file
- * @cpu: The CPU whose memory is to be dumped
- * @cpuid: ID number of the CPU
- * @opaque: pointer to the CPUState struct
- */
-int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
- int cpuid, void *opaque);
-
-/**
- * cpu_write_elf64_qemunote:
- * @f: pointer to a function that writes memory to a file
- * @cpu: The CPU whose memory is to be dumped
- * @cpuid: ID number of the CPU
- * @opaque: pointer to the CPUState struct
- */
-int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
- void *opaque);
-
-/**
- * cpu_write_elf32_note:
- * @f: pointer to a function that writes memory to a file
- * @cpu: The CPU whose memory is to be dumped
- * @cpuid: ID number of the CPU
- * @opaque: pointer to the CPUState struct
- */
-int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
- int cpuid, void *opaque);
-
-/**
- * cpu_write_elf32_qemunote:
- * @f: pointer to a function that writes memory to a file
- * @cpu: The CPU whose memory is to be dumped
- * @cpuid: ID number of the CPU
- * @opaque: pointer to the CPUState struct
- */
-int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
- void *opaque);
-
-/**
- * cpu_get_crash_info:
- * @cpu: The CPU to get crash information for
- *
- * Gets the previously saved crash information.
- * Caller is responsible for freeing the data.
- */
-GuestPanicInformation *cpu_get_crash_info(CPUState *cpu);
-
-#endif /* !CONFIG_USER_ONLY */
-
/**
* CPUDumpFlags:
* @CPU_DUMP_CODE:
@@ -529,56 +450,6 @@ void cpu_dump_state(CPUState *cpu, FILE *f, int flags);
*/
void cpu_dump_statistics(CPUState *cpu, int flags);
-#ifndef CONFIG_USER_ONLY
-/**
- * cpu_get_phys_page_attrs_debug:
- * @cpu: The CPU to obtain the physical page address for.
- * @addr: The virtual address.
- * @attrs: Updated on return with the memory transaction attributes to use
- * for this access.
- *
- * Obtains the physical page corresponding to a virtual one, together
- * with the corresponding memory transaction attributes to use for the access.
- * Use it only for debugging because no protection checks are done.
- *
- * Returns: Corresponding physical page address or -1 if no page found.
- */
-hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
- MemTxAttrs *attrs);
-
-/**
- * cpu_get_phys_page_debug:
- * @cpu: The CPU to obtain the physical page address for.
- * @addr: The virtual address.
- *
- * Obtains the physical page corresponding to a virtual one.
- * Use it only for debugging because no protection checks are done.
- *
- * Returns: Corresponding physical page address or -1 if no page found.
- */
-hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
-
-/**
- * cpu_asidx_from_attrs:
- * @cpu: CPU
- * @attrs: memory transaction attributes
- *
- * Returns the address space index specifying the CPU AddressSpace
- * to use for a memory access with the given transaction attributes.
- */
-int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs);
-
-/**
- * cpu_virtio_is_big_endian:
- * @cpu: CPU
-
- * Returns %true if a CPU which supports runtime configurable endianness
- * is currently big-endian.
- */
-bool cpu_virtio_is_big_endian(CPUState *cpu);
-
-#endif /* CONFIG_USER_ONLY */
-
/**
* cpu_list_add:
* @cpu: The CPU to be added to the list of CPUs.
@@ -917,41 +788,6 @@ static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask)
return false;
}
-#ifndef CONFIG_USER_ONLY
-int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
- int flags, CPUWatchpoint **watchpoint);
-int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
- vaddr len, int flags);
-void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint);
-void cpu_watchpoint_remove_all(CPUState *cpu, int mask);
-
-/**
- * cpu_check_watchpoint:
- * @cpu: cpu context
- * @addr: guest virtual address
- * @len: access length
- * @attrs: memory access attributes
- * @flags: watchpoint access type
- * @ra: unwind return address
- *
- * Check for a watchpoint hit in [addr, addr+len) of the type
- * specified by @flags. Exit via exception with a hit.
- */
-void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
- MemTxAttrs attrs, int flags, uintptr_t ra);
-
-/**
- * cpu_watchpoint_address_matches:
- * @cpu: cpu context
- * @addr: guest virtual address
- * @len: access length
- *
- * Return the watchpoint flags that apply to [addr, addr+len).
- * If no watchpoint is registered for the range, the result is 0.
- */
-int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len);
-#endif
-
/**
* cpu_get_address_space:
* @cpu: CPU to get address space from
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 3f9a5199dd1..da66acdc87f 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -12,6 +12,15 @@
#include "hw/core/cpu.h"
+struct CPUWatchpoint {
+ vaddr vaddr;
+ vaddr len;
+ vaddr hitaddr;
+ MemTxAttrs hitattrs;
+ int flags; /* BP_* */
+ QTAILQ_ENTRY(CPUWatchpoint) entry;
+};
+
/*
* struct SysemuCPUOps: System operations specific to a CPU class
*/
@@ -86,4 +95,150 @@ typedef struct SysemuCPUOps {
const VMStateDescription *vmsd;
} SysemuCPUOps;
+/**
+ * cpu_paging_enabled:
+ * @cpu: The CPU whose state is to be inspected.
+ *
+ * Returns: %true if paging is enabled, %false otherwise.
+ */
+bool cpu_paging_enabled(const CPUState *cpu);
+
+/**
+ * cpu_get_memory_mapping:
+ * @cpu: The CPU whose memory mappings are to be obtained.
+ * @list: Where to write the memory mappings to.
+ * @errp: Pointer for reporting an #Error.
+ */
+void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
+ Error **errp);
+
+/**
+ * cpu_write_elf64_note:
+ * @f: pointer to a function that writes memory to a file
+ * @cpu: The CPU whose memory is to be dumped
+ * @cpuid: ID number of the CPU
+ * @opaque: pointer to the CPUState struct
+ */
+int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
+ int cpuid, void *opaque);
+
+/**
+ * cpu_write_elf64_qemunote:
+ * @f: pointer to a function that writes memory to a file
+ * @cpu: The CPU whose memory is to be dumped
+ * @cpuid: ID number of the CPU
+ * @opaque: pointer to the CPUState struct
+ */
+int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
+ void *opaque);
+
+/**
+ * cpu_write_elf32_note:
+ * @f: pointer to a function that writes memory to a file
+ * @cpu: The CPU whose memory is to be dumped
+ * @cpuid: ID number of the CPU
+ * @opaque: pointer to the CPUState struct
+ */
+int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
+ int cpuid, void *opaque);
+
+/**
+ * cpu_write_elf32_qemunote:
+ * @f: pointer to a function that writes memory to a file
+ * @cpu: The CPU whose memory is to be dumped
+ * @cpuid: ID number of the CPU
+ * @opaque: pointer to the CPUState struct
+ */
+int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
+ void *opaque);
+
+/**
+ * cpu_get_crash_info:
+ * @cpu: The CPU to get crash information for
+ *
+ * Gets the previously saved crash information.
+ * Caller is responsible for freeing the data.
+ */
+GuestPanicInformation *cpu_get_crash_info(CPUState *cpu);
+
+/**
+ * cpu_get_phys_page_attrs_debug:
+ * @cpu: The CPU to obtain the physical page address for.
+ * @addr: The virtual address.
+ * @attrs: Updated on return with the memory transaction attributes to use
+ * for this access.
+ *
+ * Obtains the physical page corresponding to a virtual one, together
+ * with the corresponding memory transaction attributes to use for the access.
+ * Use it only for debugging because no protection checks are done.
+ *
+ * Returns: Corresponding physical page address or -1 if no page found.
+ */
+hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
+ MemTxAttrs *attrs);
+
+/**
+ * cpu_get_phys_page_debug:
+ * @cpu: The CPU to obtain the physical page address for.
+ * @addr: The virtual address.
+ *
+ * Obtains the physical page corresponding to a virtual one.
+ * Use it only for debugging because no protection checks are done.
+ *
+ * Returns: Corresponding physical page address or -1 if no page found.
+ */
+hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+
+/**
+ * cpu_asidx_from_attrs:
+ * @cpu: CPU
+ * @attrs: memory transaction attributes
+ *
+ * Returns the address space index specifying the CPU AddressSpace
+ * to use for a memory access with the given transaction attributes.
+ */
+int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs);
+
+/**
+ * cpu_virtio_is_big_endian:
+ * @cpu: CPU
+
+ * Returns %true if a CPU which supports runtime configurable endianness
+ * is currently big-endian.
+ */
+bool cpu_virtio_is_big_endian(CPUState *cpu);
+
+int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
+ int flags, CPUWatchpoint **watchpoint);
+int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
+ vaddr len, int flags);
+void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint);
+void cpu_watchpoint_remove_all(CPUState *cpu, int mask);
+
+/**
+ * cpu_check_watchpoint:
+ * @cpu: cpu context
+ * @addr: guest virtual address
+ * @len: access length
+ * @attrs: memory access attributes
+ * @flags: watchpoint access type
+ * @ra: unwind return address
+ *
+ * Check for a watchpoint hit in [addr, addr+len) of the type
+ * specified by @flags. Exit via exception with a hit.
+ */
+void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
+ MemTxAttrs attrs, int flags, uintptr_t ra);
+
+/**
+ * cpu_watchpoint_address_matches:
+ * @cpu: cpu context
+ * @addr: guest virtual address
+ * @len: access length
+ *
+ * Return the watchpoint flags that apply to [addr, addr+len).
+ * If no watchpoint is registered for the range, the result is 0.
+ */
+int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len);
+
#endif /* SYSEMU_CPU_OPS_H */
diff --git a/gdbstub.c b/gdbstub.c
index f3614ebcc7a..0bc609fbf24 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -41,6 +41,7 @@
#include "exec/gdbstub.h"
#include "hw/cpu/cluster.h"
#include "hw/boards.h"
+#include "hw/core/sysemu-cpu-ops.h"
#endif
#define MAX_PACKET_LENGTH 4096
diff --git a/softmmu/physmem.c b/softmmu/physmem.c
index 19e0aa9836a..00e9729fa8a 100644
--- a/softmmu/physmem.c
+++ b/softmmu/physmem.c
@@ -28,6 +28,7 @@
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
#endif /* CONFIG_TCG */
+#include "hw/core/sysemu-cpu-ops.h"
#include "exec/exec-all.h"
#include "exec/target_page.h"
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread* [PATCH v4 28/28] cpu: Move sysemu specific declarations to 'sysemu-cpu-ops.h'
@ 2021-03-03 21:47 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-03 21:47 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Thomas Huth, Eduardo Habkost,
Philippe Mathieu-Daudé, Cornelia Huck, Richard Henderson,
Laurent Vivier, Philippe Mathieu-Daudé, qemu-s390x, qemu-arm,
qemu-ppc, Claudio Fontana, Paolo Bonzini, Alex Bennée
All these prototypes and declarations don't need to be exposed
on user-mode emulation. Move them to "sysemu-cpu-ops.h".
Suggested-by: Claudio Fontana <cfontana@suse.de>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 164 -------------------------------
include/hw/core/sysemu-cpu-ops.h | 155 +++++++++++++++++++++++++++++
gdbstub.c | 1 +
softmmu/physmem.c | 1 +
4 files changed, 157 insertions(+), 164 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 79dcc9a4e42..53598c02187 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -185,15 +185,6 @@ typedef struct CPUBreakpoint {
QTAILQ_ENTRY(CPUBreakpoint) entry;
} CPUBreakpoint;
-struct CPUWatchpoint {
- vaddr vaddr;
- vaddr len;
- vaddr hitaddr;
- MemTxAttrs hitattrs;
- int flags; /* BP_* */
- QTAILQ_ENTRY(CPUWatchpoint) entry;
-};
-
#ifdef CONFIG_PLUGIN
/*
* For plugins we sometime need to save the resolved iotlb data before
@@ -428,76 +419,6 @@ static inline void cpu_tb_jmp_cache_clear(CPUState *cpu)
extern bool mttcg_enabled;
#define qemu_tcg_mttcg_enabled() (mttcg_enabled)
-/**
- * cpu_paging_enabled:
- * @cpu: The CPU whose state is to be inspected.
- *
- * Returns: %true if paging is enabled, %false otherwise.
- */
-bool cpu_paging_enabled(const CPUState *cpu);
-
-/**
- * cpu_get_memory_mapping:
- * @cpu: The CPU whose memory mappings are to be obtained.
- * @list: Where to write the memory mappings to.
- * @errp: Pointer for reporting an #Error.
- */
-void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
- Error **errp);
-
-#if !defined(CONFIG_USER_ONLY)
-
-/**
- * cpu_write_elf64_note:
- * @f: pointer to a function that writes memory to a file
- * @cpu: The CPU whose memory is to be dumped
- * @cpuid: ID number of the CPU
- * @opaque: pointer to the CPUState struct
- */
-int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
- int cpuid, void *opaque);
-
-/**
- * cpu_write_elf64_qemunote:
- * @f: pointer to a function that writes memory to a file
- * @cpu: The CPU whose memory is to be dumped
- * @cpuid: ID number of the CPU
- * @opaque: pointer to the CPUState struct
- */
-int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
- void *opaque);
-
-/**
- * cpu_write_elf32_note:
- * @f: pointer to a function that writes memory to a file
- * @cpu: The CPU whose memory is to be dumped
- * @cpuid: ID number of the CPU
- * @opaque: pointer to the CPUState struct
- */
-int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
- int cpuid, void *opaque);
-
-/**
- * cpu_write_elf32_qemunote:
- * @f: pointer to a function that writes memory to a file
- * @cpu: The CPU whose memory is to be dumped
- * @cpuid: ID number of the CPU
- * @opaque: pointer to the CPUState struct
- */
-int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
- void *opaque);
-
-/**
- * cpu_get_crash_info:
- * @cpu: The CPU to get crash information for
- *
- * Gets the previously saved crash information.
- * Caller is responsible for freeing the data.
- */
-GuestPanicInformation *cpu_get_crash_info(CPUState *cpu);
-
-#endif /* !CONFIG_USER_ONLY */
-
/**
* CPUDumpFlags:
* @CPU_DUMP_CODE:
@@ -529,56 +450,6 @@ void cpu_dump_state(CPUState *cpu, FILE *f, int flags);
*/
void cpu_dump_statistics(CPUState *cpu, int flags);
-#ifndef CONFIG_USER_ONLY
-/**
- * cpu_get_phys_page_attrs_debug:
- * @cpu: The CPU to obtain the physical page address for.
- * @addr: The virtual address.
- * @attrs: Updated on return with the memory transaction attributes to use
- * for this access.
- *
- * Obtains the physical page corresponding to a virtual one, together
- * with the corresponding memory transaction attributes to use for the access.
- * Use it only for debugging because no protection checks are done.
- *
- * Returns: Corresponding physical page address or -1 if no page found.
- */
-hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
- MemTxAttrs *attrs);
-
-/**
- * cpu_get_phys_page_debug:
- * @cpu: The CPU to obtain the physical page address for.
- * @addr: The virtual address.
- *
- * Obtains the physical page corresponding to a virtual one.
- * Use it only for debugging because no protection checks are done.
- *
- * Returns: Corresponding physical page address or -1 if no page found.
- */
-hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
-
-/**
- * cpu_asidx_from_attrs:
- * @cpu: CPU
- * @attrs: memory transaction attributes
- *
- * Returns the address space index specifying the CPU AddressSpace
- * to use for a memory access with the given transaction attributes.
- */
-int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs);
-
-/**
- * cpu_virtio_is_big_endian:
- * @cpu: CPU
-
- * Returns %true if a CPU which supports runtime configurable endianness
- * is currently big-endian.
- */
-bool cpu_virtio_is_big_endian(CPUState *cpu);
-
-#endif /* CONFIG_USER_ONLY */
-
/**
* cpu_list_add:
* @cpu: The CPU to be added to the list of CPUs.
@@ -917,41 +788,6 @@ static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask)
return false;
}
-#ifndef CONFIG_USER_ONLY
-int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
- int flags, CPUWatchpoint **watchpoint);
-int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
- vaddr len, int flags);
-void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint);
-void cpu_watchpoint_remove_all(CPUState *cpu, int mask);
-
-/**
- * cpu_check_watchpoint:
- * @cpu: cpu context
- * @addr: guest virtual address
- * @len: access length
- * @attrs: memory access attributes
- * @flags: watchpoint access type
- * @ra: unwind return address
- *
- * Check for a watchpoint hit in [addr, addr+len) of the type
- * specified by @flags. Exit via exception with a hit.
- */
-void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
- MemTxAttrs attrs, int flags, uintptr_t ra);
-
-/**
- * cpu_watchpoint_address_matches:
- * @cpu: cpu context
- * @addr: guest virtual address
- * @len: access length
- *
- * Return the watchpoint flags that apply to [addr, addr+len).
- * If no watchpoint is registered for the range, the result is 0.
- */
-int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len);
-#endif
-
/**
* cpu_get_address_space:
* @cpu: CPU to get address space from
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 3f9a5199dd1..da66acdc87f 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -12,6 +12,15 @@
#include "hw/core/cpu.h"
+struct CPUWatchpoint {
+ vaddr vaddr;
+ vaddr len;
+ vaddr hitaddr;
+ MemTxAttrs hitattrs;
+ int flags; /* BP_* */
+ QTAILQ_ENTRY(CPUWatchpoint) entry;
+};
+
/*
* struct SysemuCPUOps: System operations specific to a CPU class
*/
@@ -86,4 +95,150 @@ typedef struct SysemuCPUOps {
const VMStateDescription *vmsd;
} SysemuCPUOps;
+/**
+ * cpu_paging_enabled:
+ * @cpu: The CPU whose state is to be inspected.
+ *
+ * Returns: %true if paging is enabled, %false otherwise.
+ */
+bool cpu_paging_enabled(const CPUState *cpu);
+
+/**
+ * cpu_get_memory_mapping:
+ * @cpu: The CPU whose memory mappings are to be obtained.
+ * @list: Where to write the memory mappings to.
+ * @errp: Pointer for reporting an #Error.
+ */
+void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
+ Error **errp);
+
+/**
+ * cpu_write_elf64_note:
+ * @f: pointer to a function that writes memory to a file
+ * @cpu: The CPU whose memory is to be dumped
+ * @cpuid: ID number of the CPU
+ * @opaque: pointer to the CPUState struct
+ */
+int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
+ int cpuid, void *opaque);
+
+/**
+ * cpu_write_elf64_qemunote:
+ * @f: pointer to a function that writes memory to a file
+ * @cpu: The CPU whose memory is to be dumped
+ * @cpuid: ID number of the CPU
+ * @opaque: pointer to the CPUState struct
+ */
+int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
+ void *opaque);
+
+/**
+ * cpu_write_elf32_note:
+ * @f: pointer to a function that writes memory to a file
+ * @cpu: The CPU whose memory is to be dumped
+ * @cpuid: ID number of the CPU
+ * @opaque: pointer to the CPUState struct
+ */
+int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
+ int cpuid, void *opaque);
+
+/**
+ * cpu_write_elf32_qemunote:
+ * @f: pointer to a function that writes memory to a file
+ * @cpu: The CPU whose memory is to be dumped
+ * @cpuid: ID number of the CPU
+ * @opaque: pointer to the CPUState struct
+ */
+int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
+ void *opaque);
+
+/**
+ * cpu_get_crash_info:
+ * @cpu: The CPU to get crash information for
+ *
+ * Gets the previously saved crash information.
+ * Caller is responsible for freeing the data.
+ */
+GuestPanicInformation *cpu_get_crash_info(CPUState *cpu);
+
+/**
+ * cpu_get_phys_page_attrs_debug:
+ * @cpu: The CPU to obtain the physical page address for.
+ * @addr: The virtual address.
+ * @attrs: Updated on return with the memory transaction attributes to use
+ * for this access.
+ *
+ * Obtains the physical page corresponding to a virtual one, together
+ * with the corresponding memory transaction attributes to use for the access.
+ * Use it only for debugging because no protection checks are done.
+ *
+ * Returns: Corresponding physical page address or -1 if no page found.
+ */
+hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
+ MemTxAttrs *attrs);
+
+/**
+ * cpu_get_phys_page_debug:
+ * @cpu: The CPU to obtain the physical page address for.
+ * @addr: The virtual address.
+ *
+ * Obtains the physical page corresponding to a virtual one.
+ * Use it only for debugging because no protection checks are done.
+ *
+ * Returns: Corresponding physical page address or -1 if no page found.
+ */
+hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+
+/**
+ * cpu_asidx_from_attrs:
+ * @cpu: CPU
+ * @attrs: memory transaction attributes
+ *
+ * Returns the address space index specifying the CPU AddressSpace
+ * to use for a memory access with the given transaction attributes.
+ */
+int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs);
+
+/**
+ * cpu_virtio_is_big_endian:
+ * @cpu: CPU
+
+ * Returns %true if a CPU which supports runtime configurable endianness
+ * is currently big-endian.
+ */
+bool cpu_virtio_is_big_endian(CPUState *cpu);
+
+int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
+ int flags, CPUWatchpoint **watchpoint);
+int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
+ vaddr len, int flags);
+void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint);
+void cpu_watchpoint_remove_all(CPUState *cpu, int mask);
+
+/**
+ * cpu_check_watchpoint:
+ * @cpu: cpu context
+ * @addr: guest virtual address
+ * @len: access length
+ * @attrs: memory access attributes
+ * @flags: watchpoint access type
+ * @ra: unwind return address
+ *
+ * Check for a watchpoint hit in [addr, addr+len) of the type
+ * specified by @flags. Exit via exception with a hit.
+ */
+void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
+ MemTxAttrs attrs, int flags, uintptr_t ra);
+
+/**
+ * cpu_watchpoint_address_matches:
+ * @cpu: cpu context
+ * @addr: guest virtual address
+ * @len: access length
+ *
+ * Return the watchpoint flags that apply to [addr, addr+len).
+ * If no watchpoint is registered for the range, the result is 0.
+ */
+int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len);
+
#endif /* SYSEMU_CPU_OPS_H */
diff --git a/gdbstub.c b/gdbstub.c
index f3614ebcc7a..0bc609fbf24 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -41,6 +41,7 @@
#include "exec/gdbstub.h"
#include "hw/cpu/cluster.h"
#include "hw/boards.h"
+#include "hw/core/sysemu-cpu-ops.h"
#endif
#define MAX_PACKET_LENGTH 4096
diff --git a/softmmu/physmem.c b/softmmu/physmem.c
index 19e0aa9836a..00e9729fa8a 100644
--- a/softmmu/physmem.c
+++ b/softmmu/physmem.c
@@ -28,6 +28,7 @@
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
#endif /* CONFIG_TCG */
+#include "hw/core/sysemu-cpu-ops.h"
#include "exec/exec-all.h"
#include "exec/target_page.h"
--
2.26.2
^ permalink raw reply related [flat|nested] 79+ messages in thread
* Re: [PATCH v4 00/28] cpu: Introduce SysemuCPUOps structure, remove watchpoints from usermode
2021-03-03 21:46 ` Philippe Mathieu-Daudé
` (28 preceding siblings ...)
(?)
@ 2021-03-04 1:52 ` Richard Henderson
2021-04-22 10:39 ` Philippe Mathieu-Daudé
-1 siblings, 1 reply; 79+ messages in thread
From: Richard Henderson @ 2021-03-04 1:52 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Peter Maydell, Thomas Huth, Cornelia Huck, Laurent Vivier,
qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana, Paolo Bonzini,
Alex Bennée
On 3/3/21 1:46 PM, Philippe Mathieu-Daudé wrote:
> Patches 1-6 are generic cleanups.
> Patches 7-15 move from CPUClass to SysemuCPUOps
> Patch 16 restricts SysemuCPUOps to sysemu
> Patches 17-26 remove watchpoint code from user emulation
> Patches 27-28 remove USER_ONLY #ifdef'ry from "cpu.h"
Patches 1-18:
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
While mst has asked for a name change vs patch 4, I think that if we do that it
should be separate, because it would involve a rename through hw/ as well.
The watchpoint patches that follow need some more careful thought.
r~
^ permalink raw reply [flat|nested] 79+ messages in thread* Re: [PATCH v4 00/28] cpu: Introduce SysemuCPUOps structure, remove watchpoints from usermode
2021-03-04 1:52 ` [PATCH v4 00/28] cpu: Introduce SysemuCPUOps structure, remove watchpoints from usermode Richard Henderson
@ 2021-04-22 10:39 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 79+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 10:39 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Peter Maydell, Thomas Huth, Cornelia Huck, Laurent Vivier,
qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana, Paolo Bonzini
On 3/4/21 2:52 AM, Richard Henderson wrote:
> On 3/3/21 1:46 PM, Philippe Mathieu-Daudé wrote:
>> Patches 1-6 are generic cleanups.
>> Patches 7-15 move from CPUClass to SysemuCPUOps
>> Patch 16 restricts SysemuCPUOps to sysemu
>> Patches 17-26 remove watchpoint code from user emulation
>> Patches 27-28 remove USER_ONLY #ifdef'ry from "cpu.h"
>
> Patches 1-18:
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
> While mst has asked for a name change vs patch 4, I think that if we do
> that it should be separate, because it would involve a rename through
> hw/ as well.
>
> The watchpoint patches that follow need some more careful thought.
OK. I'll respin without the watchpoint part (first half).
Thanks,
Phil.
^ permalink raw reply [flat|nested] 79+ messages in thread