[PATCH] MIPS: Support large stack.

[PATCH] MIPS: Support large stack.

[HongJieDeng]

From: Hongjie Deng <deng.hongjie@h3c.com>

We need more stack space, xori/ori no longer apply when
 _THREAD_MASK exceeds 16 bits

Signed-off-by: Hongjie Deng <deng.hongjie@h3c.com>
---
 arch/mips/include/asm/stackframe.h | 8 ++++++++
 arch/mips/kernel/genex.S           | 6 ++++++
 2 files changed, 14 insertions(+)

diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index aa430a6..6ebc39f 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -278,8 +278,16 @@
 		sll	k0, 3		/* extract cu0 bit */
 		bltz	k0, 9f
 
+#if    _THREAD_MASK  < (1 << 16 - 1)
 		ori	$28, sp, _THREAD_MASK
 		xori	$28, _THREAD_MASK
+#else
+		li      $28,   _THREAD_MASK
+		or  $28,  sp,  $28
+		li  $24, _THREAD_MASK
+		xor   $28, $28, $24
+#endif
+
 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 		.set    mips64
 		pref    0, 0($28)       /* Prefetch the current pointer */
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index bcce32a..5ea4fe4 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -662,8 +662,14 @@ isrdhwr:
 #endif
 	MTC0	k0, CP0_EPC
 	/* I hope three instructions between MTC0 and ERET are enough... */
+#if    _THREAD_MASK  < (1 << 16 - 1)
 	ori	k1, _THREAD_MASK
 	xori	k1, _THREAD_MASK
+#else
+	li  $24 ,_THREAD_MASK
+	or   k1, k1, $24
+	xor   k1, k1, $24
+#endif
 	LONG_L	v1, TI_TP_VALUE(k1)
 	.set	push
 	.set	arch=r4000
-- 
1.8.3.1

Re: [PATCH] MIPS: Support large stack.

[Jiaxun Yang]

在 2021/3/5 11:12, HongJieDeng 写道:
> From: Hongjie Deng <deng.hongjie@h3c.com>
>
> We need more stack space, xori/ori no longer apply when
>   _THREAD_MASK exceeds 16 bits
>
> Signed-off-by: Hongjie Deng <deng.hongjie@h3c.com>
> ---
>   arch/mips/include/asm/stackframe.h | 8 ++++++++
>   arch/mips/kernel/genex.S           | 6 ++++++
>   2 files changed, 14 insertions(+)
>
> diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
> index aa430a6..6ebc39f 100644
> --- a/arch/mips/include/asm/stackframe.h
> +++ b/arch/mips/include/asm/stackframe.h
> @@ -278,8 +278,16 @@
>   		sll	k0, 3		/* extract cu0 bit */
>   		bltz	k0, 9f
>   
> +#if    _THREAD_MASK  < (1 << 16 - 1)
>   		ori	$28, sp, _THREAD_MASK
>   		xori	$28, _THREAD_MASK
> +#else
> +		li      $28,   _THREAD_MASK
> +		or  $28,  sp,  $28
> +		li  $24, _THREAD_MASK
> +		xor   $28, $28, $24

Hi Hongjie,

li breaks MIPS64, please try PTR_LI instead.
Also loading immediate cost a lot on MIPS,
you may save a unnecessary li by:

+		PTR_LI  v1,   _THREAD_MASK
+		or      gp,  sp,  v1
+		xor     gp,  gp,  v1

Also clobber v0/v1 seems much more reasonable than $24 here....

> +#endif
> +
>   #ifdef CONFIG_CPU_CAVIUM_OCTEON
>   		.set    mips64
>   		pref    0, 0($28)       /* Prefetch the current pointer */
> diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
> index bcce32a..5ea4fe4 100644
> --- a/arch/mips/kernel/genex.S
> +++ b/arch/mips/kernel/genex.S
> @@ -662,8 +662,14 @@ isrdhwr:
>   #endif
>   	MTC0	k0, CP0_EPC
>   	/* I hope three instructions between MTC0 and ERET are enough... */
> +#if    _THREAD_MASK  < (1 << 16 - 1)
>   	ori	k1, _THREAD_MASK
>   	xori	k1, _THREAD_MASK
> +#else
> +	li  $24 ,_THREAD_MASK
> +	or   k1, k1, $24
> +	xor   k1, k1, $24
> +#endif
Ditto.

Actually another possible solution could be `.set at=v1` around it
and let aeembler to decide if it needs a extra register.

Thanks.

- Jiaxun
>   	LONG_L	v1, TI_TP_VALUE(k1)
>   	.set	push
>   	.set	arch=r4000

Re: [PATCH] MIPS: Support large stack.

[Thomas Bogendoerfer]

On Fri, Mar 05, 2021 at 11:12:57AM +0800, HongJieDeng wrote:
> From: Hongjie Deng <deng.hongjie@h3c.com>
> 
> We need more stack space, xori/ori no longer apply when
>  _THREAD_MASK exceeds 16 bits

who is we and why do need more ?

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]