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From: Ard Biesheuvel <ardb@kernel.org>
To: linux-arm-kernel@lists.infradead.org
Cc: Ard Biesheuvel <ardb@kernel.org>,
	Mark Salter <msalter@redhat.com>, Will Deacon <will@kernel.org>,
	James Morse <james.morse@arm.com>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Mark Rutland <mark.rutland@arm.com>,
	Steve Capper <steve.capper@arm.com>,
	Anshuman Khandual <anshuman.khandual@arm.com>
Subject: [PATCH 4/5] arm64: mm: get rid of idmap_ptrs_per_pgd handling
Date: Wed, 10 Mar 2021 18:15:14 +0100	[thread overview]
Message-ID: <20210310171515.416643-5-ardb@kernel.org> (raw)
In-Reply-To: <20210310171515.416643-1-ardb@kernel.org>

idmap_ptrs_per_pgd is stored and re-loaded in the very early boot path,
and never referenced again. So a variable is not needed here.

Furthermore, given that on the code path in question, PTRS_PER_PGD and
'1 << (PHYS_MASK_SHIFT - PGDIR_SHIFT)' are guaranteed to be equal unless
- the kernel was built for 48-bit VAs and 52-bit PAs, and
- the kernel was loaded outside of the 48-bit addressable physical memory
  space (which is not supported by EFI to begin with),
it seems reasonable to simply drop this code path altogether.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
---
 arch/arm64/include/asm/mmu_context.h | 1 -
 arch/arm64/kernel/head.S             | 9 +--------
 arch/arm64/mm/mmu.c                  | 1 -
 3 files changed, 1 insertion(+), 10 deletions(-)

diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h
index bd02e99b1a4c..1307f5e27a5a 100644
--- a/arch/arm64/include/asm/mmu_context.h
+++ b/arch/arm64/include/asm/mmu_context.h
@@ -61,7 +61,6 @@ static inline void cpu_switch_mm(pgd_t *pgd, struct mm_struct *mm)
  * physical memory, in which case it will be smaller.
  */
 extern u64 idmap_t0sz;
-extern u64 idmap_ptrs_per_pgd;
 
 /*
  * Ensure TCR.T0SZ is set to the provided value.
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index f65d17a90204..da6e99fa4e08 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -344,16 +344,9 @@ SYM_FUNC_START_LOCAL(__create_page_tables)
 
 	mov	x4, EXTRA_PTRS
 	create_table_entry x0, x3, EXTRA_SHIFT, x4, x5, x6
-#else
-	/*
-	 * If VA_BITS == 48, we don't have to configure an additional
-	 * translation level, but the top-level table has more entries.
-	 */
-	mov	x4, #1 << (PHYS_MASK_SHIFT - PGDIR_SHIFT)
-	str_l	x4, idmap_ptrs_per_pgd, x5
 #endif
 1:
-	ldr_l	x4, idmap_ptrs_per_pgd
+	mov	x4, PTRS_PER_PGD
 	mov	x5, x3				// __pa(__idmap_text_start)
 	adr_l	x6, __idmap_text_end		// __pa(__idmap_text_end)
 
diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
index 338658cd1bea..569cf07ddb91 100644
--- a/arch/arm64/mm/mmu.c
+++ b/arch/arm64/mm/mmu.c
@@ -41,7 +41,6 @@
 #define NO_CONT_MAPPINGS	BIT(1)
 
 u64 idmap_t0sz = TCR_T0SZ(VA_BITS_MIN);
-u64 idmap_ptrs_per_pgd = PTRS_PER_PGD;
 
 #ifdef CONFIG_ARM64_VA_BITS_52
 u64 __section(".mmuoff.data.write") vabits_actual;
-- 
2.30.1


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  parent reply	other threads:[~2021-03-10 17:17 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-10 17:15 [PATCH 0/5] arm64: some 52-bit cleanups Ard Biesheuvel
2021-03-10 17:15 ` [PATCH 1/5] arm64: mm: use a 48-bit ID map when possible on 52-bit VA builds Ard Biesheuvel
2021-03-11  9:46   ` Will Deacon
2021-03-11 11:58     ` Ard Biesheuvel
2021-03-10 17:15 ` [PATCH 2/5] arm64: mm: remove unused __cpu_uses_extended_idmap[_level()] Ard Biesheuvel
2021-03-10 17:15 ` [PATCH 3/5] arm64: mm: use a compile time constant for vabits_actual when possible Ard Biesheuvel
2021-03-11  9:49   ` Will Deacon
2021-03-11 17:23     ` Ard Biesheuvel
2021-03-11 18:44       ` Will Deacon
2021-03-11 18:52         ` Ard Biesheuvel
2021-03-10 17:15 ` Ard Biesheuvel [this message]
2021-03-10 17:15 ` [PATCH 5/5] arm64: mm: switch to 52-bit ID map on 52-bit VA capable systems Ard Biesheuvel
2021-03-11 13:26 ` [PATCH 0/5] arm64: some 52-bit cleanups Will Deacon

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