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From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
To: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>,
	John Crispin <john@phrozen.org>,
	linux-mips@vger.kernel.org, linux-mediatek@lists.infradead.org,
	linux-kernel@vger.kernel.org, stable@vger.kernel.org
Subject: Re: [PATCH] MIPS: pci-mt7620: fix PLL lock check
Date: Fri, 12 Mar 2021 11:27:30 +0100	[thread overview]
Message-ID: <20210312102730.GC7027@alpha.franken.de> (raw)
In-Reply-To: <20210307041724.3185139-1-ilya.lipnitskiy@gmail.com>

On Sat, Mar 06, 2021 at 08:17:24PM -0800, Ilya Lipnitskiy wrote:
> Upstream a long-standing OpenWrt patch [0] that fixes MT7620 PCIe PLL
> lock check. The existing code checks the wrong register bit: PPLL_SW_SET
> is not defined in PPLL_CFG1 and bit 31 of PPLL_CFG1 is marked as reserved
> in the MT7620 Programming Guide. The correct bit to check for PLL lock
> is PPLL_LD (bit 23).
> 
> Also reword the error message for clarity.
> 
> Without this change it is unlikely that this driver ever worked with
> mainline kernel.
> 
> [0]: https://lists.infradead.org/pipermail/lede-commits/2017-July/004441.html
> 
> Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
> Cc: John Crispin <john@phrozen.org>
> Cc: linux-mips@vger.kernel.org
> Cc: linux-mediatek@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Cc: stable@vger.kernel.org
> ---
>  arch/mips/pci/pci-mt7620.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)

applied to mips-next.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

WARNING: multiple messages have this Message-ID (diff)
From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
To: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>,
	John Crispin <john@phrozen.org>,
	linux-mips@vger.kernel.org, linux-mediatek@lists.infradead.org,
	linux-kernel@vger.kernel.org, stable@vger.kernel.org
Subject: Re: [PATCH] MIPS: pci-mt7620: fix PLL lock check
Date: Fri, 12 Mar 2021 11:27:30 +0100	[thread overview]
Message-ID: <20210312102730.GC7027@alpha.franken.de> (raw)
In-Reply-To: <20210307041724.3185139-1-ilya.lipnitskiy@gmail.com>

On Sat, Mar 06, 2021 at 08:17:24PM -0800, Ilya Lipnitskiy wrote:
> Upstream a long-standing OpenWrt patch [0] that fixes MT7620 PCIe PLL
> lock check. The existing code checks the wrong register bit: PPLL_SW_SET
> is not defined in PPLL_CFG1 and bit 31 of PPLL_CFG1 is marked as reserved
> in the MT7620 Programming Guide. The correct bit to check for PLL lock
> is PPLL_LD (bit 23).
> 
> Also reword the error message for clarity.
> 
> Without this change it is unlikely that this driver ever worked with
> mainline kernel.
> 
> [0]: https://lists.infradead.org/pipermail/lede-commits/2017-July/004441.html
> 
> Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
> Cc: John Crispin <john@phrozen.org>
> Cc: linux-mips@vger.kernel.org
> Cc: linux-mediatek@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Cc: stable@vger.kernel.org
> ---
>  arch/mips/pci/pci-mt7620.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)

applied to mips-next.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

  reply	other threads:[~2021-03-12 10:35 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-07  4:17 [PATCH] MIPS: pci-mt7620: fix PLL lock check Ilya Lipnitskiy
2021-03-07  4:17 ` Ilya Lipnitskiy
2021-03-12 10:27 ` Thomas Bogendoerfer [this message]
2021-03-12 10:27   ` Thomas Bogendoerfer

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