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From: Shawn Guo <shawnguo@kernel.org>
To: Vladimir Oltean <olteanv@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
	netdev@vger.kernel.org,
	Alex Marginean <alexandru.marginean@nxp.com>,
	Claudiu Manoil <claudiu.manoil@nxp.com>,
	Michael Walle <michael@walle.cc>,
	Vladimir Oltean <vladimir.oltean@nxp.com>
Subject: Re: [PATCH devicetree] arm64: dts: ls1028a: set up the real link speed for ENETC port 2
Date: Mon, 15 Mar 2021 14:01:21 +0800	[thread overview]
Message-ID: <20210315060121.GH11246@dragon> (raw)
In-Reply-To: <20210308130834.2994658-1-olteanv@gmail.com>

On Mon, Mar 08, 2021 at 03:08:34PM +0200, Vladimir Oltean wrote:
> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> 
> In NXP LS1028A there is a MAC-to-MAC internal link between enetc_port2
> and mscc_felix_port4. This link operates at 2.5Gbps and is described as
> such for the mscc_felix_port4 node.
> 
> The reason for the discrepancy is a limitation in the PHY library
> support for fixed-link nodes. Due to the fact that the PHY library
> registers a software PHY which emulates the clause 22 register map, the
> drivers/net/phy/fixed_phy.c driver only supports speeds up to 1Gbps.
> 
> The mscc_felix_port4 node is probed by DSA, which does not use the PHY
> library directly, but phylink, and phylink has a different representation
> for fixed-link nodes, one that does not have the limitation of not being
> able to represent speeds > 1Gbps.
> 
> Since the enetc driver was converted to phylink too as of commit
> 71b77a7a27a3 ("enetc: Migrate to PHYLINK and PCS_LYNX"), the limitation
> has been practically lifted there too, and we can describe the real link
> speed in the device tree now.
> 
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>

Applied, thanks.

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WARNING: multiple messages have this Message-ID (diff)
From: Shawn Guo <shawnguo@kernel.org>
To: Vladimir Oltean <olteanv@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
	netdev@vger.kernel.org,
	Alex Marginean <alexandru.marginean@nxp.com>,
	Claudiu Manoil <claudiu.manoil@nxp.com>,
	Michael Walle <michael@walle.cc>,
	Vladimir Oltean <vladimir.oltean@nxp.com>
Subject: Re: [PATCH devicetree] arm64: dts: ls1028a: set up the real link speed for ENETC port 2
Date: Mon, 15 Mar 2021 14:01:21 +0800	[thread overview]
Message-ID: <20210315060121.GH11246@dragon> (raw)
In-Reply-To: <20210308130834.2994658-1-olteanv@gmail.com>

On Mon, Mar 08, 2021 at 03:08:34PM +0200, Vladimir Oltean wrote:
> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> 
> In NXP LS1028A there is a MAC-to-MAC internal link between enetc_port2
> and mscc_felix_port4. This link operates at 2.5Gbps and is described as
> such for the mscc_felix_port4 node.
> 
> The reason for the discrepancy is a limitation in the PHY library
> support for fixed-link nodes. Due to the fact that the PHY library
> registers a software PHY which emulates the clause 22 register map, the
> drivers/net/phy/fixed_phy.c driver only supports speeds up to 1Gbps.
> 
> The mscc_felix_port4 node is probed by DSA, which does not use the PHY
> library directly, but phylink, and phylink has a different representation
> for fixed-link nodes, one that does not have the limitation of not being
> able to represent speeds > 1Gbps.
> 
> Since the enetc driver was converted to phylink too as of commit
> 71b77a7a27a3 ("enetc: Migrate to PHYLINK and PCS_LYNX"), the limitation
> has been practically lifted there too, and we can describe the real link
> speed in the device tree now.
> 
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>

Applied, thanks.

  reply	other threads:[~2021-03-15  6:03 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-08 13:08 [PATCH devicetree] arm64: dts: ls1028a: set up the real link speed for ENETC port 2 Vladimir Oltean
2021-03-08 13:08 ` Vladimir Oltean
2021-03-15  6:01 ` Shawn Guo [this message]
2021-03-15  6:01   ` Shawn Guo

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