From: "Marek Behún" <kabel@kernel.org>
To: netdev@vger.kernel.org, Andrew Lunn <andrew@lunn.ch>,
"David S . Miller" <davem@davemloft.net>,
Florian Fainelli <f.fainelli@gmail.com>,
Heiner Kallweit <hkallweit1@gmail.com>,
Russell King <rmk+kernel@armlinux.org.uk>,
kuba@kernel.org
Cc: "Marek Behún" <kabel@kernel.org>
Subject: [PATCH net-next v2 04/12] net: phy: marvell10g: indicate 88X33X0 only port control registers
Date: Thu, 25 Mar 2021 14:12:42 +0100 [thread overview]
Message-ID: <20210325131250.15901-5-kabel@kernel.org> (raw)
In-Reply-To: <20210325131250.15901-1-kabel@kernel.org>
Indicate via register names registers that are only valid for 88X33X0,
not for 88E21X0.
Signed-off-by: Marek Behún <kabel@kernel.org>
---
drivers/net/phy/marvell10g.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 881a0717846e..7552a658a513 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -78,10 +78,10 @@ enum {
/* Vendor2 MMD registers */
MV_V2_PORT_CTRL = 0xf001,
- MV_V2_PORT_CTRL_SWRST = BIT(15),
- MV_V2_PORT_CTRL_PWRDOWN = BIT(11),
- MV_V2_PORT_CTRL_MACTYPE_MASK = 0x7,
- MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH = 0x6,
+ MV_V2_PORT_CTRL_PWRDOWN = BIT(11),
+ MV_V2_33X0_PORT_CTRL_SWRST = BIT(15),
+ MV_V2_33X0_PORT_CTRL_MACTYPE_MASK = 0x7,
+ MV_V2_33X0_PORT_CTRL_MACTYPE_RATE_MATCH = 0x6,
/* Temperature control/read registers (88X3310 only) */
MV_V2_TEMP_CTRL = 0xf08a,
MV_V2_TEMP_CTRL_MASK = 0xc000,
@@ -268,7 +268,7 @@ static int mv3310_power_up(struct phy_device *phydev)
return ret;
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
- MV_V2_PORT_CTRL_SWRST);
+ MV_V2_33X0_PORT_CTRL_SWRST);
}
static int mv3310_reset(struct phy_device *phydev, u32 unit)
@@ -479,8 +479,8 @@ static int mv3310_config_init(struct phy_device *phydev)
val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
if (val < 0)
return val;
- priv->rate_match = ((val & MV_V2_PORT_CTRL_MACTYPE_MASK) ==
- MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH);
+ priv->rate_match = ((val & MV_V2_33X0_PORT_CTRL_MACTYPE_MASK) ==
+ MV_V2_33X0_PORT_CTRL_MACTYPE_RATE_MATCH);
/* Enable EDPD mode - saving 600mW */
return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
--
2.26.2
next prev parent reply other threads:[~2021-03-25 13:14 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-25 13:12 [PATCH net-next v2 00/12] net: phy: marvell10g updates Marek Behún
2021-03-25 13:12 ` [PATCH net-next v2 01/12] net: phy: marvell10g: rename register Marek Behún
2021-03-25 13:12 ` [PATCH net-next v2 02/12] net: phy: marvell10g: fix typo Marek Behún
2021-03-25 13:12 ` [PATCH net-next v2 03/12] net: phy: marvell10g: allow 5gbase-r and usxgmii Marek Behún
2021-03-25 13:12 ` Marek Behún [this message]
2021-03-25 13:12 ` [PATCH net-next v2 05/12] net: phy: marvell10g: add MACTYPE definitions for 88X33X0/88X33X0P Marek Behún
2021-03-25 13:12 ` [PATCH net-next v2 06/12] net: phy: marvell10g: add MACTYPE definitions for 88E21XX Marek Behún
2021-03-25 13:12 ` [PATCH net-next v2 07/12] net: phy: marvell10g: add code to determine number of ports Marek Behún
2021-03-25 13:12 ` [PATCH net-next v2 08/12] net: phy: marvell10g: support all rate matching modes Marek Behún
2021-03-25 13:12 ` [PATCH net-next v2 09/12] net: phy: marvell10g: support other MACTYPEs Marek Behún
2021-03-25 13:12 ` [PATCH net-next v2 10/12] net: phy: add constants for 2.5G and 5G speed in PCS speed register Marek Behún
2021-03-25 13:12 ` [PATCH net-next v2 11/12] net: phy: marvell10g: print exact model Marek Behún
2021-03-25 15:36 ` Marek Behún
2021-03-25 15:54 ` Russell King - ARM Linux admin
2021-03-25 16:56 ` Marek Behún
2021-03-25 20:29 ` Marek Behún
2021-03-25 20:44 ` Heiner Kallweit
2021-03-25 20:54 ` Marek Behún
2021-03-26 9:07 ` Russell King - ARM Linux admin
2021-03-26 11:11 ` Marek Behún
2021-03-25 13:12 ` [PATCH net-next v2 12/12] net: phy: marvell10g: better check for compatible interface Marek Behún
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