Re: [PATCH 1/2] drivers/perf: hisi: Add driver for HiSilicon PCIe PMU

[kernel test robot <lkp@intel.com>]

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Hi Qi,

I love your patch! Perhaps something to improve:

[auto build test WARNING on linus/master]
[also build test WARNING on v5.12-rc6]
[cannot apply to next-20210407]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Qi-Liu/drivers-perf-hisi-Add-support-for-PCIe-PMU/20210407-175356
base:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 2d743660786ec51f5c1fefd5782bbdee7b227db0
config: arm64-allyesconfig (attached as .config)
compiler: aarch64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/32d06137b5ddb94f1e951d1252994e7178fe5e8e
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Qi-Liu/drivers-perf-hisi-Add-support-for-PCIe-PMU/20210407-175356
        git checkout 32d06137b5ddb94f1e951d1252994e7178fe5e8e
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/perf/pci/hisilicon/hisi_pcie_pmu.c:447:6: warning: no previous prototype for 'hisi_pcie_pmu_read' [-Wmissing-prototypes]
     447 | void hisi_pcie_pmu_read(struct perf_event *event)
         |      ^~~~~~~~~~~~~~~~~~
>> drivers/perf/pci/hisilicon/hisi_pcie_pmu.c:530:6: warning: no previous prototype for 'hisi_pcie_pmu_start' [-Wmissing-prototypes]
     530 | void hisi_pcie_pmu_start(struct perf_event *event, int flags)
         |      ^~~~~~~~~~~~~~~~~~~
>> drivers/perf/pci/hisilicon/hisi_pcie_pmu.c:558:6: warning: no previous prototype for 'hisi_pcie_pmu_stop' [-Wmissing-prototypes]
     558 | void hisi_pcie_pmu_stop(struct perf_event *event, int flags)
         |      ^~~~~~~~~~~~~~~~~~
>> drivers/perf/pci/hisilicon/hisi_pcie_pmu.c:577:5: warning: no previous prototype for 'hisi_pcie_pmu_add' [-Wmissing-prototypes]
     577 | int hisi_pcie_pmu_add(struct perf_event *event, int flags)
         |     ^~~~~~~~~~~~~~~~~
>> drivers/perf/pci/hisilicon/hisi_pcie_pmu.c:600:6: warning: no previous prototype for 'hisi_pcie_pmu_del' [-Wmissing-prototypes]
     600 | void hisi_pcie_pmu_del(struct perf_event *event, int flags)
         |      ^~~~~~~~~~~~~~~~~
>> drivers/perf/pci/hisilicon/hisi_pcie_pmu.c:610:6: warning: no previous prototype for 'hisi_pcie_pmu_enable' [-Wmissing-prototypes]
     610 | void hisi_pcie_pmu_enable(struct pmu *pmu)
         |      ^~~~~~~~~~~~~~~~~~~~
>> drivers/perf/pci/hisilicon/hisi_pcie_pmu.c:626:6: warning: no previous prototype for 'hisi_pcie_pmu_disable' [-Wmissing-prototypes]
     626 | void hisi_pcie_pmu_disable(struct pmu *pmu)
         |      ^~~~~~~~~~~~~~~~~~~~~


vim +/hisi_pcie_pmu_read +447 drivers/perf/pci/hisilicon/hisi_pcie_pmu.c

   446	
 > 447	void hisi_pcie_pmu_read(struct perf_event *event)
   448	{
   449		struct hw_perf_event *hwc = &event->hw;
   450		struct hw_perf_event_extra *hwc_ext = &hwc->extra_reg;
   451		u64 new_cnt_ext, prev_cnt_ext;
   452		u64 new_cnt, prev_cnt, delta;
   453	
   454		hwc_ext = &hwc->extra_reg;
   455		do {
   456			prev_cnt = local64_read(&hwc->prev_count);
   457			prev_cnt_ext = hwc_ext->config;
   458			hisi_pcie_pmu_read_counter(event, &new_cnt, &new_cnt_ext);
   459		} while (local64_cmpxchg(&hwc->prev_count, prev_cnt,
   460					 new_cnt) != prev_cnt);
   461	
   462		hwc_ext->config = new_cnt_ext;
   463	
   464		delta = hisi_pcie_pmu_process_data(event, new_cnt - prev_cnt,
   465						   new_cnt_ext - prev_cnt_ext);
   466		local64_add(delta, &event->count);
   467	}
   468	
   469	static void hisi_pcie_pmu_set_period(struct perf_event *event)
   470	{
   471		struct hw_perf_event *hwc = &event->hw;
   472		struct hw_perf_event_extra *hwc_ext;
   473		u64 val = BIT_ULL(HISI_PCIE_COUNTER_BITS - 1);
   474	
   475		hwc_ext = &hwc->extra_reg;
   476		local64_set(&hwc->prev_count, val);
   477		hwc_ext->config = 0;
   478		hisi_pcie_pmu_write_counter(event, val, 0);
   479	}
   480	
   481	static void hisi_pcie_pmu_enable_counter(struct hisi_pcie_pmu *pcie_pmu,
   482						 struct hw_perf_event *hwc)
   483	{
   484		u32 idx = hwc->idx;
   485		u64 val;
   486	
   487		val = hisi_pcie_pmu_readq(pcie_pmu, HISI_PCIE_EVENT_CTRL, idx);
   488		val |= HISI_PCIE_EVENT_EN;
   489		hisi_pcie_pmu_writeq(pcie_pmu, HISI_PCIE_EVENT_CTRL, idx, val);
   490	}
   491	
   492	static void hisi_pcie_pmu_disable_counter(struct hisi_pcie_pmu *pcie_pmu,
   493						  struct hw_perf_event *hwc)
   494	{
   495		u32 idx = hwc->idx;
   496		u64 val;
   497	
   498		val = hisi_pcie_pmu_readq(pcie_pmu, HISI_PCIE_EVENT_CTRL, idx);
   499		val &= ~HISI_PCIE_EVENT_EN;
   500		hisi_pcie_pmu_writeq(pcie_pmu, HISI_PCIE_EVENT_CTRL, idx, val);
   501	}
   502	
   503	static void hisi_pcie_pmu_enable_int(struct hisi_pcie_pmu *pcie_pmu,
   504					     struct hw_perf_event *hwc)
   505	{
   506		u32 idx = hwc->idx;
   507	
   508		hisi_pcie_pmu_writel(pcie_pmu, HISI_PCIE_INT_MASK, idx, 0);
   509	}
   510	
   511	static void hisi_pcie_pmu_disable_int(struct hisi_pcie_pmu *pcie_pmu,
   512					      struct hw_perf_event *hwc)
   513	{
   514		u32 idx = hwc->idx;
   515	
   516		hisi_pcie_pmu_writel(pcie_pmu, HISI_PCIE_INT_MASK, idx, 1);
   517	}
   518	
   519	static void hisi_pcie_pmu_reset_counter(struct hisi_pcie_pmu *pcie_pmu,
   520						struct hw_perf_event *hwc)
   521	{
   522		u32 idx = hwc->idx;
   523	
   524		hisi_pcie_pmu_writeq(pcie_pmu, HISI_PCIE_EVENT_CTRL, idx,
   525				     HISI_PCIE_RESET_CNT);
   526		hisi_pcie_pmu_writeq(pcie_pmu, HISI_PCIE_EVENT_CTRL, idx,
   527				     HISI_PCIE_DEFAULT_SET);
   528	}
   529	
 > 530	void hisi_pcie_pmu_start(struct perf_event *event, int flags)
   531	{
   532		struct hisi_pcie_pmu *pcie_pmu = to_pcie_pmu(event->pmu);
   533		struct hw_perf_event *hwc = &event->hw;
   534		struct hw_perf_event_extra *hwc_ext;
   535		u64 prev_cnt, prev_cnt_ext;
   536	
   537		hwc_ext = &hwc->extra_reg;
   538		if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
   539			return;
   540	
   541		WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
   542		hwc->state = 0;
   543	
   544		hisi_pcie_pmu_config_filter(event);
   545		hisi_pcie_pmu_enable_counter(pcie_pmu, hwc);
   546		hisi_pcie_pmu_enable_int(pcie_pmu, hwc);
   547		hisi_pcie_pmu_set_period(event);
   548	
   549		if (flags & PERF_EF_RELOAD) {
   550			prev_cnt = local64_read(&hwc->prev_count);
   551			prev_cnt_ext = hwc_ext->config;
   552			hisi_pcie_pmu_write_counter(event, prev_cnt, prev_cnt_ext);
   553		}
   554	
   555		perf_event_update_userpage(event);
   556	}
   557	
 > 558	void hisi_pcie_pmu_stop(struct perf_event *event, int flags)
   559	{
   560		struct hisi_pcie_pmu *pcie_pmu = to_pcie_pmu(event->pmu);
   561		struct hw_perf_event *hwc = &event->hw;
   562	
   563		hisi_pcie_pmu_read(event);
   564		hisi_pcie_pmu_disable_int(pcie_pmu, hwc);
   565		hisi_pcie_pmu_disable_counter(pcie_pmu, hwc);
   566		hisi_pcie_pmu_clear_filter(event);
   567		WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
   568		hwc->state |= PERF_HES_STOPPED;
   569	
   570		if (hwc->state & PERF_HES_UPTODATE)
   571			return;
   572	
   573	
   574		hwc->state |= PERF_HES_UPTODATE;
   575	}
   576	
 > 577	int hisi_pcie_pmu_add(struct perf_event *event, int flags)
   578	{
   579		struct hisi_pcie_pmu *pcie_pmu = to_pcie_pmu(event->pmu);
   580		struct hw_perf_event *hwc = &event->hw;
   581		int idx;
   582	
   583		hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
   584		idx = hisi_pcie_pmu_get_event_idx(pcie_pmu);
   585		if (idx < 0)
   586			return idx;
   587	
   588		hwc->idx = idx;
   589		pcie_pmu->hw_events[idx] = event;
   590	
   591		/* Reset PMC to avoid interference caused by previous statistic. */
   592		hisi_pcie_pmu_reset_counter(pcie_pmu, hwc);
   593	
   594		if (flags & PERF_EF_START)
   595			hisi_pcie_pmu_start(event, PERF_EF_RELOAD);
   596	
   597		return 0;
   598	}
   599	
 > 600	void hisi_pcie_pmu_del(struct perf_event *event, int flags)
   601	{
   602		struct hisi_pcie_pmu *pcie_pmu = to_pcie_pmu(event->pmu);
   603		struct hw_perf_event *hwc = &event->hw;
   604	
   605		hisi_pcie_pmu_stop(event, PERF_EF_UPDATE);
   606		pcie_pmu->hw_events[hwc->idx] = NULL;
   607		perf_event_update_userpage(event);
   608	}
   609	
 > 610	void hisi_pcie_pmu_enable(struct pmu *pmu)
   611	{
   612		struct hisi_pcie_pmu *pcie_pmu = to_pcie_pmu(pmu);
   613		int num;
   614	
   615		for (num = 0; num < HISI_PCIE_MAX_COUNTERS; num++) {
   616			if (pcie_pmu->hw_events[num])
   617				break;
   618		}
   619	
   620		if (num == HISI_PCIE_MAX_COUNTERS)
   621			return;
   622	
   623		writel(HISI_PCIE_GLOBAL_EN, pcie_pmu->base + HISI_PCIE_GLOBAL_CTRL);
   624	}
   625	
 > 626	void hisi_pcie_pmu_disable(struct pmu *pmu)
   627	{
   628		struct hisi_pcie_pmu *pcie_pmu = to_pcie_pmu(pmu);
   629	
   630		writel(HISI_PCIE_GLOBAL_NONE, pcie_pmu->base + HISI_PCIE_GLOBAL_CTRL);
   631	}
   632	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

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