From: Rob Herring <robh@kernel.org>
To: Claudiu Beznea <claudiu.beznea@microchip.com>
Cc: devicetree@vger.kernel.org, alexandre.belloni@bootlin.com,
linux-kernel@vger.kernel.org, linux@armlinux.org.uk,
ludovic.desroches@microchip.com,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 16/24] dt-bindings: atmel-sysreg: add bindings for sama7g5
Date: Mon, 12 Apr 2021 11:02:16 -0500 [thread overview]
Message-ID: <20210412160216.GA3970458@robh.at.kernel.org> (raw)
In-Reply-To: <20210409111345.294472-17-claudiu.beznea@microchip.com>
On Fri, Apr 09, 2021 at 02:13:37PM +0300, Claudiu Beznea wrote:
> Add RAM controller and RAM PHY controller DT bindings.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
> .../devicetree/bindings/arm/atmel-sysregs.txt | 15 ++++++++++++++-
> 1 file changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
> index 807264a78edc..7cd55a760d41 100644
> --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
> +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
> @@ -45,7 +45,8 @@ RAMC SDRAM/DDR Controller required properties:
> "atmel,at91sam9260-sdramc",
> "atmel,at91sam9g45-ddramc",
> "atmel,sama5d3-ddramc",
> - "microchip,sam9x60-ddramc"
> + "microchip,sam9x60-ddramc",
> + "microchip,sama7g5-uddrc"
> - reg: Should contain registers location and length
>
> Examples:
> @@ -55,6 +56,18 @@ Examples:
> reg = <0xffffe800 0x200>;
> };
>
> +RAMC PHY Controller required properties:
> +- compatible: Should be "microchip,sama7g5-ddr3phy", "syscon"
> +- reg: Should contain registers location and length
> +
> +Example:
> +
> + ddr3phy: ddr3phy@e3804000 {
> + compatible = "microchip,sama7g5-ddr3phy", "syscon";
> + reg = <0xe3804000 0x1000>;
> + status = "okay";
Really need an example for this? If so, drop 'status'.
> +};
> +
> SHDWC Shutdown Controller
>
> required properties:
> --
> 2.25.1
>
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WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Claudiu Beznea <claudiu.beznea@microchip.com>
Cc: nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com,
ludovic.desroches@microchip.com, linux@armlinux.org.uk,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 16/24] dt-bindings: atmel-sysreg: add bindings for sama7g5
Date: Mon, 12 Apr 2021 11:02:16 -0500 [thread overview]
Message-ID: <20210412160216.GA3970458@robh.at.kernel.org> (raw)
In-Reply-To: <20210409111345.294472-17-claudiu.beznea@microchip.com>
On Fri, Apr 09, 2021 at 02:13:37PM +0300, Claudiu Beznea wrote:
> Add RAM controller and RAM PHY controller DT bindings.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
> .../devicetree/bindings/arm/atmel-sysregs.txt | 15 ++++++++++++++-
> 1 file changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
> index 807264a78edc..7cd55a760d41 100644
> --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
> +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
> @@ -45,7 +45,8 @@ RAMC SDRAM/DDR Controller required properties:
> "atmel,at91sam9260-sdramc",
> "atmel,at91sam9g45-ddramc",
> "atmel,sama5d3-ddramc",
> - "microchip,sam9x60-ddramc"
> + "microchip,sam9x60-ddramc",
> + "microchip,sama7g5-uddrc"
> - reg: Should contain registers location and length
>
> Examples:
> @@ -55,6 +56,18 @@ Examples:
> reg = <0xffffe800 0x200>;
> };
>
> +RAMC PHY Controller required properties:
> +- compatible: Should be "microchip,sama7g5-ddr3phy", "syscon"
> +- reg: Should contain registers location and length
> +
> +Example:
> +
> + ddr3phy: ddr3phy@e3804000 {
> + compatible = "microchip,sama7g5-ddr3phy", "syscon";
> + reg = <0xe3804000 0x1000>;
> + status = "okay";
Really need an example for this? If so, drop 'status'.
> +};
> +
> SHDWC Shutdown Controller
>
> required properties:
> --
> 2.25.1
>
next prev parent reply other threads:[~2021-04-12 16:04 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-09 11:13 [PATCH v2 00/24] ARM: at91: pm: add support for sama7g5 Claudiu Beznea
2021-04-09 11:13 ` Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 01/24] ARM: at91: pm: move pm_bu to soc_pm data structure Claudiu Beznea
2021-04-09 11:13 ` Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 02/24] ARM: at91: pm: move the setup of soc_pm.bu->suspended Claudiu Beznea
2021-04-09 11:13 ` Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 03/24] ARM: at91: pm: document at91_soc_pm structure Claudiu Beznea
2021-04-09 11:13 ` Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 04/24] ARM: at91: pm: check for different controllers in at91_pm_modes_init() Claudiu Beznea
2021-04-09 11:13 ` Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 05/24] ARM: at91: pm: do not initialize pdev Claudiu Beznea
2021-04-09 11:13 ` Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 06/24] ARM: at91: pm: use r7 instead of tmp1 Claudiu Beznea
2021-04-09 11:13 ` Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 07/24] ARM: at91: pm: avoid push and pop on stack while memory is in self-refersh Claudiu Beznea
2021-04-09 11:13 ` Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 08/24] ARM: at91: pm: s/CONFIG_SOC_SAM9X60/CONFIG_HAVE_AT91_SAM9X60_PLL/g Claudiu Beznea
2021-04-09 11:13 ` Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 09/24] ARM: at91: pm: add support for waiting MCK1..4 Claudiu Beznea
2021-04-09 11:13 ` Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 10/24] ARM: at91: sfrbu: add sfrbu registers definitions for sama7g5 Claudiu Beznea
2021-04-09 11:13 ` Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 11/24] ARM: at91: ddr: add registers definitions for sama7g5's ddr Claudiu Beznea
2021-04-09 11:13 ` Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 12/24] ARM: at91: pm: add self-refresh support for sama7g5 Claudiu Beznea
2021-04-09 11:13 ` Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 13/24] ARM: at91: pm: add support for MCK1..4 save/restore for ulp modes Claudiu Beznea
2021-04-09 11:13 ` Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 14/24] ARM: at91: pm: add support for 2.5V LDO regulator control Claudiu Beznea
2021-04-09 11:13 ` Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 15/24] ARM: at91: pm: wait for ddr power mode off Claudiu Beznea
2021-04-09 11:13 ` Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 16/24] dt-bindings: atmel-sysreg: add bindings for sama7g5 Claudiu Beznea
2021-04-09 11:13 ` Claudiu Beznea
2021-04-12 16:02 ` Rob Herring [this message]
2021-04-12 16:02 ` Rob Herring
2021-04-15 7:31 ` Claudiu.Beznea
2021-04-15 7:31 ` Claudiu.Beznea
2021-04-09 11:13 ` [PATCH v2 17/24] ARM: at91: pm: add sama7g5 ddr controller Claudiu Beznea
2021-04-09 11:13 ` Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 18/24] ARM: at91: pm: add sama7g5 ddr phy controller Claudiu Beznea
2021-04-09 11:13 ` Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 19/24] ARM: at91: pm: save ddr phy calibration data to securam Claudiu Beznea
2021-04-09 11:13 ` Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 20/24] ARM: at91: pm: add backup mode support for SAMA7G5 Claudiu Beznea
2021-04-09 11:13 ` Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 21/24] ARM: at91: pm: add sama7g5's pmc Claudiu Beznea
2021-04-09 11:13 ` Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 22/24] ARM: at91: sama7: introduce sama7 SoC family Claudiu Beznea
2021-04-09 11:13 ` Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 23/24] ARM: at91: pm: add pm support for SAMA7G5 Claudiu Beznea
2021-04-09 11:13 ` Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 24/24] ARM: at91: pm: add sama7g5 shdwc Claudiu Beznea
2021-04-09 11:13 ` Claudiu Beznea
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