Re: [RFC 4/8] phy: dwc: Add Synopsys DesignWare HDMI RX PHYs e405 and e406 Driver

[kernel test robot <lkp@intel.com>]

[-- Attachment #1: Type: text/plain, Size: 2708 bytes --]

Hi Nelson,

[FYI, it's a private test report for your RFC patch.]
[auto build test WARNING on linuxtv-media/master]
[also build test WARNING on linux/master linus/master v5.12 next-20210428]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Nelson-Costa/Add-Synopsys-DesignWare-HDMI-RX-Controller-and-PHY-drivers/20210428-232828
base:   git://linuxtv.org/media_tree.git master
config: ia64-allmodconfig (attached as .config)
compiler: ia64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/616184ab2857513c2a560411bc86d51aeda69c92
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Nelson-Costa/Add-Synopsys-DesignWare-HDMI-RX-Controller-and-PHY-drivers/20210428-232828
        git checkout 616184ab2857513c2a560411bc86d51aeda69c92
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross W=1 ARCH=ia64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/phy/dwc/phy-dw-hdmi-e406.c:139:6: warning: no previous prototype for 'dw_phy_eq_settings' [-Wmissing-prototypes]
     139 | void dw_phy_eq_settings(struct dw_phy_dev *dw_dev, u16 ch0_setting,
         |      ^~~~~~~~~~~~~~~~~~


vim +/dw_phy_eq_settings +139 drivers/phy/dwc/phy-dw-hdmi-e406.c

   138	
 > 139	void dw_phy_eq_settings(struct dw_phy_dev *dw_dev, u16 ch0_setting,
   140				u16 ch1_setting, u16 ch2_setting)
   141	{
   142		dw_phy_write(dw_dev,
   143			     (DW_CHX_EQ_CTRL3_MASK |
   144			      (ch0_setting & DW_PHY_CH0_EXT_EQ_SET_MASK)),
   145			     DW_PHY_CH0_EQ_CTRL3);
   146		dw_phy_write(dw_dev,
   147			     (DW_CHX_EQ_CTRL3_MASK |
   148			      (ch1_setting & DW_PHY_CH1_EXT_EQ_SET_MASK)),
   149			     DW_PHY_CH1_EQ_CTRL3);
   150		dw_phy_write(dw_dev,
   151			     (DW_CHX_EQ_CTRL3_MASK |
   152			      (ch2_setting & DW_PHY_CH2_EXT_EQ_SET_MASK)),
   153			     DW_PHY_CH2_EQ_CTRL3);
   154		dw_phy_write(dw_dev, DW_PHY_EQ_EN_OVR_EN, DW_PHY_MAINFSM_OVR2);
   155	
   156		dw_phy_eq_auto_calib(dw_dev);
   157	}
   158	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 63947 bytes --]