* drivers/iio/imu/adis16475.c:1201 adis16475_config_sync_mode() warn: '2100 / st->clk_freq' 123456789 can't fit into 65535 'up_scale'
@ 2021-05-08 18:36 kernel test robot
0 siblings, 0 replies; 2+ messages in thread
From: kernel test robot @ 2021-05-08 18:36 UTC (permalink / raw)
To: kbuild
[-- Attachment #1: Type: text/plain, Size: 6926 bytes --]
CC: kbuild-all(a)lists.01.org
CC: linux-kernel(a)vger.kernel.org
TO: Nuno Sa <nuno.sa@analog.com>
CC: Jonathan Cameron <Jonathan.Cameron@huawei.com>
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: ab159ac569fddf812c0a217d6dbffaa5d93ef88f
commit: 39c024b51b5607e9d2fc6c04c2573e4a778c728d iio: adis16475: improve sync scale mode handling
date: 8 weeks ago
:::::: branch date: 3 hours ago
:::::: commit date: 8 weeks ago
config: s390-randconfig-m031-20210509 (attached as .config)
compiler: s390-linux-gcc (GCC) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
smatch warnings:
drivers/iio/imu/adis16475.c:1201 adis16475_config_sync_mode() warn: '2100 / st->clk_freq' 123456789 can't fit into 65535 'up_scale'
vim +1201 drivers/iio/imu/adis16475.c
fff7352bf7a3ce Nuno Sá 2020-04-13 1144
fff7352bf7a3ce Nuno Sá 2020-04-13 1145 static int adis16475_config_sync_mode(struct adis16475 *st)
fff7352bf7a3ce Nuno Sá 2020-04-13 1146 {
fff7352bf7a3ce Nuno Sá 2020-04-13 1147 int ret;
fff7352bf7a3ce Nuno Sá 2020-04-13 1148 struct device *dev = &st->adis.spi->dev;
fff7352bf7a3ce Nuno Sá 2020-04-13 1149 const struct adis16475_sync *sync;
fff7352bf7a3ce Nuno Sá 2020-04-13 1150 u32 sync_mode;
fff7352bf7a3ce Nuno Sá 2020-04-13 1151
fff7352bf7a3ce Nuno Sá 2020-04-13 1152 /* default to internal clk */
fff7352bf7a3ce Nuno Sá 2020-04-13 1153 st->clk_freq = st->info->int_clk * 1000;
fff7352bf7a3ce Nuno Sá 2020-04-13 1154
fff7352bf7a3ce Nuno Sá 2020-04-13 1155 ret = device_property_read_u32(dev, "adi,sync-mode", &sync_mode);
fff7352bf7a3ce Nuno Sá 2020-04-13 1156 if (ret)
fff7352bf7a3ce Nuno Sá 2020-04-13 1157 return 0;
fff7352bf7a3ce Nuno Sá 2020-04-13 1158
fff7352bf7a3ce Nuno Sá 2020-04-13 1159 if (sync_mode >= st->info->num_sync) {
fff7352bf7a3ce Nuno Sá 2020-04-13 1160 dev_err(dev, "Invalid sync mode: %u for %s\n", sync_mode,
fff7352bf7a3ce Nuno Sá 2020-04-13 1161 st->info->name);
fff7352bf7a3ce Nuno Sá 2020-04-13 1162 return -EINVAL;
fff7352bf7a3ce Nuno Sá 2020-04-13 1163 }
fff7352bf7a3ce Nuno Sá 2020-04-13 1164
fff7352bf7a3ce Nuno Sá 2020-04-13 1165 sync = &st->info->sync[sync_mode];
39c024b51b5607 Nuno Sa 2021-02-18 1166 st->sync_mode = sync->sync_mode;
fff7352bf7a3ce Nuno Sá 2020-04-13 1167
fff7352bf7a3ce Nuno Sá 2020-04-13 1168 /* All the other modes require external input signal */
fff7352bf7a3ce Nuno Sá 2020-04-13 1169 if (sync->sync_mode != ADIS16475_SYNC_OUTPUT) {
fff7352bf7a3ce Nuno Sá 2020-04-13 1170 struct clk *clk = devm_clk_get(dev, NULL);
fff7352bf7a3ce Nuno Sá 2020-04-13 1171
fff7352bf7a3ce Nuno Sá 2020-04-13 1172 if (IS_ERR(clk))
fff7352bf7a3ce Nuno Sá 2020-04-13 1173 return PTR_ERR(clk);
fff7352bf7a3ce Nuno Sá 2020-04-13 1174
fff7352bf7a3ce Nuno Sá 2020-04-13 1175 ret = clk_prepare_enable(clk);
fff7352bf7a3ce Nuno Sá 2020-04-13 1176 if (ret)
fff7352bf7a3ce Nuno Sá 2020-04-13 1177 return ret;
fff7352bf7a3ce Nuno Sá 2020-04-13 1178
fff7352bf7a3ce Nuno Sá 2020-04-13 1179 ret = devm_add_action_or_reset(dev, adis16475_disable_clk, clk);
fff7352bf7a3ce Nuno Sá 2020-04-13 1180 if (ret)
fff7352bf7a3ce Nuno Sá 2020-04-13 1181 return ret;
fff7352bf7a3ce Nuno Sá 2020-04-13 1182
fff7352bf7a3ce Nuno Sá 2020-04-13 1183 st->clk_freq = clk_get_rate(clk);
fff7352bf7a3ce Nuno Sá 2020-04-13 1184 if (st->clk_freq < sync->min_rate ||
fff7352bf7a3ce Nuno Sá 2020-04-13 1185 st->clk_freq > sync->max_rate) {
fff7352bf7a3ce Nuno Sá 2020-04-13 1186 dev_err(dev,
fff7352bf7a3ce Nuno Sá 2020-04-13 1187 "Clk rate:%u not in a valid range:[%u %u]\n",
fff7352bf7a3ce Nuno Sá 2020-04-13 1188 st->clk_freq, sync->min_rate, sync->max_rate);
fff7352bf7a3ce Nuno Sá 2020-04-13 1189 return -EINVAL;
fff7352bf7a3ce Nuno Sá 2020-04-13 1190 }
fff7352bf7a3ce Nuno Sá 2020-04-13 1191
fff7352bf7a3ce Nuno Sá 2020-04-13 1192 if (sync->sync_mode == ADIS16475_SYNC_SCALED) {
fff7352bf7a3ce Nuno Sá 2020-04-13 1193 u16 up_scale;
39c024b51b5607 Nuno Sa 2021-02-18 1194
fff7352bf7a3ce Nuno Sá 2020-04-13 1195 /*
39c024b51b5607 Nuno Sa 2021-02-18 1196 * In sync scaled mode, the IMU sample rate is the clk_freq * sync_scale.
39c024b51b5607 Nuno Sa 2021-02-18 1197 * Hence, default the IMU sample rate to the highest multiple of the input
39c024b51b5607 Nuno Sa 2021-02-18 1198 * clock lower than the IMU max sample rate. The optimal range is
39c024b51b5607 Nuno Sa 2021-02-18 1199 * 1900-2100 sps...
fff7352bf7a3ce Nuno Sá 2020-04-13 1200 */
39c024b51b5607 Nuno Sa 2021-02-18 @1201 up_scale = 2100 / st->clk_freq;
fff7352bf7a3ce Nuno Sá 2020-04-13 1202
fff7352bf7a3ce Nuno Sá 2020-04-13 1203 ret = __adis_write_reg_16(&st->adis,
fff7352bf7a3ce Nuno Sá 2020-04-13 1204 ADIS16475_REG_UP_SCALE,
fff7352bf7a3ce Nuno Sá 2020-04-13 1205 up_scale);
fff7352bf7a3ce Nuno Sá 2020-04-13 1206 if (ret)
fff7352bf7a3ce Nuno Sá 2020-04-13 1207 return ret;
fff7352bf7a3ce Nuno Sá 2020-04-13 1208 }
fff7352bf7a3ce Nuno Sá 2020-04-13 1209
fff7352bf7a3ce Nuno Sá 2020-04-13 1210 st->clk_freq *= 1000;
fff7352bf7a3ce Nuno Sá 2020-04-13 1211 }
fff7352bf7a3ce Nuno Sá 2020-04-13 1212 /*
fff7352bf7a3ce Nuno Sá 2020-04-13 1213 * Keep in mind that the mask for the clk modes in adis1650*
fff7352bf7a3ce Nuno Sá 2020-04-13 1214 * chips is different (1100 instead of 11100). However, we
fff7352bf7a3ce Nuno Sá 2020-04-13 1215 * are not configuring BIT(4) in these chips and the default
fff7352bf7a3ce Nuno Sá 2020-04-13 1216 * value is 0, so we are fine in doing the below operations.
fff7352bf7a3ce Nuno Sá 2020-04-13 1217 * I'm keeping this for simplicity and avoiding extra variables
fff7352bf7a3ce Nuno Sá 2020-04-13 1218 * in chip_info.
fff7352bf7a3ce Nuno Sá 2020-04-13 1219 */
fff7352bf7a3ce Nuno Sá 2020-04-13 1220 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL,
fff7352bf7a3ce Nuno Sá 2020-04-13 1221 ADIS16475_SYNC_MODE_MASK, sync->sync_mode);
fff7352bf7a3ce Nuno Sá 2020-04-13 1222 if (ret)
fff7352bf7a3ce Nuno Sá 2020-04-13 1223 return ret;
fff7352bf7a3ce Nuno Sá 2020-04-13 1224
fff7352bf7a3ce Nuno Sá 2020-04-13 1225 usleep_range(250, 260);
fff7352bf7a3ce Nuno Sá 2020-04-13 1226
fff7352bf7a3ce Nuno Sá 2020-04-13 1227 return 0;
fff7352bf7a3ce Nuno Sá 2020-04-13 1228 }
fff7352bf7a3ce Nuno Sá 2020-04-13 1229
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 28761 bytes --]
^ permalink raw reply [flat|nested] 2+ messages in thread
* drivers/iio/imu/adis16475.c:1201 adis16475_config_sync_mode() warn: '2100 / st->clk_freq' 123456789 can't fit into 65535 'up_scale'
@ 2021-05-09 1:20 kernel test robot
0 siblings, 0 replies; 2+ messages in thread
From: kernel test robot @ 2021-05-09 1:20 UTC (permalink / raw)
To: kbuild
[-- Attachment #1: Type: text/plain, Size: 6926 bytes --]
CC: kbuild-all(a)lists.01.org
CC: linux-kernel(a)vger.kernel.org
TO: Nuno Sa <nuno.sa@analog.com>
CC: Jonathan Cameron <Jonathan.Cameron@huawei.com>
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: b741596468b010af2846b75f5e75a842ce344a6e
commit: 39c024b51b5607e9d2fc6c04c2573e4a778c728d iio: adis16475: improve sync scale mode handling
date: 8 weeks ago
:::::: branch date: 6 hours ago
:::::: commit date: 8 weeks ago
config: s390-randconfig-m031-20210509 (attached as .config)
compiler: s390-linux-gcc (GCC) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
smatch warnings:
drivers/iio/imu/adis16475.c:1201 adis16475_config_sync_mode() warn: '2100 / st->clk_freq' 123456789 can't fit into 65535 'up_scale'
vim +1201 drivers/iio/imu/adis16475.c
fff7352bf7a3ce Nuno Sá 2020-04-13 1144
fff7352bf7a3ce Nuno Sá 2020-04-13 1145 static int adis16475_config_sync_mode(struct adis16475 *st)
fff7352bf7a3ce Nuno Sá 2020-04-13 1146 {
fff7352bf7a3ce Nuno Sá 2020-04-13 1147 int ret;
fff7352bf7a3ce Nuno Sá 2020-04-13 1148 struct device *dev = &st->adis.spi->dev;
fff7352bf7a3ce Nuno Sá 2020-04-13 1149 const struct adis16475_sync *sync;
fff7352bf7a3ce Nuno Sá 2020-04-13 1150 u32 sync_mode;
fff7352bf7a3ce Nuno Sá 2020-04-13 1151
fff7352bf7a3ce Nuno Sá 2020-04-13 1152 /* default to internal clk */
fff7352bf7a3ce Nuno Sá 2020-04-13 1153 st->clk_freq = st->info->int_clk * 1000;
fff7352bf7a3ce Nuno Sá 2020-04-13 1154
fff7352bf7a3ce Nuno Sá 2020-04-13 1155 ret = device_property_read_u32(dev, "adi,sync-mode", &sync_mode);
fff7352bf7a3ce Nuno Sá 2020-04-13 1156 if (ret)
fff7352bf7a3ce Nuno Sá 2020-04-13 1157 return 0;
fff7352bf7a3ce Nuno Sá 2020-04-13 1158
fff7352bf7a3ce Nuno Sá 2020-04-13 1159 if (sync_mode >= st->info->num_sync) {
fff7352bf7a3ce Nuno Sá 2020-04-13 1160 dev_err(dev, "Invalid sync mode: %u for %s\n", sync_mode,
fff7352bf7a3ce Nuno Sá 2020-04-13 1161 st->info->name);
fff7352bf7a3ce Nuno Sá 2020-04-13 1162 return -EINVAL;
fff7352bf7a3ce Nuno Sá 2020-04-13 1163 }
fff7352bf7a3ce Nuno Sá 2020-04-13 1164
fff7352bf7a3ce Nuno Sá 2020-04-13 1165 sync = &st->info->sync[sync_mode];
39c024b51b5607 Nuno Sa 2021-02-18 1166 st->sync_mode = sync->sync_mode;
fff7352bf7a3ce Nuno Sá 2020-04-13 1167
fff7352bf7a3ce Nuno Sá 2020-04-13 1168 /* All the other modes require external input signal */
fff7352bf7a3ce Nuno Sá 2020-04-13 1169 if (sync->sync_mode != ADIS16475_SYNC_OUTPUT) {
fff7352bf7a3ce Nuno Sá 2020-04-13 1170 struct clk *clk = devm_clk_get(dev, NULL);
fff7352bf7a3ce Nuno Sá 2020-04-13 1171
fff7352bf7a3ce Nuno Sá 2020-04-13 1172 if (IS_ERR(clk))
fff7352bf7a3ce Nuno Sá 2020-04-13 1173 return PTR_ERR(clk);
fff7352bf7a3ce Nuno Sá 2020-04-13 1174
fff7352bf7a3ce Nuno Sá 2020-04-13 1175 ret = clk_prepare_enable(clk);
fff7352bf7a3ce Nuno Sá 2020-04-13 1176 if (ret)
fff7352bf7a3ce Nuno Sá 2020-04-13 1177 return ret;
fff7352bf7a3ce Nuno Sá 2020-04-13 1178
fff7352bf7a3ce Nuno Sá 2020-04-13 1179 ret = devm_add_action_or_reset(dev, adis16475_disable_clk, clk);
fff7352bf7a3ce Nuno Sá 2020-04-13 1180 if (ret)
fff7352bf7a3ce Nuno Sá 2020-04-13 1181 return ret;
fff7352bf7a3ce Nuno Sá 2020-04-13 1182
fff7352bf7a3ce Nuno Sá 2020-04-13 1183 st->clk_freq = clk_get_rate(clk);
fff7352bf7a3ce Nuno Sá 2020-04-13 1184 if (st->clk_freq < sync->min_rate ||
fff7352bf7a3ce Nuno Sá 2020-04-13 1185 st->clk_freq > sync->max_rate) {
fff7352bf7a3ce Nuno Sá 2020-04-13 1186 dev_err(dev,
fff7352bf7a3ce Nuno Sá 2020-04-13 1187 "Clk rate:%u not in a valid range:[%u %u]\n",
fff7352bf7a3ce Nuno Sá 2020-04-13 1188 st->clk_freq, sync->min_rate, sync->max_rate);
fff7352bf7a3ce Nuno Sá 2020-04-13 1189 return -EINVAL;
fff7352bf7a3ce Nuno Sá 2020-04-13 1190 }
fff7352bf7a3ce Nuno Sá 2020-04-13 1191
fff7352bf7a3ce Nuno Sá 2020-04-13 1192 if (sync->sync_mode == ADIS16475_SYNC_SCALED) {
fff7352bf7a3ce Nuno Sá 2020-04-13 1193 u16 up_scale;
39c024b51b5607 Nuno Sa 2021-02-18 1194
fff7352bf7a3ce Nuno Sá 2020-04-13 1195 /*
39c024b51b5607 Nuno Sa 2021-02-18 1196 * In sync scaled mode, the IMU sample rate is the clk_freq * sync_scale.
39c024b51b5607 Nuno Sa 2021-02-18 1197 * Hence, default the IMU sample rate to the highest multiple of the input
39c024b51b5607 Nuno Sa 2021-02-18 1198 * clock lower than the IMU max sample rate. The optimal range is
39c024b51b5607 Nuno Sa 2021-02-18 1199 * 1900-2100 sps...
fff7352bf7a3ce Nuno Sá 2020-04-13 1200 */
39c024b51b5607 Nuno Sa 2021-02-18 @1201 up_scale = 2100 / st->clk_freq;
fff7352bf7a3ce Nuno Sá 2020-04-13 1202
fff7352bf7a3ce Nuno Sá 2020-04-13 1203 ret = __adis_write_reg_16(&st->adis,
fff7352bf7a3ce Nuno Sá 2020-04-13 1204 ADIS16475_REG_UP_SCALE,
fff7352bf7a3ce Nuno Sá 2020-04-13 1205 up_scale);
fff7352bf7a3ce Nuno Sá 2020-04-13 1206 if (ret)
fff7352bf7a3ce Nuno Sá 2020-04-13 1207 return ret;
fff7352bf7a3ce Nuno Sá 2020-04-13 1208 }
fff7352bf7a3ce Nuno Sá 2020-04-13 1209
fff7352bf7a3ce Nuno Sá 2020-04-13 1210 st->clk_freq *= 1000;
fff7352bf7a3ce Nuno Sá 2020-04-13 1211 }
fff7352bf7a3ce Nuno Sá 2020-04-13 1212 /*
fff7352bf7a3ce Nuno Sá 2020-04-13 1213 * Keep in mind that the mask for the clk modes in adis1650*
fff7352bf7a3ce Nuno Sá 2020-04-13 1214 * chips is different (1100 instead of 11100). However, we
fff7352bf7a3ce Nuno Sá 2020-04-13 1215 * are not configuring BIT(4) in these chips and the default
fff7352bf7a3ce Nuno Sá 2020-04-13 1216 * value is 0, so we are fine in doing the below operations.
fff7352bf7a3ce Nuno Sá 2020-04-13 1217 * I'm keeping this for simplicity and avoiding extra variables
fff7352bf7a3ce Nuno Sá 2020-04-13 1218 * in chip_info.
fff7352bf7a3ce Nuno Sá 2020-04-13 1219 */
fff7352bf7a3ce Nuno Sá 2020-04-13 1220 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL,
fff7352bf7a3ce Nuno Sá 2020-04-13 1221 ADIS16475_SYNC_MODE_MASK, sync->sync_mode);
fff7352bf7a3ce Nuno Sá 2020-04-13 1222 if (ret)
fff7352bf7a3ce Nuno Sá 2020-04-13 1223 return ret;
fff7352bf7a3ce Nuno Sá 2020-04-13 1224
fff7352bf7a3ce Nuno Sá 2020-04-13 1225 usleep_range(250, 260);
fff7352bf7a3ce Nuno Sá 2020-04-13 1226
fff7352bf7a3ce Nuno Sá 2020-04-13 1227 return 0;
fff7352bf7a3ce Nuno Sá 2020-04-13 1228 }
fff7352bf7a3ce Nuno Sá 2020-04-13 1229
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 28761 bytes --]
^ permalink raw reply [flat|nested] 2+ messages in thread
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2021-05-09 1:20 drivers/iio/imu/adis16475.c:1201 adis16475_config_sync_mode() warn: '2100 / st->clk_freq' 123456789 can't fit into 65535 'up_scale' kernel test robot
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