From: Dan Carpenter <dan.carpenter@oracle.com>
To: kvm-riscv@lists.infradead.org
Subject: [PATCH v18 14/18] RISC-V: KVM: Implement ONE REG interface for FP registers
Date: Wed, 19 May 2021 13:11:49 +0300 [thread overview]
Message-ID: <20210519101149.GS1955@kadam> (raw)
In-Reply-To: <20210519033553.1110536-15-anup.patel@wdc.com>
On Wed, May 19, 2021 at 09:05:49AM +0530, Anup Patel wrote:
> static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu,
> const struct kvm_one_reg *reg)
> {
> @@ -427,6 +519,12 @@ static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu,
> return kvm_riscv_vcpu_set_reg_csr(vcpu, reg);
> else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER)
> return kvm_riscv_vcpu_set_reg_timer(vcpu, reg);
> + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F)
> + return kvm_riscv_vcpu_set_reg_fp(vcpu, reg,
> + KVM_REG_RISCV_FP_F);
> + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D)
> + return kvm_riscv_vcpu_set_reg_fp(vcpu, reg,
> + KVM_REG_RISCV_FP_D);
>
> return -EINVAL;
> }
> @@ -442,6 +540,12 @@ static int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcpu,
> return kvm_riscv_vcpu_get_reg_csr(vcpu, reg);
> else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER)
> return kvm_riscv_vcpu_get_reg_timer(vcpu, reg);
> + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F)
> + return kvm_riscv_vcpu_get_reg_fp(vcpu, reg,
> + KVM_REG_RISCV_FP_F);
> + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D)
> + return kvm_riscv_vcpu_get_reg_fp(vcpu, reg,
> + KVM_REG_RISCV_FP_D);
These have become unwieldy. Use a switch statement:
switch (reg->id & KVM_REG_RISCV_TYPE_MASK) {
case KVM_REG_RISCV_TIMER:
return kvm_riscv_vcpu_get_reg_timer(vcpu, reg);
regards,
dan carpenter
WARNING: multiple messages have this Message-ID (diff)
From: Dan Carpenter <dan.carpenter@oracle.com>
To: Anup Patel <anup.patel@wdc.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Palmer Dabbelt <palmerdabbelt@google.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Paolo Bonzini <pbonzini@redhat.com>,
Jonathan Corbet <corbet@lwn.net>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Alexander Graf <graf@amazon.com>,
Atish Patra <atish.patra@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Damien Le Moal <damien.lemoal@wdc.com>,
Anup Patel <anup@brainfault.org>,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-riscv@lists.infradead.org, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev
Subject: Re: [PATCH v18 14/18] RISC-V: KVM: Implement ONE REG interface for FP registers
Date: Wed, 19 May 2021 13:11:49 +0300 [thread overview]
Message-ID: <20210519101149.GS1955@kadam> (raw)
In-Reply-To: <20210519033553.1110536-15-anup.patel@wdc.com>
On Wed, May 19, 2021 at 09:05:49AM +0530, Anup Patel wrote:
> static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu,
> const struct kvm_one_reg *reg)
> {
> @@ -427,6 +519,12 @@ static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu,
> return kvm_riscv_vcpu_set_reg_csr(vcpu, reg);
> else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER)
> return kvm_riscv_vcpu_set_reg_timer(vcpu, reg);
> + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F)
> + return kvm_riscv_vcpu_set_reg_fp(vcpu, reg,
> + KVM_REG_RISCV_FP_F);
> + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D)
> + return kvm_riscv_vcpu_set_reg_fp(vcpu, reg,
> + KVM_REG_RISCV_FP_D);
>
> return -EINVAL;
> }
> @@ -442,6 +540,12 @@ static int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcpu,
> return kvm_riscv_vcpu_get_reg_csr(vcpu, reg);
> else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER)
> return kvm_riscv_vcpu_get_reg_timer(vcpu, reg);
> + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F)
> + return kvm_riscv_vcpu_get_reg_fp(vcpu, reg,
> + KVM_REG_RISCV_FP_F);
> + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D)
> + return kvm_riscv_vcpu_get_reg_fp(vcpu, reg,
> + KVM_REG_RISCV_FP_D);
These have become unwieldy. Use a switch statement:
switch (reg->id & KVM_REG_RISCV_TYPE_MASK) {
case KVM_REG_RISCV_TIMER:
return kvm_riscv_vcpu_get_reg_timer(vcpu, reg);
regards,
dan carpenter
WARNING: multiple messages have this Message-ID (diff)
From: Dan Carpenter <dan.carpenter@oracle.com>
To: Anup Patel <anup.patel@wdc.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Palmer Dabbelt <palmerdabbelt@google.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Paolo Bonzini <pbonzini@redhat.com>,
Jonathan Corbet <corbet@lwn.net>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Alexander Graf <graf@amazon.com>,
Atish Patra <atish.patra@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Damien Le Moal <damien.lemoal@wdc.com>,
Anup Patel <anup@brainfault.org>,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-riscv@lists.infradead.org, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev
Subject: Re: [PATCH v18 14/18] RISC-V: KVM: Implement ONE REG interface for FP registers
Date: Wed, 19 May 2021 13:11:49 +0300 [thread overview]
Message-ID: <20210519101149.GS1955@kadam> (raw)
In-Reply-To: <20210519033553.1110536-15-anup.patel@wdc.com>
On Wed, May 19, 2021 at 09:05:49AM +0530, Anup Patel wrote:
> static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu,
> const struct kvm_one_reg *reg)
> {
> @@ -427,6 +519,12 @@ static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu,
> return kvm_riscv_vcpu_set_reg_csr(vcpu, reg);
> else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER)
> return kvm_riscv_vcpu_set_reg_timer(vcpu, reg);
> + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F)
> + return kvm_riscv_vcpu_set_reg_fp(vcpu, reg,
> + KVM_REG_RISCV_FP_F);
> + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D)
> + return kvm_riscv_vcpu_set_reg_fp(vcpu, reg,
> + KVM_REG_RISCV_FP_D);
>
> return -EINVAL;
> }
> @@ -442,6 +540,12 @@ static int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcpu,
> return kvm_riscv_vcpu_get_reg_csr(vcpu, reg);
> else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER)
> return kvm_riscv_vcpu_get_reg_timer(vcpu, reg);
> + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F)
> + return kvm_riscv_vcpu_get_reg_fp(vcpu, reg,
> + KVM_REG_RISCV_FP_F);
> + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D)
> + return kvm_riscv_vcpu_get_reg_fp(vcpu, reg,
> + KVM_REG_RISCV_FP_D);
These have become unwieldy. Use a switch statement:
switch (reg->id & KVM_REG_RISCV_TYPE_MASK) {
case KVM_REG_RISCV_TIMER:
return kvm_riscv_vcpu_get_reg_timer(vcpu, reg);
regards,
dan carpenter
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next prev parent reply other threads:[~2021-05-19 10:11 UTC|newest]
Thread overview: 141+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-19 3:35 [PATCH v18 00/18] KVM RISC-V Support Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 3:35 ` [PATCH v18 01/18] RISC-V: Add hypervisor extension related CSR defines Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 3:35 ` [PATCH v18 02/18] RISC-V: Add initial skeletal KVM support Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 9:24 ` Dan Carpenter
2021-05-19 9:24 ` Dan Carpenter
2021-05-19 9:24 ` Dan Carpenter
2021-05-19 10:17 ` Dan Carpenter
2021-05-19 10:17 ` Dan Carpenter
2021-05-19 10:17 ` Dan Carpenter
2021-05-19 3:35 ` [PATCH v18 03/18] RISC-V: KVM: Implement VCPU create, init and destroy functions Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 3:35 ` [PATCH v18 04/18] RISC-V: KVM: Implement VCPU interrupts and requests handling Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 3:35 ` [PATCH v18 05/18] RISC-V: KVM: Implement KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 3:35 ` [PATCH v18 06/18] RISC-V: KVM: Implement VCPU world-switch Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 3:35 ` [PATCH v18 07/18] RISC-V: KVM: Handle MMIO exits for VCPU Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 3:35 ` [PATCH v18 08/18] RISC-V: KVM: Handle WFI " Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 3:35 ` [PATCH v18 09/18] RISC-V: KVM: Implement VMID allocator Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 3:35 ` [PATCH v18 10/18] RISC-V: KVM: Implement stage2 page table programming Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 3:35 ` [PATCH v18 11/18] RISC-V: KVM: Implement MMU notifiers Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 10:09 ` Dan Carpenter
2021-05-19 10:09 ` Dan Carpenter
2021-05-19 10:09 ` Dan Carpenter
2021-05-19 3:35 ` [PATCH v18 12/18] RISC-V: KVM: Add timer functionality Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 3:35 ` [PATCH v18 13/18] RISC-V: KVM: FP lazy save/restore Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 3:35 ` [PATCH v18 14/18] RISC-V: KVM: Implement ONE REG interface for FP registers Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 10:11 ` Dan Carpenter [this message]
2021-05-19 10:11 ` Dan Carpenter
2021-05-19 10:11 ` Dan Carpenter
2021-05-20 6:09 ` Dan Carpenter
2021-05-20 6:09 ` Dan Carpenter
2021-05-20 6:09 ` Dan Carpenter
2021-05-19 3:35 ` [PATCH v18 15/18] RISC-V: KVM: Add SBI v0.1 support Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 3:35 ` [PATCH v18 16/18] RISC-V: KVM: Document RISC-V specific parts of KVM API Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 3:35 ` [PATCH v18 17/18] RISC-V: KVM: Move sources to drivers/staging directory Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 3:35 ` [PATCH v18 18/18] RISC-V: KVM: Add MAINTAINERS entry Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 3:35 ` Anup Patel
2021-05-19 4:58 ` [PATCH v18 00/18] KVM RISC-V Support Greg Kroah-Hartman
2021-05-19 4:58 ` Greg Kroah-Hartman
2021-05-19 4:58 ` Greg Kroah-Hartman
2021-05-19 5:10 ` Anup Patel
2021-05-19 5:10 ` Anup Patel
2021-05-19 5:10 ` Anup Patel
2021-05-19 5:21 ` Greg Kroah-Hartman
2021-05-19 5:21 ` Greg Kroah-Hartman
2021-05-19 5:21 ` Greg Kroah-Hartman
2021-05-19 10:47 ` Greg Kroah-Hartman
2021-05-19 10:47 ` Greg Kroah-Hartman
2021-05-19 10:47 ` Greg Kroah-Hartman
2021-05-19 11:18 ` Paolo Bonzini
2021-05-19 11:18 ` Paolo Bonzini
2021-05-19 11:18 ` Paolo Bonzini
2021-05-19 12:23 ` Greg Kroah-Hartman
2021-05-19 12:23 ` Greg Kroah-Hartman
2021-05-19 12:23 ` Greg Kroah-Hartman
2021-05-19 13:29 ` Paolo Bonzini
2021-05-19 13:29 ` Paolo Bonzini
2021-05-19 13:29 ` Paolo Bonzini
2021-05-19 13:58 ` Greg Kroah-Hartman
2021-05-19 13:58 ` Greg Kroah-Hartman
2021-05-19 13:58 ` Greg Kroah-Hartman
2021-05-19 15:08 ` Dan Carpenter
2021-05-19 15:08 ` Dan Carpenter
2021-05-19 15:08 ` Dan Carpenter
2021-05-19 15:26 ` Paolo Bonzini
2021-05-19 15:26 ` Paolo Bonzini
2021-05-19 15:26 ` Paolo Bonzini
2021-05-21 17:13 ` Palmer Dabbelt
2021-05-21 17:13 ` Palmer Dabbelt
2021-05-21 17:13 ` Palmer Dabbelt
2021-05-21 17:21 ` Paolo Bonzini
2021-05-21 17:21 ` Paolo Bonzini
2021-05-21 17:21 ` Paolo Bonzini
2021-05-21 17:47 ` Greg KH
2021-05-21 17:47 ` Greg KH
2021-05-21 17:47 ` Greg KH
2021-05-21 18:08 ` Palmer Dabbelt
2021-05-21 18:08 ` Palmer Dabbelt
2021-05-21 18:08 ` Palmer Dabbelt
2021-05-21 18:25 ` Greg KH
2021-05-21 18:25 ` Greg KH
2021-05-21 18:25 ` Greg KH
2021-05-21 20:25 ` Paolo Bonzini
2021-05-21 20:25 ` Paolo Bonzini
2021-05-21 20:25 ` Paolo Bonzini
2021-05-24 7:09 ` Guo Ren
2021-05-24 7:09 ` Guo Ren
2021-05-24 7:09 ` Guo Ren
2021-05-24 22:57 ` Palmer Dabbelt
2021-05-24 22:57 ` Palmer Dabbelt
2021-05-24 22:57 ` Palmer Dabbelt
2021-05-24 23:08 ` Damien Le Moal
2021-05-24 23:08 ` Damien Le Moal
2021-05-24 23:08 ` Damien Le Moal
2021-05-25 7:37 ` Greg KH
2021-05-25 7:37 ` Greg KH
2021-05-25 7:37 ` Greg KH
2021-05-25 8:01 ` Damien Le Moal
2021-05-25 8:01 ` Damien Le Moal
2021-05-25 8:01 ` Damien Le Moal
2021-05-25 8:11 ` Greg KH
2021-05-25 8:11 ` Greg KH
2021-05-25 8:11 ` Greg KH
2021-05-25 8:24 ` Paolo Bonzini
2021-05-25 8:24 ` Paolo Bonzini
2021-05-25 8:24 ` Paolo Bonzini
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