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From: Matthew Brost <matthew.brost@intel.com>
To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org>
Cc: daniel.vetter@intel.com
Subject: [Intel-gfx] [PATCH 10/20] drm/i915/guc: Don't repeat CTB layout calculations
Date: Wed,  2 Jun 2021 22:16:20 -0700	[thread overview]
Message-ID: <20210603051630.2635-11-matthew.brost@intel.com> (raw)
In-Reply-To: <20210603051630.2635-1-matthew.brost@intel.com>

From: Michal Wajdeczko <michal.wajdeczko@intel.com>

We can retrieve offsets to cmds buffers and descriptor from
actual pointers that we already keep locally.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 079e1a160894..34c582105860 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -244,6 +244,7 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
 {
 	struct intel_guc *guc = ct_to_guc(ct);
 	u32 base, cmds;
+	void *blob;
 	int err;
 	int i;
 
@@ -251,15 +252,18 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
 
 	/* vma should be already allocated and map'ed */
 	GEM_BUG_ON(!ct->vma);
+	GEM_BUG_ON(!i915_gem_object_has_pinned_pages(ct->vma->obj));
 	base = intel_guc_ggtt_offset(guc, ct->vma);
 
-	/* (re)initialize descriptors
-	 * cmds buffers are in the second half of the blob page
-	 */
+	/* blob should start with send descriptor */
+	blob = __px_vaddr(ct->vma->obj);
+	GEM_BUG_ON(blob != ct->ctbs[CTB_SEND].desc);
+
+	/* (re)initialize descriptors */
 	for (i = 0; i < ARRAY_SIZE(ct->ctbs); i++) {
 		GEM_BUG_ON((i != CTB_SEND) && (i != CTB_RECV));
 
-		cmds = base + PAGE_SIZE / 4 * i + PAGE_SIZE / 2;
+		cmds = base + ptrdiff(ct->ctbs[i].cmds, blob);
 		CT_DEBUG(ct, "%d: cmds addr=%#x\n", i, cmds);
 
 		guc_ct_buffer_reset(&ct->ctbs[i], cmds);
@@ -269,12 +273,12 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
 	 * Register both CT buffers starting with RECV buffer.
 	 * Descriptors are in first half of the blob.
 	 */
-	err = ct_register_buffer(ct, base + PAGE_SIZE / 4 * CTB_RECV,
+	err = ct_register_buffer(ct, base + ptrdiff(ct->ctbs[CTB_RECV].desc, blob),
 				 INTEL_GUC_CT_BUFFER_TYPE_RECV);
 	if (unlikely(err))
 		goto err_out;
 
-	err = ct_register_buffer(ct, base + PAGE_SIZE / 4 * CTB_SEND,
+	err = ct_register_buffer(ct, base + ptrdiff(ct->ctbs[CTB_SEND].desc, blob),
 				 INTEL_GUC_CT_BUFFER_TYPE_SEND);
 	if (unlikely(err))
 		goto err_deregister;
-- 
2.28.0

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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

WARNING: multiple messages have this Message-ID (diff)
From: Matthew Brost <matthew.brost@intel.com>
To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org>
Cc: daniel.vetter@intel.com
Subject: [PATCH 10/20] drm/i915/guc: Don't repeat CTB layout calculations
Date: Wed,  2 Jun 2021 22:16:20 -0700	[thread overview]
Message-ID: <20210603051630.2635-11-matthew.brost@intel.com> (raw)
In-Reply-To: <20210603051630.2635-1-matthew.brost@intel.com>

From: Michal Wajdeczko <michal.wajdeczko@intel.com>

We can retrieve offsets to cmds buffers and descriptor from
actual pointers that we already keep locally.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 079e1a160894..34c582105860 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -244,6 +244,7 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
 {
 	struct intel_guc *guc = ct_to_guc(ct);
 	u32 base, cmds;
+	void *blob;
 	int err;
 	int i;
 
@@ -251,15 +252,18 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
 
 	/* vma should be already allocated and map'ed */
 	GEM_BUG_ON(!ct->vma);
+	GEM_BUG_ON(!i915_gem_object_has_pinned_pages(ct->vma->obj));
 	base = intel_guc_ggtt_offset(guc, ct->vma);
 
-	/* (re)initialize descriptors
-	 * cmds buffers are in the second half of the blob page
-	 */
+	/* blob should start with send descriptor */
+	blob = __px_vaddr(ct->vma->obj);
+	GEM_BUG_ON(blob != ct->ctbs[CTB_SEND].desc);
+
+	/* (re)initialize descriptors */
 	for (i = 0; i < ARRAY_SIZE(ct->ctbs); i++) {
 		GEM_BUG_ON((i != CTB_SEND) && (i != CTB_RECV));
 
-		cmds = base + PAGE_SIZE / 4 * i + PAGE_SIZE / 2;
+		cmds = base + ptrdiff(ct->ctbs[i].cmds, blob);
 		CT_DEBUG(ct, "%d: cmds addr=%#x\n", i, cmds);
 
 		guc_ct_buffer_reset(&ct->ctbs[i], cmds);
@@ -269,12 +273,12 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
 	 * Register both CT buffers starting with RECV buffer.
 	 * Descriptors are in first half of the blob.
 	 */
-	err = ct_register_buffer(ct, base + PAGE_SIZE / 4 * CTB_RECV,
+	err = ct_register_buffer(ct, base + ptrdiff(ct->ctbs[CTB_RECV].desc, blob),
 				 INTEL_GUC_CT_BUFFER_TYPE_RECV);
 	if (unlikely(err))
 		goto err_out;
 
-	err = ct_register_buffer(ct, base + PAGE_SIZE / 4 * CTB_SEND,
+	err = ct_register_buffer(ct, base + ptrdiff(ct->ctbs[CTB_SEND].desc, blob),
 				 INTEL_GUC_CT_BUFFER_TYPE_SEND);
 	if (unlikely(err))
 		goto err_deregister;
-- 
2.28.0


  parent reply	other threads:[~2021-06-03  4:59 UTC|newest]

Thread overview: 88+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-03  5:16 [Intel-gfx] [PATCH 00/20] GuC CTBs changes + a few misc patches Matthew Brost
2021-06-03  5:16 ` Matthew Brost
2021-06-03  5:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2021-06-03  5:11 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-06-03  5:16 ` [Intel-gfx] [PATCH 01/20] drm/i915/guc: skip disabling CTBs before sanitizing the GuC Matthew Brost
2021-06-03  5:16   ` Matthew Brost
2021-06-03  5:16 ` [Intel-gfx] [PATCH 02/20] drm/i915/guc: use probe_error log for CT enablement failure Matthew Brost
2021-06-03  5:16   ` Matthew Brost
2021-06-03  5:16 ` [Intel-gfx] [PATCH 03/20] drm/i915/guc: enable only the user interrupt when using GuC submission Matthew Brost
2021-06-03  5:16   ` Matthew Brost
2021-06-03  5:16 ` [Intel-gfx] [PATCH 04/20] drm/i915/guc: Remove sample_forcewake h2g action Matthew Brost
2021-06-03  5:16   ` Matthew Brost
2021-06-03  5:16 ` [Intel-gfx] [PATCH 05/20] drm/i915/guc: Keep strict GuC ABI definitions Matthew Brost
2021-06-03  5:16   ` Matthew Brost
2021-06-03  5:16 ` [Intel-gfx] [PATCH 06/20] drm/i915/guc: Drop guc->interrupts.enabled Matthew Brost
2021-06-03  5:16   ` Matthew Brost
2021-06-03  5:16 ` [Intel-gfx] [PATCH 07/20] drm/i915/guc: Stop using fence/status from CTB descriptor Matthew Brost
2021-06-03  5:16   ` Matthew Brost
2021-06-03  5:16 ` [Intel-gfx] [PATCH 08/20] drm/i915: Promote ptrdiff() to i915_utils.h Matthew Brost
2021-06-03  5:16   ` Matthew Brost
2021-06-03 21:35   ` [Intel-gfx] " Daniel Vetter
2021-06-03 21:35     ` Daniel Vetter
2021-06-04  2:02     ` [Intel-gfx] " Matthew Brost
2021-06-04  2:02       ` Matthew Brost
2021-06-04  8:11       ` [Intel-gfx] " Daniel Vetter
2021-06-04  8:11         ` Daniel Vetter
2021-06-03  5:16 ` [Intel-gfx] [PATCH 09/20] drm/i915/guc: Only rely on own CTB size Matthew Brost
2021-06-03  5:16   ` Matthew Brost
2021-06-03  5:16 ` Matthew Brost [this message]
2021-06-03  5:16   ` [PATCH 10/20] drm/i915/guc: Don't repeat CTB layout calculations Matthew Brost
2021-06-03  5:16 ` [Intel-gfx] [PATCH 11/20] drm/i915/guc: Replace CTB array with explicit members Matthew Brost
2021-06-03  5:16   ` Matthew Brost
2021-06-03  7:25   ` [Intel-gfx] " kernel test robot
2021-06-03  7:25     ` kernel test robot
2021-06-03  7:25     ` kernel test robot
2021-06-03 21:37     ` [Intel-gfx] " Daniel Vetter
2021-06-03 21:37       ` Daniel Vetter
2021-06-03 21:37       ` Daniel Vetter
2021-06-03 22:44       ` [Intel-gfx] [PATCH 1/2] " Matthew Brost
2021-06-03 22:44         ` Matthew Brost
2021-06-03 22:44         ` [Intel-gfx] [PATCH 2/2] drm/i915/guc: Update sizes of CTB buffers Matthew Brost
2021-06-03 22:44           ` Matthew Brost
2021-06-03 23:04       ` [Intel-gfx] [v3 PATCH 1/2] drm/i915/guc: Replace CTB array with explicit members Matthew Brost
2021-06-03 23:04         ` Matthew Brost
2021-06-03 23:04         ` [Intel-gfx] [v3 PATCH 2/2] drm/i915/guc: Update sizes of CTB buffers Matthew Brost
2021-06-03 23:04           ` Matthew Brost
2021-06-04  8:20           ` [Intel-gfx] " Daniel Vetter
2021-06-04  8:20             ` Daniel Vetter
2021-06-04  8:49             ` [Intel-gfx] " Michal Wajdeczko
2021-06-04  8:49               ` Michal Wajdeczko
2021-06-03  5:16 ` [Intel-gfx] [PATCH 12/20] " Matthew Brost
2021-06-03  5:16   ` Matthew Brost
2021-06-03  5:16 ` [Intel-gfx] [PATCH 13/20] drm/i915/guc: Relax CTB response timeout Matthew Brost
2021-06-03  5:16   ` Matthew Brost
2021-06-04  8:33   ` [Intel-gfx] " Daniel Vetter
2021-06-04  8:33     ` Daniel Vetter
2021-06-04 18:35     ` Matthew Brost
2021-06-04 18:35       ` Matthew Brost
2021-06-09 13:24       ` Daniel Vetter
2021-06-09 13:24         ` Daniel Vetter
2021-06-03  5:16 ` [Intel-gfx] [PATCH 14/20] drm/i915/guc: Start protecting access to CTB descriptors Matthew Brost
2021-06-03  5:16   ` Matthew Brost
2021-06-04  8:35   ` [Intel-gfx] " Daniel Vetter
2021-06-04  8:35     ` Daniel Vetter
2021-06-03  5:16 ` [Intel-gfx] [PATCH 15/20] drm/i915/guc: Ensure H2G buffer updates visible before tail update Matthew Brost
2021-06-03  5:16   ` Matthew Brost
2021-06-03  9:44   ` [Intel-gfx] " Michal Wajdeczko
2021-06-03  9:44     ` Michal Wajdeczko
2021-06-03 16:10     ` Matthew Brost
2021-06-03 16:10       ` Matthew Brost
2021-06-04  8:39       ` Daniel Vetter
2021-06-04  8:39         ` Daniel Vetter
2021-06-03  5:16 ` [Intel-gfx] [PATCH 16/20] drm/i915/guc: Stop using mutex while sending CTB messages Matthew Brost
2021-06-03  5:16   ` Matthew Brost
2021-06-03  5:16 ` [Intel-gfx] [PATCH 17/20] drm/i915/guc: Don't receive all G2H messages in irq handler Matthew Brost
2021-06-03  5:16   ` Matthew Brost
2021-06-03  5:16 ` [Intel-gfx] [PATCH 18/20] drm/i915/guc: Always copy CT message to new allocation Matthew Brost
2021-06-03  5:16   ` Matthew Brost
2021-06-03  5:16 ` [Intel-gfx] [PATCH 19/20] drm/i915/guc: Early initialization of GuC send registers Matthew Brost
2021-06-03  5:16   ` Matthew Brost
2021-06-03  5:16 ` [Intel-gfx] [PATCH 20/20] drm/i915/guc: Use guc_class instead of engine_class in fw interface Matthew Brost
2021-06-03  5:16   ` Matthew Brost
2021-06-04  8:44   ` [Intel-gfx] " Daniel Vetter
2021-06-04  8:44     ` Daniel Vetter
2021-06-04 18:12     ` [Intel-gfx] " Matthew Brost
2021-06-04 18:12       ` Matthew Brost
2021-06-03  5:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success for GuC CTBs changes + a few misc patches Patchwork
2021-06-03  6:50 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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