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From: Chris Morgan <macroalpha82@gmail.com>
To: linux-spi@vger.kernel.org
Cc: jon.lin@rock-chips.com, broonie@kernel.org, robh+dt@kernel.org,
	heiko@sntech.de, jbx6244@gmail.com, hjc@rock-chips.com,
	yifeng.zhao@rock-chips.com, sugar.zhang@rock-chips.com,
	linux-rockchip@lists.infradead.org,
	linux-mtd@lists.infradead.org, p.yadav@ti.com,
	Chris Morgan <macromorgan@hotmail.com>
Subject: [RFC v4 5/8] arm: dts: rockchip: Add SFC to RK3036
Date: Fri,  4 Jun 2021 10:10:52 -0500	[thread overview]
Message-ID: <20210604151055.28636-6-macroalpha82@gmail.com> (raw)
In-Reply-To: <20210604151055.28636-1-macroalpha82@gmail.com>

From: Chris Morgan <macromorgan@hotmail.com>

Add a devicetree entry for the Rockchip SFC for the RK3036 SOC.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
 arch/arm/boot/dts/rk3036.dtsi | 42 +++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index e24230d50a78..0dba2956dfb8 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -206,6 +206,17 @@ emac: ethernet@10200000 {
 		status = "disabled";
 	};
 
+	sfc: spi@10208000 {
+		compatible = "rockchip,rk3036-sfc";
+		reg = <0x10208000 0x4000>;
+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_SFC>, <&cru SCLK_SFC>;
+		clock-names = "ahb", "sfc";
+		pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
+		pinctrl-names = "default";
+		status = "disabled";
+	};
+
 	sdmmc: mmc@10214000 {
 		compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 		reg = <0x10214000 0x4000>;
@@ -684,6 +695,37 @@ flash_wrn: flash-wrn {
 			};
 		};
 
+		serial_flash {
+			sfc_bus4: sfc-bus4 {
+				rockchip,pins =
+					<1 RK_PD0 3 &pcfg_pull_none>,
+					<1 RK_PD1 3 &pcfg_pull_none>,
+					<1 RK_PD2 3 &pcfg_pull_none>,
+					<1 RK_PD3 3 &pcfg_pull_none>;
+			};
+
+			sfc_bus2: sfc-bus2 {
+				rockchip,pins =
+					<1 RK_PD0 3 &pcfg_pull_none>,
+					<1 RK_PD1 3 &pcfg_pull_none>;
+			};
+
+			sfc_cs0: sfc-cs0 {
+				rockchip,pins =
+					<2 RK_PA2 3 &pcfg_pull_none>;
+			};
+
+			sfc_cs1: sfc-cs1 {
+				rockchip,pins =
+					<2 RK_PA3 3 &pcfg_pull_none>;
+			};
+
+			sfc_clk: sfc-clk {
+				rockchip,pins =
+					<2 RK_PA4 3 &pcfg_pull_none>;
+			};
+		};
+
 		emac {
 			emac_xfer: emac-xfer {
 				rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */
-- 
2.25.1


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

WARNING: multiple messages have this Message-ID (diff)
From: Chris Morgan <macroalpha82@gmail.com>
To: linux-spi@vger.kernel.org
Cc: jon.lin@rock-chips.com, broonie@kernel.org, robh+dt@kernel.org,
	heiko@sntech.de, jbx6244@gmail.com, hjc@rock-chips.com,
	yifeng.zhao@rock-chips.com, sugar.zhang@rock-chips.com,
	linux-rockchip@lists.infradead.org,
	linux-mtd@lists.infradead.org, p.yadav@ti.com,
	Chris Morgan <macromorgan@hotmail.com>
Subject: [RFC v4 5/8] arm: dts: rockchip: Add SFC to RK3036
Date: Fri,  4 Jun 2021 10:10:52 -0500	[thread overview]
Message-ID: <20210604151055.28636-6-macroalpha82@gmail.com> (raw)
In-Reply-To: <20210604151055.28636-1-macroalpha82@gmail.com>

From: Chris Morgan <macromorgan@hotmail.com>

Add a devicetree entry for the Rockchip SFC for the RK3036 SOC.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
 arch/arm/boot/dts/rk3036.dtsi | 42 +++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index e24230d50a78..0dba2956dfb8 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -206,6 +206,17 @@ emac: ethernet@10200000 {
 		status = "disabled";
 	};
 
+	sfc: spi@10208000 {
+		compatible = "rockchip,rk3036-sfc";
+		reg = <0x10208000 0x4000>;
+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_SFC>, <&cru SCLK_SFC>;
+		clock-names = "ahb", "sfc";
+		pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
+		pinctrl-names = "default";
+		status = "disabled";
+	};
+
 	sdmmc: mmc@10214000 {
 		compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 		reg = <0x10214000 0x4000>;
@@ -684,6 +695,37 @@ flash_wrn: flash-wrn {
 			};
 		};
 
+		serial_flash {
+			sfc_bus4: sfc-bus4 {
+				rockchip,pins =
+					<1 RK_PD0 3 &pcfg_pull_none>,
+					<1 RK_PD1 3 &pcfg_pull_none>,
+					<1 RK_PD2 3 &pcfg_pull_none>,
+					<1 RK_PD3 3 &pcfg_pull_none>;
+			};
+
+			sfc_bus2: sfc-bus2 {
+				rockchip,pins =
+					<1 RK_PD0 3 &pcfg_pull_none>,
+					<1 RK_PD1 3 &pcfg_pull_none>;
+			};
+
+			sfc_cs0: sfc-cs0 {
+				rockchip,pins =
+					<2 RK_PA2 3 &pcfg_pull_none>;
+			};
+
+			sfc_cs1: sfc-cs1 {
+				rockchip,pins =
+					<2 RK_PA3 3 &pcfg_pull_none>;
+			};
+
+			sfc_clk: sfc-clk {
+				rockchip,pins =
+					<2 RK_PA4 3 &pcfg_pull_none>;
+			};
+		};
+
 		emac {
 			emac_xfer: emac-xfer {
 				rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */
-- 
2.25.1


_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

WARNING: multiple messages have this Message-ID (diff)
From: Chris Morgan <macroalpha82@gmail.com>
To: linux-spi@vger.kernel.org
Cc: jon.lin@rock-chips.com, broonie@kernel.org, robh+dt@kernel.org,
	heiko@sntech.de, jbx6244@gmail.com, hjc@rock-chips.com,
	yifeng.zhao@rock-chips.com, sugar.zhang@rock-chips.com,
	linux-rockchip@lists.infradead.org,
	linux-mtd@lists.infradead.org, p.yadav@ti.com,
	Chris Morgan <macromorgan@hotmail.com>
Subject: [RFC v4 5/8] arm: dts: rockchip: Add SFC to RK3036
Date: Fri,  4 Jun 2021 10:10:52 -0500	[thread overview]
Message-ID: <20210604151055.28636-6-macroalpha82@gmail.com> (raw)
In-Reply-To: <20210604151055.28636-1-macroalpha82@gmail.com>

From: Chris Morgan <macromorgan@hotmail.com>

Add a devicetree entry for the Rockchip SFC for the RK3036 SOC.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
 arch/arm/boot/dts/rk3036.dtsi | 42 +++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index e24230d50a78..0dba2956dfb8 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -206,6 +206,17 @@ emac: ethernet@10200000 {
 		status = "disabled";
 	};
 
+	sfc: spi@10208000 {
+		compatible = "rockchip,rk3036-sfc";
+		reg = <0x10208000 0x4000>;
+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_SFC>, <&cru SCLK_SFC>;
+		clock-names = "ahb", "sfc";
+		pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
+		pinctrl-names = "default";
+		status = "disabled";
+	};
+
 	sdmmc: mmc@10214000 {
 		compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 		reg = <0x10214000 0x4000>;
@@ -684,6 +695,37 @@ flash_wrn: flash-wrn {
 			};
 		};
 
+		serial_flash {
+			sfc_bus4: sfc-bus4 {
+				rockchip,pins =
+					<1 RK_PD0 3 &pcfg_pull_none>,
+					<1 RK_PD1 3 &pcfg_pull_none>,
+					<1 RK_PD2 3 &pcfg_pull_none>,
+					<1 RK_PD3 3 &pcfg_pull_none>;
+			};
+
+			sfc_bus2: sfc-bus2 {
+				rockchip,pins =
+					<1 RK_PD0 3 &pcfg_pull_none>,
+					<1 RK_PD1 3 &pcfg_pull_none>;
+			};
+
+			sfc_cs0: sfc-cs0 {
+				rockchip,pins =
+					<2 RK_PA2 3 &pcfg_pull_none>;
+			};
+
+			sfc_cs1: sfc-cs1 {
+				rockchip,pins =
+					<2 RK_PA3 3 &pcfg_pull_none>;
+			};
+
+			sfc_clk: sfc-clk {
+				rockchip,pins =
+					<2 RK_PA4 3 &pcfg_pull_none>;
+			};
+		};
+
 		emac {
 			emac_xfer: emac-xfer {
 				rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */
-- 
2.25.1


  parent reply	other threads:[~2021-06-04 15:15 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-04 15:10 [RFC v4 0/8] Add Rockchip SFC(serial flash controller) support Chris Morgan
2021-06-04 15:10 ` Chris Morgan
2021-06-04 15:10 ` Chris Morgan
2021-06-04 15:10 ` [RFC v4 1/8] dt-bindings: rockchip-sfc: Bindings for Rockchip serial flash controller Chris Morgan
2021-06-04 15:10   ` Chris Morgan
2021-06-04 15:10   ` Chris Morgan
2021-06-04 15:31   ` Rob Herring
2021-06-04 15:31     ` Rob Herring
2021-06-04 15:31     ` Rob Herring
2021-06-04 15:44     ` Chris Morgan
2021-06-04 15:44       ` Chris Morgan
2021-06-04 15:10 ` [RFC v4 2/8] spi: rockchip-sfc: add rockchip " Chris Morgan
2021-06-04 15:10   ` Chris Morgan
2021-06-04 15:10   ` Chris Morgan
2021-06-06 10:47   ` Lukas Wunner
2021-06-04 15:10 ` [RFC v4 3/8] arm64: dts: rockchip: Add SFC to PX30 Chris Morgan
2021-06-04 15:10   ` Chris Morgan
2021-06-04 15:10   ` Chris Morgan
2021-06-04 15:10 ` [RFC v4 4/8] clk: rockchip: Add support for hclk_sfc on rk3036 Chris Morgan
2021-06-04 15:10   ` Chris Morgan
2021-06-04 15:10   ` Chris Morgan
2021-06-04 15:10 ` Chris Morgan [this message]
2021-06-04 15:10   ` [RFC v4 5/8] arm: dts: rockchip: Add SFC to RK3036 Chris Morgan
2021-06-04 15:10   ` Chris Morgan
2021-06-04 15:10 ` [RFC v4 6/8] arm: dts: rockchip: Add SFC to RV1108 Chris Morgan
2021-06-04 15:10   ` Chris Morgan
2021-06-04 15:10   ` Chris Morgan
2021-06-04 15:10 ` [RFC v4 7/8] arm64: dts: rockchip: Add SFC to RK3308 Chris Morgan
2021-06-04 15:10   ` Chris Morgan
2021-06-04 15:10   ` Chris Morgan
2021-06-04 15:10 ` [RFC v4 8/8] arm64: dts: rockchip: Enable SFC for Odroid Go Advance Chris Morgan
2021-06-04 15:10   ` Chris Morgan
2021-06-04 15:10   ` Chris Morgan

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