From: kernel test robot <lkp@intel.com>
To: kbuild-all@lists.01.org
Subject: Re: [PATCH 3/3] i2c:support new register set for ast2600
Date: Thu, 17 Jun 2021 22:48:20 +0800 [thread overview]
Message-ID: <202106172249.UYoFTs0w-lkp@intel.com> (raw)
In-Reply-To: <20210617094424.27123-4-jamin_lin@aspeedtech.com>
[-- Attachment #1: Type: text/plain, Size: 14453 bytes --]
Hi Jamin,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on wsa/i2c/for-next]
[also build test WARNING on robh/for-next joel-aspeed/for-next v5.13-rc6 next-20210617]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Jamin-Lin/Support-ASPEED-AST2600-I2C/20210617-174709
base: https://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git i2c/for-next
config: arm-allyesconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/8d16cf8cbc5d3dccd05c23dd7c4744a0890e356f
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Jamin-Lin/Support-ASPEED-AST2600-I2C/20210617-174709
git checkout 8d16cf8cbc5d3dccd05c23dd7c4744a0890e356f
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/i2c/busses/i2c-new-aspeed.c:542:6: warning: no previous prototype for 'aspeed_i2c_slave_packet_irq' [-Wmissing-prototypes]
542 | void aspeed_i2c_slave_packet_irq(struct aspeed_new_i2c_bus *i2c_bus, u32 sts)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/i2c/busses/i2c-new-aspeed.c:827:6: warning: no previous prototype for 'aspeed_i2c_slave_byte_irq' [-Wmissing-prototypes]
827 | void aspeed_i2c_slave_byte_irq(struct aspeed_new_i2c_bus *i2c_bus, u32 sts)
| ^~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/i2c/busses/i2c-new-aspeed.c:883:5: warning: no previous prototype for 'aspeed_new_i2c_slave_irq' [-Wmissing-prototypes]
883 | int aspeed_new_i2c_slave_irq(struct aspeed_new_i2c_bus *i2c_bus)
| ^~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/i2c/busses/i2c-new-aspeed.c:1091:6: warning: no previous prototype for 'aspeed_i2c_master_package_irq' [-Wmissing-prototypes]
1091 | void aspeed_i2c_master_package_irq(struct aspeed_new_i2c_bus *i2c_bus, u32 sts)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/i2c/busses/i2c-new-aspeed.c:1347:5: warning: no previous prototype for 'aspeed_new_i2c_master_irq' [-Wmissing-prototypes]
1347 | int aspeed_new_i2c_master_irq(struct aspeed_new_i2c_bus *i2c_bus)
| ^~~~~~~~~~~~~~~~~~~~~~~~~
vim +/aspeed_i2c_slave_packet_irq +542 drivers/i2c/busses/i2c-new-aspeed.c
540
541 #ifdef CONFIG_I2C_SLAVE
> 542 void aspeed_i2c_slave_packet_irq(struct aspeed_new_i2c_bus *i2c_bus, u32 sts)
543 {
544 u32 cmd = 0;
545 u8 value;
546 u8 byte_data;
547 int i = 0;
548 int slave_rx_len;
549
550 sts &= ~(AST_I2CS_PKT_DONE | AST_I2CS_PKT_ERROR);
551 writel(AST_I2CS_PKT_DONE, i2c_bus->reg_base + AST_I2CS_ISR);
552 switch (sts) {
553 case 0:
554 cmd = SLAVE_TRIGGER_CMD;
555 if (i2c_bus->mode == DMA_MODE)
556 cmd |= AST_I2CS_RX_DMA_EN;
557 else if (i2c_bus->mode == BUFF_MODE)
558 cmd |= AST_I2CS_RX_BUFF_EN;
559 else
560 cmd &= ~AST_I2CS_PKT_MODE_EN;
561 writel(cmd, i2c_bus->reg_base + AST_I2CS_CMD_STS);
562 break;
563 case AST_I2CS_SLAVE_MATCH:
564 dev_dbg(i2c_bus->dev, "S : Sw\n");
565 i2c_slave_event(i2c_bus->slave,
566 I2C_SLAVE_WRITE_REQUESTED, &value);
567 break;
568
569 case AST_I2CS_SLAVE_MATCH | AST_I2CS_STOP:
570 dev_dbg(i2c_bus->dev, "S : Sw|P\n");
571 i2c_slave_event(i2c_bus->slave, I2C_SLAVE_STOP, &value);
572 cmd = SLAVE_TRIGGER_CMD;
573 if (i2c_bus->mode == DMA_MODE) {
574 cmd |= AST_I2CS_RX_DMA_EN;
575 writel(AST_I2CS_SET_RX_DMA_LEN(I2C_SLAVE_MSG_BUF_SIZE),
576 i2c_bus->reg_base + AST_I2CS_DMA_LEN);
577 } else if (i2c_bus->mode == BUFF_MODE) {
578 cmd |= AST_I2CS_RX_BUFF_EN;
579 writel(AST_I2CC_SET_RX_BUF_LEN(i2c_bus->buf_size),
580 i2c_bus->reg_base + AST_I2CC_BUFF_CTRL);
581 } else {
582 cmd &= ~AST_I2CS_PKT_MODE_EN;
583 }
584 writel(cmd, i2c_bus->reg_base + AST_I2CS_CMD_STS);
585 break;
586
587 case AST_I2CS_SLAVE_MATCH | AST_I2CS_RX_DONE |
588 AST_I2CS_Wait_RX_DMA | AST_I2CS_STOP:
589 case AST_I2CS_RX_DONE | AST_I2CS_Wait_RX_DMA | AST_I2CS_STOP:
590 case AST_I2CS_RX_DONE | AST_I2CS_STOP:
591 case AST_I2CS_SLAVE_MATCH | AST_I2CS_RX_DONE | AST_I2CS_Wait_RX_DMA:
592 case AST_I2CS_SLAVE_MATCH | AST_I2CS_RX_DONE | AST_I2CS_STOP:
593 cmd = SLAVE_TRIGGER_CMD;
594 if (sts & AST_I2CS_STOP) {
595 if (sts & AST_I2CS_SLAVE_MATCH)
596 dev_dbg(i2c_bus->dev, "S : Sw|D|P\n");
597 else
598 dev_dbg(i2c_bus->dev, "S : D|P\n");
599 } else {
600 dev_dbg(i2c_bus->dev, "S : Sw|D\n");
601 }
602
603 if (sts & AST_I2CS_SLAVE_MATCH)
604 i2c_slave_event(i2c_bus->slave,
605 I2C_SLAVE_WRITE_REQUESTED,
606 &value);
607
608 if (i2c_bus->mode == DMA_MODE) {
609 cmd |= AST_I2CS_RX_DMA_EN;
610 slave_rx_len =
611 AST_I2C_GET_RX_DMA_LEN(readl(i2c_bus->reg_base +
612 AST_I2CS_DMA_LEN_STS));
613 dev_dbg(i2c_bus->dev, "rx len %d\n", slave_rx_len);
614 for (i = 0; i < slave_rx_len; i++) {
615 i2c_slave_event(i2c_bus->slave,
616 I2C_SLAVE_WRITE_RECEIVED,
617 &i2c_bus->slave_dma_buf[i]);
618 }
619 writel(AST_I2CS_SET_RX_DMA_LEN(I2C_SLAVE_MSG_BUF_SIZE),
620 i2c_bus->reg_base + AST_I2CS_DMA_LEN);
621 } else if (i2c_bus->mode == BUFF_MODE) {
622 cmd |= AST_I2CS_RX_BUFF_EN;
623 slave_rx_len =
624 AST_I2CC_GET_RX_BUF_LEN(readl(i2c_bus->reg_base +
625 AST_I2CC_BUFF_CTRL));
626 for (i = 0; i < slave_rx_len; i++) {
627 value = readb(i2c_bus->buf_base + i);
628 dev_dbg(i2c_bus->dev, "[%02x]", value);
629 i2c_slave_event(i2c_bus->slave,
630 I2C_SLAVE_WRITE_RECEIVED,
631 &value);
632 }
633 writel(AST_I2CC_SET_RX_BUF_LEN(i2c_bus->buf_size),
634 i2c_bus->reg_base + AST_I2CC_BUFF_CTRL);
635 } else {
636 cmd &= ~AST_I2CS_PKT_MODE_EN;
637 byte_data = AST_I2CC_GET_RX_BUFF(readl(i2c_bus->reg_base +
638 AST_I2CC_STS_AND_BUFF));
639 dev_dbg(i2c_bus->dev, "[%02x]", byte_data);
640 i2c_slave_event(i2c_bus->slave,
641 I2C_SLAVE_WRITE_RECEIVED,
642 &byte_data);
643 }
644 if (sts & AST_I2CS_STOP)
645 i2c_slave_event(i2c_bus->slave, I2C_SLAVE_STOP,
646 &value);
647 writel(cmd, i2c_bus->reg_base + AST_I2CS_CMD_STS);
648 break;
649
650 /* it is Mw data Mr coming -> it need send tx */
651 case AST_I2CS_RX_DONE | AST_I2CS_Wait_TX_DMA:
652 case AST_I2CS_SLAVE_MATCH | AST_I2CS_RX_DONE | AST_I2CS_Wait_TX_DMA:
653 /* it should be repeat start read */
654 if (sts & AST_I2CS_SLAVE_MATCH)
655 dev_dbg(i2c_bus->dev,
656 "S: AST_I2CS_Wait_TX_DMA | AST_I2CS_SLAVE_MATCH | AST_I2CS_RX_DONE\n");
657 else
658 dev_dbg(i2c_bus->dev,
659 "S: AST_I2CS_Wait_TX_DMA | AST_I2CS_RX_DONE\n");
660
661 if (sts & AST_I2CS_SLAVE_MATCH)
662 i2c_slave_event(i2c_bus->slave,
663 I2C_SLAVE_WRITE_REQUESTED,
664 &value);
665
666 cmd = SLAVE_TRIGGER_CMD;
667 if (i2c_bus->mode == DMA_MODE) {
668 cmd |= AST_I2CS_TX_DMA_EN;
669 slave_rx_len =
670 AST_I2C_GET_RX_DMA_LEN(readl(i2c_bus->reg_base +
671 AST_I2CS_DMA_LEN_STS));
672 for (i = 0; i < slave_rx_len; i++) {
673 dev_dbg(i2c_bus->dev, "rx [%02x]",
674 i2c_bus->slave_dma_buf[i]);
675 i2c_slave_event(i2c_bus->slave,
676 I2C_SLAVE_WRITE_RECEIVED,
677 &i2c_bus->slave_dma_buf[i]);
678 }
679 i2c_slave_event(i2c_bus->slave,
680 I2C_SLAVE_READ_REQUESTED,
681 &i2c_bus->slave_dma_buf[0]);
682 dev_dbg(i2c_bus->dev, "tx : [%02x]",
683 i2c_bus->slave_dma_buf[0]);
684 writel(0, i2c_bus->reg_base + AST_I2CS_DMA_LEN_STS);
685 writel(AST_I2CS_SET_TX_DMA_LEN(1),
686 i2c_bus->reg_base + AST_I2CS_DMA_LEN);
687 } else if (i2c_bus->mode == BUFF_MODE) {
688 cmd |= AST_I2CS_TX_BUFF_EN;
689 slave_rx_len =
690 AST_I2CC_GET_RX_BUF_LEN(readl(i2c_bus->reg_base +
691 AST_I2CC_BUFF_CTRL));
692 for (i = 0; i < slave_rx_len; i++) {
693 value = readb(i2c_bus->buf_base + i);
694 dev_dbg(i2c_bus->dev, "rx : [%02x]",
695 value);
696 i2c_slave_event(i2c_bus->slave,
697 I2C_SLAVE_WRITE_RECEIVED,
698 &value);
699 }
700 i2c_slave_event(i2c_bus->slave,
701 I2C_SLAVE_READ_REQUESTED,
702 &value);
703 dev_dbg(i2c_bus->dev, "tx : [%02x]", value);
704 writeb(value, i2c_bus->buf_base);
705 writel(AST_I2CC_SET_TX_BUF_LEN(1),
706 i2c_bus->reg_base + AST_I2CC_BUFF_CTRL);
707 } else {
708 cmd &= ~AST_I2CS_PKT_MODE_EN;
709 cmd |= AST_I2CS_TX_CMD;
710 byte_data = AST_I2CC_GET_RX_BUFF(readl(i2c_bus->reg_base +
711 AST_I2CC_STS_AND_BUFF));
712 dev_dbg(i2c_bus->dev, "rx : [%02x]", byte_data);
713 i2c_slave_event(i2c_bus->slave,
714 I2C_SLAVE_WRITE_RECEIVED,
715 &byte_data);
716 i2c_slave_event(i2c_bus->slave,
717 I2C_SLAVE_READ_REQUESTED,
718 &byte_data);
719 dev_dbg(i2c_bus->dev, "tx : [%02x]", byte_data);
720 writel(byte_data, i2c_bus->reg_base +
721 AST_I2CC_STS_AND_BUFF);
722 }
723 writel(cmd, i2c_bus->reg_base + AST_I2CS_CMD_STS);
724 break;
725
726 case AST_I2CS_SLAVE_MATCH | AST_I2CS_Wait_TX_DMA:
727 /* First Start read */
728 dev_dbg(i2c_bus->dev,
729 "S: AST_I2CS_SLAVE_MATCH | AST_I2CS_Wait_TX_DMA\n");
730 cmd = SLAVE_TRIGGER_CMD;
731 if (i2c_bus->mode == DMA_MODE) {
732 cmd |= AST_I2CS_TX_DMA_EN;
733 i2c_slave_event(i2c_bus->slave,
734 I2C_SLAVE_READ_REQUESTED,
735 &i2c_bus->slave_dma_buf[0]);
736 dev_dbg(i2c_bus->dev, "tx: [%x]\n",
737 i2c_bus->slave_dma_buf[0]);
738 writel(AST_I2CS_SET_TX_DMA_LEN(1),
739 i2c_bus->reg_base + AST_I2CS_DMA_LEN);
740 } else if (i2c_bus->mode == BUFF_MODE) {
741 cmd |= AST_I2CS_TX_BUFF_EN;
742 i2c_slave_event(i2c_bus->slave,
743 I2C_SLAVE_READ_REQUESTED,
744 &byte_data);
745 dev_dbg(i2c_bus->dev, "tx : [%02x]", byte_data);
746 writeb(byte_data, i2c_bus->buf_base);
747 writel(AST_I2CC_SET_TX_BUF_LEN(1),
748 i2c_bus->reg_base + AST_I2CC_BUFF_CTRL);
749 } else {
750 cmd &= ~AST_I2CS_PKT_MODE_EN;
751 cmd |= AST_I2CS_TX_CMD;
752 i2c_slave_event(i2c_bus->slave,
753 I2C_SLAVE_READ_REQUESTED,
754 &byte_data);
755 writel(byte_data, i2c_bus->reg_base +
756 AST_I2CC_STS_AND_BUFF);
757 }
758 writel(cmd, i2c_bus->reg_base + AST_I2CS_CMD_STS);
759 break;
760
761 case AST_I2CS_Wait_TX_DMA:
762 /* it should be next start read */
763 dev_dbg(i2c_bus->dev, "S: AST_I2CS_Wait_TX_DMA\n");
764 cmd = SLAVE_TRIGGER_CMD;
765 if (i2c_bus->mode == DMA_MODE) {
766 cmd |= AST_I2CS_TX_DMA_EN;
767 i2c_slave_event(i2c_bus->slave,
768 I2C_SLAVE_READ_PROCESSED,
769 &i2c_bus->slave_dma_buf[0]);
770 dev_dbg(i2c_bus->dev, "tx : [%02x]",
771 i2c_bus->slave_dma_buf[0]);
772 writel(0, i2c_bus->reg_base + AST_I2CS_DMA_LEN_STS);
773 writel(AST_I2CS_SET_TX_DMA_LEN(1),
774 i2c_bus->reg_base + AST_I2CS_DMA_LEN);
775 } else if (i2c_bus->mode == BUFF_MODE) {
776 cmd |= AST_I2CS_TX_BUFF_EN;
777 i2c_slave_event(i2c_bus->slave,
778 I2C_SLAVE_READ_PROCESSED,
779 &value);
780 dev_dbg(i2c_bus->dev, "tx: [%02x]\n", value);
781 writeb(value, i2c_bus->buf_base);
782 writel(AST_I2CC_SET_TX_BUF_LEN(1),
783 i2c_bus->reg_base + AST_I2CC_BUFF_CTRL);
784 } else {
785 cmd &= ~AST_I2CS_PKT_MODE_EN;
786 cmd |= AST_I2CS_TX_CMD;
787 i2c_slave_event(i2c_bus->slave,
788 I2C_SLAVE_READ_PROCESSED,
789 &byte_data);
790 dev_dbg(i2c_bus->dev, "tx: [%02x]\n",
791 byte_data);
792 writel(byte_data, i2c_bus->reg_base +
793 AST_I2CC_STS_AND_BUFF);
794 }
795 writel(cmd, i2c_bus->reg_base + AST_I2CS_CMD_STS);
796 break;
797
798 case AST_I2CS_TX_NAK | AST_I2CS_STOP:
799 /* it just tx complete */
800 dev_dbg(i2c_bus->dev,
801 "S: AST_I2CS_TX_NAK | AST_I2CS_STOP\n");
802 cmd = SLAVE_TRIGGER_CMD;
803 i2c_slave_event(i2c_bus->slave, I2C_SLAVE_STOP, &value);
804 if (i2c_bus->mode == DMA_MODE) {
805 cmd |= AST_I2CS_RX_DMA_EN;
806 writel(0, i2c_bus->reg_base + AST_I2CS_DMA_LEN_STS);
807 writel(AST_I2CS_SET_RX_DMA_LEN(I2C_SLAVE_MSG_BUF_SIZE),
808 i2c_bus->reg_base + AST_I2CS_DMA_LEN);
809 } else if (i2c_bus->mode == BUFF_MODE) {
810 cmd |= AST_I2CS_RX_BUFF_EN;
811 writel(AST_I2CC_SET_RX_BUF_LEN(i2c_bus->buf_size),
812 i2c_bus->reg_base + AST_I2CC_BUFF_CTRL);
813 } else {
814 cmd &= ~AST_I2CS_PKT_MODE_EN;
815 }
816 writel(cmd, i2c_bus->reg_base + AST_I2CS_CMD_STS);
817 break;
818
819 default:
820 dev_dbg(i2c_bus->dev,
821 "todo slave sts case %x, now %x\n", sts,
822 readl(i2c_bus->reg_base + AST_I2CS_ISR));
823 break;
824 }
825 }
826
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 78563 bytes --]
prev parent reply other threads:[~2021-06-17 14:48 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-17 9:43 [PATCH 0/3] *** Support ASPEED AST2600 I2C *** Jamin Lin
2021-06-17 9:43 ` Jamin Lin
2021-06-17 9:43 ` Jamin Lin
2021-06-17 9:43 ` [PATCH 1/3] dts: aspeed: Add node for AST2600 I2C and I2CS Jamin Lin
2021-06-17 9:43 ` Jamin Lin
2021-06-17 9:43 ` Jamin Lin
2021-06-17 9:43 ` [PATCH 2/3] dt-bindings: i2c-new: Add bindings for AST2600 I2C Jamin Lin
2021-06-17 9:43 ` Jamin Lin
2021-06-17 9:43 ` Jamin Lin
2021-06-24 21:28 ` Rob Herring
2021-06-24 21:28 ` Rob Herring
2021-06-24 21:28 ` Rob Herring
2021-06-17 9:43 ` [PATCH 3/3] i2c:support new register set for ast2600 Jamin Lin
2021-06-17 9:43 ` Jamin Lin
2021-06-17 9:43 ` Jamin Lin
2021-06-17 10:33 ` Andy Shevchenko
2021-06-17 10:33 ` Andy Shevchenko
2021-06-17 10:33 ` Andy Shevchenko
2021-06-18 3:53 ` Jamin Lin
2021-06-18 3:53 ` Jamin Lin
2021-06-18 3:53 ` Jamin Lin
2021-06-18 9:59 ` Andy Shevchenko
2021-06-18 9:59 ` Andy Shevchenko
2021-06-18 9:59 ` Andy Shevchenko
2021-06-21 5:13 ` Jamin Lin
2021-06-21 5:13 ` Jamin Lin
2021-06-21 5:13 ` Jamin Lin
2021-06-17 10:36 ` Andy Shevchenko
2021-06-17 10:36 ` Andy Shevchenko
2021-06-17 10:36 ` Andy Shevchenko
2021-06-18 3:58 ` Jamin Lin
2021-06-18 3:58 ` Jamin Lin
2021-06-18 3:58 ` Jamin Lin
2021-06-18 10:00 ` Andy Shevchenko
2021-06-18 10:00 ` Andy Shevchenko
2021-06-18 10:00 ` Andy Shevchenko
2021-06-21 5:14 ` Jamin Lin
2021-06-21 5:14 ` Jamin Lin
2021-06-21 5:14 ` Jamin Lin
2021-06-17 14:48 ` kernel test robot [this message]
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