From: Catalin Marinas <catalin.marinas@arm.com>
To: Peter Collingbourne <pcc@google.com>
Cc: Vincenzo Frascino <vincenzo.frascino@arm.com>,
Will Deacon <will@kernel.org>,
Evgenii Stepanov <eugenis@google.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2] arm64: mte: avoid TFSR related operations unless in async mode
Date: Tue, 27 Jul 2021 18:19:05 +0100 [thread overview]
Message-ID: <20210727171905.GR13920@arm.com> (raw)
In-Reply-To: <20210709023532.2133673-1-pcc@google.com>
On Thu, Jul 08, 2021 at 07:35:32PM -0700, Peter Collingbourne wrote:
> There is no reason to touch TFSR nor issue a DSB unless our task is
> in asynchronous mode. Since these operations (especially the DSB)
> may be expensive on certain microarchitectures, only perform them
> if necessary.
>
> Furthermore, stop clearing TFSR on entry because it will be cleared
> on exit and it is not necessary to have any particular value in TFSR
> between entry and exit.
Nitpick: this should be clearer that it's about TFSRE0_EL1 not the
kernel's TFSR_EL1.
Anyway, the patch looks fine, no need to repost. I can change the
comment.
Thanks.
--
Catalin
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next prev parent reply other threads:[~2021-07-27 17:20 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-09 2:35 [PATCH v2] arm64: mte: avoid TFSR related operations unless in async mode Peter Collingbourne
2021-07-27 17:19 ` Catalin Marinas [this message]
2021-07-27 18:06 ` Catalin Marinas
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