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From: Jisheng Zhang <jszhang3@mail.ustc.edu.cn>
To: Xianting Tian <xianting.tian@linux.alibaba.com>
Cc: paul.walmsley@sifive.com, palmer@dabbelt.com,
	aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH] riscv: add ARCH_DMA_MINALIGN support
Date: Mon, 9 Aug 2021 00:30:44 +0800	[thread overview]
Message-ID: <20210809003044.6692ddce@xhacker> (raw)
In-Reply-To: <20210807145537.124744-1-xianting.tian@linux.alibaba.com>

On Sat,  7 Aug 2021 22:55:37 +0800
Xianting Tian <xianting.tian@linux.alibaba.com> wrote:

> Introduce ARCH_DMA_MINALIGN to riscv arch.
> 
> Signed-off-by: Xianting Tian <xianting.tian@linux.alibaba.com>
> ---
>  arch/riscv/include/asm/cache.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
> index 9b58b1045..2945bbe2b 100644
> --- a/arch/riscv/include/asm/cache.h
> +++ b/arch/riscv/include/asm/cache.h
> @@ -11,6 +11,8 @@
>  
>  #define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
>  
> +#define ARCH_DMA_MINALIGN	L1_CACHE_BYTES

It's not a good idea to blindly set this for all riscv. For "coherent"
platforms, this is not necessary and will waste memory.


> +
>  /*
>   * RISC-V requires the stack pointer to be 16-byte aligned, so ensure that
>   * the flat loader aligns it accordingly.



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WARNING: multiple messages have this Message-ID (diff)
From: Jisheng Zhang <jszhang3@mail.ustc.edu.cn>
To: Xianting Tian <xianting.tian@linux.alibaba.com>
Cc: paul.walmsley@sifive.com, palmer@dabbelt.com,
	aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH] riscv: add ARCH_DMA_MINALIGN support
Date: Mon, 9 Aug 2021 00:30:44 +0800	[thread overview]
Message-ID: <20210809003044.6692ddce@xhacker> (raw)
In-Reply-To: <20210807145537.124744-1-xianting.tian@linux.alibaba.com>

On Sat,  7 Aug 2021 22:55:37 +0800
Xianting Tian <xianting.tian@linux.alibaba.com> wrote:

> Introduce ARCH_DMA_MINALIGN to riscv arch.
> 
> Signed-off-by: Xianting Tian <xianting.tian@linux.alibaba.com>
> ---
>  arch/riscv/include/asm/cache.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
> index 9b58b1045..2945bbe2b 100644
> --- a/arch/riscv/include/asm/cache.h
> +++ b/arch/riscv/include/asm/cache.h
> @@ -11,6 +11,8 @@
>  
>  #define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
>  
> +#define ARCH_DMA_MINALIGN	L1_CACHE_BYTES

It's not a good idea to blindly set this for all riscv. For "coherent"
platforms, this is not necessary and will waste memory.


> +
>  /*
>   * RISC-V requires the stack pointer to be 16-byte aligned, so ensure that
>   * the flat loader aligns it accordingly.



  reply	other threads:[~2021-08-08 16:37 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-07 14:55 [PATCH] riscv: add ARCH_DMA_MINALIGN support Xianting Tian
2021-08-07 14:55 ` Xianting Tian
2021-08-08 16:30 ` Jisheng Zhang [this message]
2021-08-08 16:30   ` Jisheng Zhang
2021-08-09  1:55   ` Xianting TIan
2021-08-09  1:55     ` Xianting TIan
2021-08-10  1:30     ` Guo Ren
2021-08-10  1:30       ` Guo Ren
2021-08-09  6:20   ` Xianting TIan
2021-08-09  6:20     ` Xianting TIan
2021-08-09  7:49     ` Arnd Bergmann
2021-08-09  7:49       ` Arnd Bergmann
2021-08-09  9:00       ` Xianting TIan
2021-08-09  9:00         ` Xianting TIan
2021-08-09 19:19       ` Atish Patra
2021-08-09 19:19         ` Atish Patra

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