From: Raghavendra Rao Ananta <rananta@google.com>
To: Paolo Bonzini <pbonzini@redhat.com>, Marc Zyngier <maz@kernel.org>
Cc: kvm@vger.kernel.org, Peter Shier <pshier@google.com>,
Raghavendra Rao Anata <rananta@google.com>,
kvmarm@lists.cs.columbia.edu
Subject: [PATCH v2 01/10] KVM: arm64: selftests: Add MMIO readl/writel support
Date: Wed, 18 Aug 2021 18:43:02 +0000 [thread overview]
Message-ID: <20210818184311.517295-2-rananta@google.com> (raw)
In-Reply-To: <20210818184311.517295-1-rananta@google.com>
Define the readl() and writel() functions for the guests to
access (4-byte) the MMIO region.
The routines, and their dependents, are inspired from the kernel's
arch/arm64/include/asm/io.h and arch/arm64/include/asm/barrier.h.
Signed-off-by: Raghavendra Rao Ananta <rananta@google.com>
---
.../selftests/kvm/include/aarch64/processor.h | 45 ++++++++++++++++++-
1 file changed, 44 insertions(+), 1 deletion(-)
diff --git a/tools/testing/selftests/kvm/include/aarch64/processor.h b/tools/testing/selftests/kvm/include/aarch64/processor.h
index 27dc5c2e56b9..14f68bf55036 100644
--- a/tools/testing/selftests/kvm/include/aarch64/processor.h
+++ b/tools/testing/selftests/kvm/include/aarch64/processor.h
@@ -127,6 +127,49 @@ void vm_install_sync_handler(struct kvm_vm *vm,
val; \
})
-#define isb() asm volatile("isb" : : : "memory")
+#define isb() asm volatile("isb" : : : "memory")
+#define dsb(opt) asm volatile("dsb " #opt : : : "memory")
+#define dmb(opt) asm volatile("dmb " #opt : : : "memory")
+
+#define dma_wmb() dmb(oshst)
+#define __iowmb() dma_wmb()
+
+#define dma_rmb() dmb(oshld)
+
+#define __iormb(v) \
+({ \
+ unsigned long tmp; \
+ \
+ dma_rmb(); \
+ \
+ /* \
+ * Courtesy of arch/arm64/include/asm/io.h: \
+ * Create a dummy control dependency from the IO read to any \
+ * later instructions. This ensures that a subsequent call \
+ * to udelay() will be ordered due to the ISB in __delay(). \
+ */ \
+ asm volatile("eor %0, %1, %1\n" \
+ "cbnz %0, ." \
+ : "=r" (tmp) : "r" ((unsigned long)(v)) \
+ : "memory"); \
+})
+
+static __always_inline void __raw_writel(u32 val, volatile void *addr)
+{
+ asm volatile("str %w0, [%1]" : : "rZ" (val), "r" (addr));
+}
+
+static __always_inline u32 __raw_readl(const volatile void *addr)
+{
+ u32 val;
+ asm volatile("ldr %w0, [%1]" : "=r" (val) : "r" (addr));
+ return val;
+}
+
+#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
+#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
+
+#define writel(v,c) ({ __iowmb(); writel_relaxed((v),(c));})
+#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(__v); __v; })
#endif /* SELFTEST_KVM_PROCESSOR_H */
--
2.33.0.rc1.237.g0d66db33f3-goog
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WARNING: multiple messages have this Message-ID (diff)
From: Raghavendra Rao Ananta <rananta@google.com>
To: Paolo Bonzini <pbonzini@redhat.com>, Marc Zyngier <maz@kernel.org>
Cc: Alexandru Elisei <alexandru.elisei@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
James Morse <james.morse@arm.com>,
Peter Shier <pshier@google.com>,
Ricardo Koller <ricarkol@google.com>,
Oliver Upton <oupton@google.com>,
Reiji Watanabe <reijiw@google.com>,
Jing Zhang <jingzhangos@google.com>,
Raghavendra Rao Anata <rananta@google.com>,
kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu
Subject: [PATCH v2 01/10] KVM: arm64: selftests: Add MMIO readl/writel support
Date: Wed, 18 Aug 2021 18:43:02 +0000 [thread overview]
Message-ID: <20210818184311.517295-2-rananta@google.com> (raw)
In-Reply-To: <20210818184311.517295-1-rananta@google.com>
Define the readl() and writel() functions for the guests to
access (4-byte) the MMIO region.
The routines, and their dependents, are inspired from the kernel's
arch/arm64/include/asm/io.h and arch/arm64/include/asm/barrier.h.
Signed-off-by: Raghavendra Rao Ananta <rananta@google.com>
---
.../selftests/kvm/include/aarch64/processor.h | 45 ++++++++++++++++++-
1 file changed, 44 insertions(+), 1 deletion(-)
diff --git a/tools/testing/selftests/kvm/include/aarch64/processor.h b/tools/testing/selftests/kvm/include/aarch64/processor.h
index 27dc5c2e56b9..14f68bf55036 100644
--- a/tools/testing/selftests/kvm/include/aarch64/processor.h
+++ b/tools/testing/selftests/kvm/include/aarch64/processor.h
@@ -127,6 +127,49 @@ void vm_install_sync_handler(struct kvm_vm *vm,
val; \
})
-#define isb() asm volatile("isb" : : : "memory")
+#define isb() asm volatile("isb" : : : "memory")
+#define dsb(opt) asm volatile("dsb " #opt : : : "memory")
+#define dmb(opt) asm volatile("dmb " #opt : : : "memory")
+
+#define dma_wmb() dmb(oshst)
+#define __iowmb() dma_wmb()
+
+#define dma_rmb() dmb(oshld)
+
+#define __iormb(v) \
+({ \
+ unsigned long tmp; \
+ \
+ dma_rmb(); \
+ \
+ /* \
+ * Courtesy of arch/arm64/include/asm/io.h: \
+ * Create a dummy control dependency from the IO read to any \
+ * later instructions. This ensures that a subsequent call \
+ * to udelay() will be ordered due to the ISB in __delay(). \
+ */ \
+ asm volatile("eor %0, %1, %1\n" \
+ "cbnz %0, ." \
+ : "=r" (tmp) : "r" ((unsigned long)(v)) \
+ : "memory"); \
+})
+
+static __always_inline void __raw_writel(u32 val, volatile void *addr)
+{
+ asm volatile("str %w0, [%1]" : : "rZ" (val), "r" (addr));
+}
+
+static __always_inline u32 __raw_readl(const volatile void *addr)
+{
+ u32 val;
+ asm volatile("ldr %w0, [%1]" : "=r" (val) : "r" (addr));
+ return val;
+}
+
+#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
+#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
+
+#define writel(v,c) ({ __iowmb(); writel_relaxed((v),(c));})
+#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(__v); __v; })
#endif /* SELFTEST_KVM_PROCESSOR_H */
--
2.33.0.rc1.237.g0d66db33f3-goog
next prev parent reply other threads:[~2021-08-18 20:00 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-18 18:43 [PATCH v2 00/10] KVM: arm64: selftests: Introduce arch_timer selftest Raghavendra Rao Ananta
2021-08-18 18:43 ` Raghavendra Rao Ananta
2021-08-18 18:43 ` Raghavendra Rao Ananta [this message]
2021-08-18 18:43 ` [PATCH v2 01/10] KVM: arm64: selftests: Add MMIO readl/writel support Raghavendra Rao Ananta
2021-08-18 18:43 ` [PATCH v2 02/10] KVM: arm64: selftests: Add write_sysreg_s and read_sysreg_s Raghavendra Rao Ananta
2021-08-18 18:43 ` Raghavendra Rao Ananta
2021-08-18 18:43 ` [PATCH v2 03/10] KVM: arm64: selftests: Add support for cpu_relax Raghavendra Rao Ananta
2021-08-18 18:43 ` Raghavendra Rao Ananta
2021-08-18 18:43 ` [PATCH v2 04/10] KVM: arm64: selftests: Add basic support for arch_timers Raghavendra Rao Ananta
2021-08-18 18:43 ` Raghavendra Rao Ananta
2021-08-18 18:43 ` [PATCH v2 05/10] KVM: arm64: selftests: Add basic support to generate delays Raghavendra Rao Ananta
2021-08-18 18:43 ` Raghavendra Rao Ananta
2021-08-18 18:43 ` [PATCH v2 06/10] KVM: arm64: selftests: Add support to disable and enable local IRQs Raghavendra Rao Ananta
2021-08-18 18:43 ` Raghavendra Rao Ananta
2021-08-18 18:43 ` [PATCH v2 07/10] KVM: arm64: selftests: Add support to get the vcpuid from MPIDR_EL1 Raghavendra Rao Ananta
2021-08-18 18:43 ` Raghavendra Rao Ananta
2021-08-18 18:43 ` [PATCH v2 08/10] KVM: arm64: selftests: Add light-weight spinlock support Raghavendra Rao Ananta
2021-08-18 18:43 ` Raghavendra Rao Ananta
2021-08-18 18:43 ` [PATCH v2 09/10] KVM: arm64: selftests: Add basic GICv3 support Raghavendra Rao Ananta
2021-08-18 18:43 ` Raghavendra Rao Ananta
2021-08-18 18:43 ` [PATCH v2 10/10] KVM: arm64: selftests: Add arch_timer test Raghavendra Rao Ananta
2021-08-18 18:43 ` Raghavendra Rao Ananta
2021-08-26 21:54 ` Ricardo Koller
2021-08-26 21:54 ` Ricardo Koller
2021-08-27 16:36 ` Raghavendra Rao Ananta
2021-08-27 16:36 ` Raghavendra Rao Ananta
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