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From: Jisheng Zhang <jszhang3@mail.ustc.edu.cn>
To: Chen Huang <chenhuang5@huawei.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Kefeng Wang <wangkefeng.wang@huawei.com>,
	Darius Rad <darius@bluespec.com>,
	<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 0/2] riscv: improve unaligned memory accesses
Date: Fri, 17 Sep 2021 22:14:29 +0800	[thread overview]
Message-ID: <20210917221429.4d3a15ca@xhacker> (raw)
In-Reply-To: <20210916130855.4054926-1-chenhuang5@huawei.com>

On Thu, 16 Sep 2021 13:08:53 +0000
Chen Huang <chenhuang5@huawei.com> wrote:

> The patchset improves RISCV unaligned memory accesses, selects
> HAVE_EFFICIENT_UNALIGNED_ACCESS if CPU_HAS_NO_UNALIGNED not
> enabled and supports DCACHE_WORD_ACCESS to improve the efficiency
> of unaligned memory accesses.
> 
> If CPU don't support unaligned memory accesses for now, please
> select CONFIG_CPU_HAS_NO_UNALIGNED. For I don't know which CPU
> don't support unaligned memory accesses, I don't choose the
> CONFIG for them.

This will break unified kernel Image for riscv. Obviously, we will have
two images for efficient unaligned access platforms and non-efficient
unaligned access platforms. IMHO, we may need alternative mechanism or
something else to dynamically enable related code path.

Regards

> 
> Changes since v1:
>  - As Darius Rad and Jisheng Zhang mentioned, some CPUs don't support
>    unaligned memory accesses, add an option for CPUs to choose it or not.
> 
> Chen Huang (2):
>   riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS
>   riscv: Support DCACHE_WORD_ACCESS
> 
>  arch/riscv/Kconfig                      |  5 ++++
>  arch/riscv/include/asm/word-at-a-time.h | 37 +++++++++++++++++++++++++
>  2 files changed, 42 insertions(+)
> 



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WARNING: multiple messages have this Message-ID (diff)
From: Jisheng Zhang <jszhang3@mail.ustc.edu.cn>
To: Chen Huang <chenhuang5@huawei.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Kefeng Wang <wangkefeng.wang@huawei.com>,
	Darius Rad <darius@bluespec.com>,
	<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 0/2] riscv: improve unaligned memory accesses
Date: Fri, 17 Sep 2021 22:14:29 +0800	[thread overview]
Message-ID: <20210917221429.4d3a15ca@xhacker> (raw)
In-Reply-To: <20210916130855.4054926-1-chenhuang5@huawei.com>

On Thu, 16 Sep 2021 13:08:53 +0000
Chen Huang <chenhuang5@huawei.com> wrote:

> The patchset improves RISCV unaligned memory accesses, selects
> HAVE_EFFICIENT_UNALIGNED_ACCESS if CPU_HAS_NO_UNALIGNED not
> enabled and supports DCACHE_WORD_ACCESS to improve the efficiency
> of unaligned memory accesses.
> 
> If CPU don't support unaligned memory accesses for now, please
> select CONFIG_CPU_HAS_NO_UNALIGNED. For I don't know which CPU
> don't support unaligned memory accesses, I don't choose the
> CONFIG for them.

This will break unified kernel Image for riscv. Obviously, we will have
two images for efficient unaligned access platforms and non-efficient
unaligned access platforms. IMHO, we may need alternative mechanism or
something else to dynamically enable related code path.

Regards

> 
> Changes since v1:
>  - As Darius Rad and Jisheng Zhang mentioned, some CPUs don't support
>    unaligned memory accesses, add an option for CPUs to choose it or not.
> 
> Chen Huang (2):
>   riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS
>   riscv: Support DCACHE_WORD_ACCESS
> 
>  arch/riscv/Kconfig                      |  5 ++++
>  arch/riscv/include/asm/word-at-a-time.h | 37 +++++++++++++++++++++++++
>  2 files changed, 42 insertions(+)
> 



  parent reply	other threads:[~2021-09-17 14:21 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-16 13:08 [PATCH v2 0/2] riscv: improve unaligned memory accesses Chen Huang
2021-09-16 13:08 ` Chen Huang
2021-09-16 13:08 ` [PATCH v2 1/2] riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS Chen Huang
2021-09-16 13:08   ` Chen Huang
2021-09-16 13:08 ` [PATCH v2 2/2] riscv: Support DCACHE_WORD_ACCESS Chen Huang
2021-09-16 13:08   ` Chen Huang
2021-09-17 14:14 ` Jisheng Zhang [this message]
2021-09-17 14:14   ` [PATCH v2 0/2] riscv: improve unaligned memory accesses Jisheng Zhang
2021-09-18  1:14   ` Kefeng Wang
2021-09-18  1:14     ` Kefeng Wang
2021-09-18 14:17     ` Jisheng Zhang
2021-09-18 14:17       ` Jisheng Zhang
2021-10-05  1:04       ` Palmer Dabbelt
2021-10-05  1:04         ` Palmer Dabbelt

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