[PATCH v2 0/6] hw/riscv: Use MachineState::ram and MachineClass::default_ram_id in all machines

[Bin Meng <bmeng.cn@gmail.com>]

As of today, all RISC-V machines (except virt) are still using memory_region_init_ram()
to initilize the sysytem RAM, which can't possibly handle vhost-user, and can't
work as expected with '-numa node,memdev' options.

Change to use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to opt in to
memdev scheme.

Changes in v2:
- split RAM into low and high regions using aliases to machine->ram
- rename mc->default_ram_id to "microchip.icicle.kit.ram"
- opentitan: add RAM size check
- opentitan: assign mc->default_ram_size
- sifive_e: add RAM size check
- sifive_e: assign mc->default_ram_size

Bin Meng (6):
  hw/riscv: microchip_pfsoc: Use MachineState::ram and
    MachineClass::default_ram_id
  hw/riscv: opentitan: Use MachineState::ram and
    MachineClass::default_ram_id
  hw/riscv: shakti_c: Use MachineState::ram and
    MachineClass::default_ram_id
  hw/riscv: sifive_e: Use MachineState::ram and
    MachineClass::default_ram_id
  hw/riscv: sifive_u: Use MachineState::ram and
    MachineClass::default_ram_id
  hw/riscv: spike: Use MachineState::ram and
    MachineClass::default_ram_id

 hw/riscv/microchip_pfsoc.c | 36 ++++++++++++++++++++----------------
 hw/riscv/opentitan.c       | 16 ++++++++++++----
 hw/riscv/shakti_c.c        |  6 ++----
 hw/riscv/sifive_e.c        | 16 ++++++++++++----
 hw/riscv/sifive_u.c        |  6 ++----
 hw/riscv/spike.c           |  6 ++----
 6 files changed, 50 insertions(+), 36 deletions(-)

-- 
2.25.1