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From: Chester Lin <clin@suse.com>
To: s32@nxp.com, "Andreas Färber" <afaerber@suse.de>,
	"Matthias Brugger" <mbrugger@suse.com>,
	devicetree@vger.kernel.org
Cc: Ulf Hansson <ulf.hansson@linaro.org>,
	Rob Herring <robh+dt@kernel.org>, Shawn Guo <shawnguo@kernel.org>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	Pengutronix Kernel Team <kernel@pengutronix.de>,
	Fabio Estevam <festevam@gmail.com>,
	NXP Linux Team <linux-imx@nxp.com>,
	linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	Radu Nicolae Pirea <radu-nicolae.pirea@oss.nxp.com>,
	Dong Aisheng <aisheng.dong@nxp.com>,
	BOUGH CHEN <haibo.chen@nxp.com>,
	"Ivan T . Ivanov" <iivanov@suse.de>,
	"Lee, Chun-Yi" <jlee@suse.com>, Chester Lin <clin@suse.com>
Subject: [PATCH 3/3] arm64: dts: s32g2: add USDHC support
Date: Thu, 21 Oct 2021 15:13:33 +0800	[thread overview]
Message-ID: <20211021071333.32485-4-clin@suse.com> (raw)
In-Reply-To: <20211021071333.32485-1-clin@suse.com>

Add a mmc node to support USDHC on NXP S32G2 platforms.

Signed-off-by: Chester Lin <clin@suse.com>
---
 arch/arm64/boot/dts/freescale/s32g2.dtsi      | 32 +++++++++++++++++++
 .../arm64/boot/dts/freescale/s32g274a-evb.dts |  4 +++
 .../boot/dts/freescale/s32g274a-rdb2.dts      |  4 +++
 3 files changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 59ea8a25aa4c..19e2e2561374 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -79,6 +79,26 @@ psci {
 		};
 	};
 
+	clocks {
+		usdhc_clk_module: usdhc_clk_module {
+			compatible = "fixed-clock";
+			clock-frequency = <133333333>;
+			#clock-cells = <0>;
+		};
+
+		usdhc_clk_ahb: usdhc_clk_ahb {
+			compatible = "fixed-clock";
+			clock-frequency = <400000000>;
+			#clock-cells = <0>;
+		};
+
+		usdhc_clk_core: usdhc_clk_core {
+			compatible = "fixed-clock";
+			clock-frequency = <400000000>;
+			#clock-cells = <0>;
+		};
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
@@ -109,6 +129,18 @@ uart2: serial@402bc000 {
 			status = "disabled";
 		};
 
+		usdhc0: mmc@402f0000 {
+			compatible = "nxp,s32g2-usdhc";
+			reg = <0x402f0000 0x1000>;
+			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+			bus-width = <8>;
+			clocks = <&usdhc_clk_module>, <&usdhc_clk_ahb>,
+				 <&usdhc_clk_core>;
+			clock-names = "ipg", "ahb", "per";
+			no-1-8-v;
+			status = "disabled";
+		};
+
 		gic: interrupt-controller@50800000 {
 			compatible = "arm,gic-v3";
 			reg = <0x50800000 0x10000>,
diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
index 9118d8d2ee01..89428f1883d9 100644
--- a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
+++ b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
@@ -32,3 +32,7 @@ memory@80000000 {
 &uart0 {
 	status = "okay";
 };
+
+&usdhc0 {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
index e05ee854cdf5..30eae51121de 100644
--- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
+++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
@@ -38,3 +38,7 @@ &uart0 {
 &uart1 {
 	status = "okay";
 };
+
+&usdhc0 {
+	status = "okay";
+};
-- 
2.30.0


WARNING: multiple messages have this Message-ID (diff)
From: Chester Lin <clin@suse.com>
To: s32@nxp.com, "Andreas Färber" <afaerber@suse.de>,
	"Matthias Brugger" <mbrugger@suse.com>,
	devicetree@vger.kernel.org
Cc: Ulf Hansson <ulf.hansson@linaro.org>,
	Rob Herring <robh+dt@kernel.org>, Shawn Guo <shawnguo@kernel.org>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	Pengutronix Kernel Team <kernel@pengutronix.de>,
	Fabio Estevam <festevam@gmail.com>,
	NXP Linux Team <linux-imx@nxp.com>,
	linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	Radu Nicolae Pirea <radu-nicolae.pirea@oss.nxp.com>,
	Dong Aisheng <aisheng.dong@nxp.com>,
	BOUGH CHEN <haibo.chen@nxp.com>,
	"Ivan T . Ivanov" <iivanov@suse.de>,
	"Lee, Chun-Yi" <jlee@suse.com>, Chester Lin <clin@suse.com>
Subject: [PATCH 3/3] arm64: dts: s32g2: add USDHC support
Date: Thu, 21 Oct 2021 15:13:33 +0800	[thread overview]
Message-ID: <20211021071333.32485-4-clin@suse.com> (raw)
In-Reply-To: <20211021071333.32485-1-clin@suse.com>

Add a mmc node to support USDHC on NXP S32G2 platforms.

Signed-off-by: Chester Lin <clin@suse.com>
---
 arch/arm64/boot/dts/freescale/s32g2.dtsi      | 32 +++++++++++++++++++
 .../arm64/boot/dts/freescale/s32g274a-evb.dts |  4 +++
 .../boot/dts/freescale/s32g274a-rdb2.dts      |  4 +++
 3 files changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 59ea8a25aa4c..19e2e2561374 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -79,6 +79,26 @@ psci {
 		};
 	};
 
+	clocks {
+		usdhc_clk_module: usdhc_clk_module {
+			compatible = "fixed-clock";
+			clock-frequency = <133333333>;
+			#clock-cells = <0>;
+		};
+
+		usdhc_clk_ahb: usdhc_clk_ahb {
+			compatible = "fixed-clock";
+			clock-frequency = <400000000>;
+			#clock-cells = <0>;
+		};
+
+		usdhc_clk_core: usdhc_clk_core {
+			compatible = "fixed-clock";
+			clock-frequency = <400000000>;
+			#clock-cells = <0>;
+		};
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
@@ -109,6 +129,18 @@ uart2: serial@402bc000 {
 			status = "disabled";
 		};
 
+		usdhc0: mmc@402f0000 {
+			compatible = "nxp,s32g2-usdhc";
+			reg = <0x402f0000 0x1000>;
+			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+			bus-width = <8>;
+			clocks = <&usdhc_clk_module>, <&usdhc_clk_ahb>,
+				 <&usdhc_clk_core>;
+			clock-names = "ipg", "ahb", "per";
+			no-1-8-v;
+			status = "disabled";
+		};
+
 		gic: interrupt-controller@50800000 {
 			compatible = "arm,gic-v3";
 			reg = <0x50800000 0x10000>,
diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
index 9118d8d2ee01..89428f1883d9 100644
--- a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
+++ b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
@@ -32,3 +32,7 @@ memory@80000000 {
 &uart0 {
 	status = "okay";
 };
+
+&usdhc0 {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
index e05ee854cdf5..30eae51121de 100644
--- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
+++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
@@ -38,3 +38,7 @@ &uart0 {
 &uart1 {
 	status = "okay";
 };
+
+&usdhc0 {
+	status = "okay";
+};
-- 
2.30.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2021-10-21  7:14 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-21  7:13 [PATCH 0/3] Add SDHCI driver support for NXP S32G2 Chester Lin
2021-10-21  7:13 ` Chester Lin
2021-10-21  7:13 ` [PATCH 1/3] dt-bindings: mmc: fsl-imx-esdhc: add NXP S32G2 support Chester Lin
2021-10-21  7:13   ` Chester Lin
2021-10-21  7:13 ` [RFC PATCH 2/3] mmc: sdhci-esdhc-imx: " Chester Lin
2021-10-21  7:13   ` Chester Lin
2021-10-21  7:21   ` Bough Chen
2021-10-21  7:21     ` Bough Chen
2021-10-21  7:30   ` Chester Lin
2021-10-21  7:30     ` Chester Lin
2021-10-21  8:00     ` Bough Chen
2021-10-21  8:00       ` Bough Chen
2021-10-21 13:59       ` Chester Lin
2021-10-21 13:59         ` Chester Lin
2021-10-21  7:13 ` Chester Lin [this message]
2021-10-21  7:13   ` [PATCH 3/3] arm64: dts: s32g2: add USDHC support Chester Lin
2021-10-21 13:32   ` Radu Nicolae Pirea (NXP OSS)
2021-10-21 13:32     ` Radu Nicolae Pirea (NXP OSS)
2021-10-21 14:38     ` Chester Lin
2021-10-21 14:38       ` Chester Lin
2021-10-26 15:39 ` [PATCH 0/3] Add SDHCI driver support for NXP S32G2 Ulf Hansson
2021-10-26 15:39   ` Ulf Hansson

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