From: Like Xu <like.xu.linux@gmail.com>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: Sean Christopherson <seanjc@google.com>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Wanpeng Li <wanpengli@tencent.com>,
Jim Mattson <jmattson@google.com>, Joerg Roedel <joro@8bytes.org>,
kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
Like Xu <likexu@tencent.com>,
Peter Zijlstra <peterz@infradead.org>
Subject: [PATCH 6/7] perf: x86/core: Add interface to query perfmon_event_map[] directly
Date: Fri, 12 Nov 2021 17:51:38 +0800 [thread overview]
Message-ID: <20211112095139.21775-7-likexu@tencent.com> (raw)
In-Reply-To: <20211112095139.21775-1-likexu@tencent.com>
From: Like Xu <likexu@tencent.com>
Currently, we have [intel|knc|p4|p6]_perfmon_event_map on the Intel
platforms and amd_[f17h]_perfmon_event_map on the AMD platforms.
Early clumsy KVM code or other potential perf_event users may have
hard-coded these perfmon_maps (e.g., arch/x86/kvm/svm/pmu.c), so
it would not make sense to program a common hardware event based
on the generic "enum perf_hw_id" once the two tables do not match.
Let's provide an interface for callers outside the perf subsystem to get
the counter config based on the perfmon_event_map currently in use,
and it also helps to save bytes.
Cc: Peter Zijlstra <peterz@infradead.org>
Signed-off-by: Like Xu <likexu@tencent.com>
---
arch/x86/events/core.c | 9 +++++++++
arch/x86/include/asm/perf_event.h | 5 +++++
2 files changed, 14 insertions(+)
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 2a57dbed4894..dc88d39cec1b 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -691,6 +691,15 @@ void x86_pmu_disable_all(void)
}
}
+u64 perf_get_hw_event_config(int perf_hw_id)
+{
+ if (perf_hw_id < x86_pmu.max_events)
+ return x86_pmu.event_map(perf_hw_id);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(perf_get_hw_event_config);
+
struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
{
return static_call(x86_pmu_guest_get_msrs)(nr);
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 8fc1b5003713..11a93cb1198b 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -492,9 +492,14 @@ static inline void perf_check_microcode(void) { }
#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_INTEL)
extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr);
+extern u64 perf_get_hw_event_config(int perf_hw_id);
extern int x86_perf_get_lbr(struct x86_pmu_lbr *lbr);
#else
struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr);
+u64 perf_get_hw_event_config(int perf_hw_id);
+{
+ return 0;
+}
static inline int x86_perf_get_lbr(struct x86_pmu_lbr *lbr)
{
return -1;
--
2.33.0
next prev parent reply other threads:[~2021-11-12 9:52 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-12 9:51 [PATCH 0/7] KVM: x86/pmu: Four functional fixes Like Xu
2021-11-12 9:51 ` [PATCH 1/7] KVM: x86/pmu: Make top-down.slots event unavailable in supported leaf Like Xu
2021-11-12 9:51 ` [PATCH 2/7] KVM: x86/pmu: Fix available_event_types check for REF_CPU_CYCLES event Like Xu
2021-11-12 9:51 ` [PATCH 3/7] KVM: x86/pmu: Pass "struct kvm_pmu *" to the find_fixed_event() Like Xu
2021-11-12 9:51 ` [PATCH 4/7] KVM: x86/pmu: Avoid perf_event creation for invalid counter config Like Xu
2021-11-12 9:51 ` [PATCH 5/7] KVM: x86/pmu: Refactor pmu->available_event_types field using BITMAP Like Xu
2021-11-12 9:51 ` Like Xu [this message]
2021-11-17 23:21 ` [PATCH 6/7] perf: x86/core: Add interface to query perfmon_event_map[] directly kernel test robot
2021-11-17 23:21 ` kernel test robot
2021-11-18 8:06 ` Like Xu
2021-11-18 8:06 ` Like Xu
2021-11-18 13:36 ` Like Xu
2021-11-18 13:36 ` Like Xu
2021-11-12 9:51 ` [PATCH 7/7] KVM: x86/pmu: Setup the {inte|amd}_event_mapping[] when hardware_setup Like Xu
2021-11-25 13:18 ` [KVM] 54244a5dd7: BUG:KASAN:stack-out-of-bounds_in_find_first_bit kernel test robot
2021-11-25 13:18 ` kernel test robot
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